ish: Add support for ISH chip

This patch adds the initial support for ISH chip to enable the EC
firmware to boot on Intel Integrated Sensor Hub (ISH). The following are
enabled:

1. Inter-Processor Communication (IPC) driver that enables the ISH to
communicate with the host Operating system via shared registers.
2. High Precision Event Timer (HPET) driver that provides configurable
timers for the FW to use in task scheduling.
3. I2C bus driver for accessing sensors.
4. UART console driver with TX support only.

BUG=chrome-os-partner:51851
BRANCH=None
TEST=`make buildall -j`

Change-Id: I15d4c201b799cfa79bed220ee573b75f5cd7b1f7
Signed-off-by: Jaiber John <jaiber.j.john@intel.com>
Signed-off-by: Alex Brill <alexander.brill@intel.com>
Signed-off-by: Gomathi Kumar <gomathi.kumar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/336710
Commit-Ready: Raj Mojumder <raj.mojumder@intel.com>
Tested-by: Jaiber J John <jaiber.j.john@intel.com>
Tested-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Jaiber J John <jaiber.j.john@intel.com>
Reviewed-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 79 insertions, 0 deletions

diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h
new file mode 100644
index 0000000000..ee31ccca05
--- /dev/null
+++ b/chip/ish/config_chip.h
@@ -0,0 +1,79 @@
+/* Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CONFIG_CHIP_H
+#define __CROS_EC_CONFIG_CHIP_H
+
+/* CPU core BFD configuration */
+#include "core/minute-ia/config_core.h"
+
+/* Number of IRQ vectors on the ISH */
+#define CONFIG_IRQ_COUNT	15
+
+/* Use a bigger console output buffer */
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE	2048
+
+/* Interval between HOOK_TICK notifications */
+#define HOOK_TICK_INTERVAL_MS	250
+#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
+
+/* Maximum number of deferrable functions */
+#define DEFERRABLE_MAX_COUNT	8
+
+
+/****************************************************************************/
+/* Memory mapping */
+/****************************************************************************/
+
+/* Define our SRAM layout. */
+#define CONFIG_ISH_SRAM_BASE_START	0xFF000000
+#define CONFIG_ISH_SRAM_BASE_END	0xFF0A0000
+#define CONFIG_ISH_SRAM_SIZE		(CONFIG_ISH_SRAM_BASE_END - \
+					CONFIG_ISH_SRAM_BASE_START)
+
+/* Required for panic_output */
+#define CONFIG_RAM_SIZE			CONFIG_ISH_SRAM_SIZE
+#define CONFIG_RAM_BASE			CONFIG_ISH_SRAM_BASE_START
+
+/* System stack size */
+#define CONFIG_STACK_SIZE		1024
+
+/* non-standard task stack sizes */
+#define IDLE_TASK_STACK_SIZE		640
+#define LARGER_TASK_STACK_SIZE		1024
+#define HUGE_TASK_STACK_SIZE		2048
+/* Default task stack size */
+#define TASK_STACK_SIZE			640
+
+/****************************************************************************/
+/* Define our flash layout. */
+/* Note: The 4 macros below are unnecesasry for the ISH chip. However they are
+ * referenced in common files and hence retained to avoid build errors.
+ */
+
+/* Protect bank size 4K bytes */
+#define CONFIG_FLASH_BANK_SIZE		0x00001000
+/* Sector erase size 4K bytes */
+#define CONFIG_FLASH_ERASE_SIZE		0x00000000
+/* Minimum write size */
+#define CONFIG_FLASH_WRITE_SIZE		0x00000000
+/* Program memory base address */
+#define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
+
+#include "config_flash_layout.h"
+
+/****************************************************************************/
+/* Customize the build */
+/* Optional features present on this chip */
+
+/* Note: ISH does not use the LPC bus but the protocol. */
+#define CONFIG_LPC
+
+/* GPIO - to be implemented */
+#define GPIO_PIN(index) (index)
+#define GPIO_PIN_MASK(pin, mask) ((pin), (mask))
+
+#endif  /* __CROS_EC_CONFIG_CHIP_H */