diff options
| author | Sadashiva Rao Pv <sadashiva.rao.pv@intel.com> | 2017-09-27 10:23:54 +0530 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-12-12 17:04:56 -0800 |
| commit | 80e6645b2d9876be58102c454cb0cf188f1d1eff (patch) | |
| tree | d2e3f157835473f361d5fac26a74aa4e8fe25367 /chip/ish/hpet.h | |
| parent | e95e95a0007fa8e69a002f551c31aee34ae94574 (diff) | |
| download | chrome-ec-80e6645b2d9876be58102c454cb0cf188f1d1eff.tar.gz | |
ISH3.0: Scaling timer from 12MHz to 1MHz
-Added support to scale 12MHz to 1MHz
-Fixes the timestamp issue
-Changes under CONFIG_ISH_30
ISH 3.0 has 12MHz Main counter
ISH 4.0 has 32KHz Main counter
BUG=none
BRANCH=master
TEST=On Soraka board modified for ISH, ensure
clock tick happens correctly. Ensure ISH
probe and sensor info is seen in kernel logs
Change-Id: Ib5d8a48bf99d1398a0424596399abd7df431e07a
Signed-off-by: Naresh Solakni <naresh.solanki@intel.com>
Signed-off-by: Sadashiva Rao Pv <sadashiva.rao.pv@intel.com>
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/686434
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Diffstat (limited to 'chip/ish/hpet.h')
| -rw-r--r-- | chip/ish/hpet.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h index 086adfaa88..0ad374350e 100644 --- a/chip/ish/hpet.h +++ b/chip/ish/hpet.h @@ -45,14 +45,24 @@ #define HPET_Tn_INT_ROUTE_CNF_MASK (0x1f << 9) #define HPET_GENERAL_CONFIG REG32(ISH_HPET_BASE + GENERAL_CONFIG_REG) +#if defined CONFIG_ISH_30 +#define HPET_MAIN_COUNTER_64 REG64(ISH_HPET_BASE + MAIN_COUNTER_REG) +#else #define HPET_MAIN_COUNTER REG32(ISH_HPET_BASE + MAIN_COUNTER_REG) +#endif #define HPET_INTR_CLEAR REG32(ISH_HPET_BASE + GENERAL_INT_STAT_REG) #define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + CONTROL_AND_STATUS_REG) #define HPET_TIMER_CONF_CAP(x) \ - REG32(ISH_HPET_BASE + TIMER0_CONF_CAP_REG + (x * 0x20)) + REG32(ISH_HPET_BASE + TIMER0_CONF_CAP_REG + ((x) * 0x20)) +/* HPET1/2 are 32 bit only. HPET0 is 32bit/64bit from configuration register + * HPET_TIMER_CONFIG_CAP(0) */ #define HPET_TIMER_COMP(x) \ - REG32(ISH_HPET_BASE + TIMER0_COMP_VAL_REG + (x * 0x20)) + REG32(ISH_HPET_BASE + TIMER0_COMP_VAL_REG + ((x) * 0x20)) +#if defined CONFIG_ISH_30 +#define HPET_TIMER_COMP_64(x) \ + REG64(ISH_HPET_BASE + TIMER0_COMP_VAL_REG + ((x) * 0x20)) +#endif #if defined CONFIG_ISH_20 #define ISH_HPET_CLK_FREQ 1000000 /* 1 MHz clock */ |