diff options
author | Shine Liu <shine.liu@intel.com> | 2018-12-06 16:25:55 -0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-12-18 00:42:31 -0800 |
commit | 0d28df409ea6fa112d1ffefef9e8349dd355d4fc (patch) | |
tree | 3748ffc08c29f8c930fc9da1c381bc3fd2da5d0a /chip/ish/hwtimer.c | |
parent | d352b810f72b381679839f2d60423cc5d627aaf6 (diff) | |
download | chrome-ec-0d28df409ea6fa112d1ffefef9e8349dd355d4fc.tar.gz |
chip/ish: replace CONFIG_ISH_xx flags with CHIP_FAMILY and CHIP_VARIANT
Replace all CONFIG_ISH_xx flags in chip/ish/* files with CHIP_FAMILY and
CHIP_VARIANT. Which provides more structural defines between ISH generations.
BRANCH=none
BUG=b:120295222 b:112385410
TEST=Test host FW loading for main ISH FW.
Change-Id: Ica92eee11034447c9f0828aa986fb1736d20cf27
Signed-off-by: Shine Liu <shine.liu@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1367010
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/ish/hwtimer.c')
-rw-r--r-- | chip/ish/hwtimer.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c index 1ba08f048f..960a4218ff 100644 --- a/chip/ish/hwtimer.c +++ b/chip/ish/hwtimer.c @@ -12,7 +12,7 @@ #include "task.h" #include "util.h" -#ifdef CONFIG_ISH_30 +#if defined(CHIP_FAMILY_ISH3) #define CLOCK_FACTOR 12 #endif @@ -31,7 +31,7 @@ static uint32_t last_deadline; void __hw_clock_event_set(uint32_t deadline) { last_deadline = deadline; -#ifdef CONFIG_ISH_30 +#if defined(CHIP_FAMILY_ISH3) HPET_TIMER_COMP(1) = deadline * CLOCK_FACTOR; #else HPET_TIMER_COMP(1) = deadline; @@ -51,7 +51,7 @@ void __hw_clock_event_clear(void) uint32_t __hw_clock_source_read(void) { -#ifdef CONFIG_ISH_30 +#if defined(CHIP_FAMILY_ISH3) uint64_t tmp = HPET_MAIN_COUNTER_64; uint32_t hi = tmp >> 32; uint32_t lo = tmp; @@ -67,7 +67,7 @@ uint32_t __hw_clock_source_read(void) void __hw_clock_source_set(uint32_t ts) { HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF; -#ifdef CONFIG_ISH_30 +#if defined(CHIP_FAMILY_ISH3) HPET_MAIN_COUNTER_64 = (uint64_t)ts * CLOCK_FACTOR; #else HPET_MAIN_COUNTER = ts; @@ -111,13 +111,13 @@ int __hw_clock_source_init(uint32_t start_t) /* Disable HPET */ HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF; -#ifdef CONFIG_ISH_30 +#if defined(CHIP_FAMILY_ISH3) HPET_MAIN_COUNTER_64 = (uint64_t)start_t * CLOCK_FACTOR; #else HPET_MAIN_COUNTER = start_t; #endif -#ifdef CONFIG_ISH_30 +#if defined(CHIP_FAMILY_ISH3) /* * Set comparator value. HMC will operate in 64 bit mode. * HMC is 12MHz, Hence set COMP to 12x of 1MHz. @@ -129,7 +129,7 @@ int __hw_clock_source_init(uint32_t start_t) #endif /* Timer 0 - enable periodic mode */ timer0_config |= HPET_Tn_TYPE_CNF; -#ifdef CONFIG_ISH_30 +#if defined(CHIP_FAMILY_ISH3) /* TIMER0 in 64-bit mode */ timer0_config &= ~HPET_Tn_32MODE_CNF; #else @@ -162,7 +162,7 @@ int __hw_clock_source_init(uint32_t start_t) HPET_TIMER_CONF_CAP(0) |= timer0_config; HPET_TIMER_CONF_CAP(1) |= timer1_config; -#ifdef CONFIG_ISH_40 +#if defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5) /* Wait for timer to settle. required for ISH 4 */ while (HPET_CTRL_STATUS & HPET_T_CONF_CAP_BIT) ; |