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authorHyungwoo Yang <hyungwoo.yang@intel.com>2019-01-22 15:50:42 -0800
committerchrome-bot <chrome-bot@chromium.org>2019-01-30 20:41:25 -0800
commit8eaeaa23c39159574e941381c6fd70454e1c85e7 (patch)
treead2efbf086715f74c8fd6e1131e3b28ebf9d8f5e /chip/ish/hwtimer.c
parentf3a919e2f449a65c4be223938318bf37f5164ad8 (diff)
downloadchrome-ec-8eaeaa23c39159574e941381c6fd70454e1c85e7.tar.gz
ish: fix timer 0 periodic mode
We are using timer 0 with periodic mode and in this mode, the value of timer 0 comparator should be automatically increased by the value last written when main counter equals the value. But due to mis-configuration, currently it is not automatically increased. This patch corrects the configuration for timer 0. BRANCH=none BUG=b:112750896 TEST=Tested on Atlas and verified increased value in timer 0 comparator. Change-Id: I1c98d980cd5c28226e223ca058b2181cf40b87f9 Reviewed-on: https://chromium-review.googlesource.com/1431874 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/ish/hwtimer.c')
-rw-r--r--chip/ish/hwtimer.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c
index ab393ab3c1..97a2a4f848 100644
--- a/chip/ish/hwtimer.c
+++ b/chip/ish/hwtimer.c
@@ -177,7 +177,6 @@ int __hw_clock_source_init(uint32_t start_t)
/*TIMER0 in 32-bit mode*/
timer0_config |= HPET_Tn_32MODE_CNF;
#endif
- timer0_config |= HPET_Tn_VAL_SET_CNF;
/* Timer 0 - IRQ routing, no need IRQ set for HPET0 */
timer0_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK;