diff options
author | Kyoung Kim <kyoung.il.kim@intel.com> | 2017-08-22 15:29:55 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2017-08-30 16:13:19 -0700 |
commit | c07c76e9ca83db42a9be258e95cc519dfbf768cf (patch) | |
tree | 5399a25c89890a47d039addb6e5491db22e776a2 /chip/ish/hwtimer.c | |
parent | f35ae8ab1cb26acaa6fc5a27e63568f04e22094e (diff) | |
download | chrome-ec-c07c76e9ca83db42a9be258e95cc519dfbf768cf.tar.gz |
ISH: correction for HPET1 interrupt routing
-Routing HPET1 timer requires HPET's General Config register's Legacy
routing bit should be set.
-For HPET0 interrupt, no need to set IRQ# to T0C register.
-change IRQ# back to default values.
BUG=None
BRANCH=master
TEST=`Build ISH and verify the timer interrupt via various
console cmds`
Change-Id: I9f83d62a1f7d999ebf6cedafd38691531ec91081
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/627628
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'chip/ish/hwtimer.c')
-rw-r--r-- | chip/ish/hwtimer.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c index 800b728fb7..ed34be583a 100644 --- a/chip/ish/hwtimer.c +++ b/chip/ish/hwtimer.c @@ -98,10 +98,8 @@ int __hw_clock_source_init(uint32_t start_t) timer0_config |= HPET_Tn_32MODE_CNF; timer0_config |= HPET_Tn_VAL_SET_CNF; - /* Timer 0 - IRQ routing */ + /* Timer 0 - IRQ routing, no need IRQ set for HPET0 */ timer0_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK; - timer0_config |= (ISH_HPET_TIMER0_IRQ << - HPET_Tn_INT_ROUTE_CNF_SHIFT); /* Timer 1 - IRQ routing */ timer1_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK; @@ -130,8 +128,11 @@ int __hw_clock_source_init(uint32_t start_t) ; #endif - /* Enable HPET main counter */ - HPET_GENERAL_CONFIG |= HPET_ENABLE_CNF; + /* + * LEGACY_RT_CNF for HPET1 interrupt routing + * and enable overall HPET counter/interrupts. + */ + HPET_GENERAL_CONFIG |= (HPET_ENABLE_CNF | HPET_LEGACY_RT_CNF); return ISH_HPET_TIMER1_IRQ; } |