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| author | Leifu Zhao <leifu.zhao@intel.com> | 2019-10-08 13:28:20 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-11-09 00:24:06 +0000 |
| commit | d8db28afe8e93a358ab8e9b656cfcb4f4681a222 (patch) | |
| tree | cbe6d4829f3f59ea3b3ae9558e43ed0ae764c3f2 /chip/ish/ipc_heci.c | |
| parent | b70a82f452c0f1b62bd0c7d44981b72a6924852c (diff) | |
| download | chrome-ec-d8db28afe8e93a358ab8e9b656cfcb4f4681a222.tar.gz | |
ish: chip enablement of ish5.4 on tgl rvp platform
Chip level enablement of ish5.4 on tgl rvp platform.
BUG=b:141519691
BRANCH=none
TEST=tested on tgl rvp
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I3f6249e1816d81deec0420a12b093918ee7fbddc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846788
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Diffstat (limited to 'chip/ish/ipc_heci.c')
| -rw-r--r-- | chip/ish/ipc_heci.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c index cce3298f01..5271aa3a91 100644 --- a/chip/ish/ipc_heci.c +++ b/chip/ish/ipc_heci.c @@ -459,7 +459,9 @@ static void ipc_host2ish_isr(void) if ((pisr & IPC_PISR_HOST2ISH_BIT) && (pimr & IPC_PIMR_HOST2ISH_BIT)) handle_msg_recv_interrupt(IPC_PEER_ID_HOST); } +#ifndef CONFIG_ISH_HOST2ISH_COMBINED_ISR DECLARE_IRQ(ISH_IPC_HOST2ISH_IRQ, ipc_host2ish_isr); +#endif static void ipc_host2ish_busy_clear_isr(void) { @@ -470,7 +472,18 @@ static void ipc_host2ish_busy_clear_isr(void) (pimr & IPC_PIMR_ISH2HOST_CLR_BIT)) handle_busy_clear_interrupt(IPC_PEER_ID_HOST); } +#ifndef CONFIG_ISH_HOST2ISH_COMBINED_ISR DECLARE_IRQ(ISH_IPC_ISH2HOST_CLR_IRQ, ipc_host2ish_busy_clear_isr); +#endif + +static __maybe_unused void ipc_host2ish_combined_isr(void) +{ + ipc_host2ish_isr(); + ipc_host2ish_busy_clear_isr(); +} +#ifdef CONFIG_ISH_HOST2ISH_COMBINED_ISR +DECLARE_IRQ(ISH_IPC_HOST2ISH_IRQ, ipc_host2ish_combined_isr); +#endif int ipc_write_timestamp(const ipc_handle_t handle, const void *buf, const size_t buf_size, uint32_t *timestamp) @@ -558,7 +571,8 @@ ipc_handle_t ipc_open(const enum ipc_peer_id peer_id, if (ctx->initialized == 0) { task_enable_irq(ctx->irq_in); - task_enable_irq(ctx->irq_clr); + if (!IS_ENABLED(CONFIG_ISH_HOST2ISH_COMBINED_ISR)) + task_enable_irq(ctx->irq_clr); ipc_enable_pimr_db_interrupt(ctx); ipc_enable_pimr_clearing_interrupt(ctx); |