ish: refactor IPC usage of REG macros into registers.h

This is the final CL needed to resolve b:130573158.

BUG=b:130573158
BRANCH=none
TEST=arcada_ish functions as normal after changes

Change-Id: Ia4cc9bfa95938b9f57fc1cd241cd6821b42a3ce6
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1578435
Reviewed-by: Jett Rink <jettrink@chromium.org>

1 files changed, 18 insertions, 18 deletions

diff --git a/chip/ish/ish_fwst.h b/chip/ish/ish_fwst.h
index c05caaefcb..edc347aa12 100644
--- a/chip/ish/ish_fwst.h
+++ b/chip/ish/ish_fwst.h
@@ -99,43 +99,43 @@ enum {
 /* get ISH FW status register */
 static inline uint32_t ish_fwst_get(void)
 {
-	return REG32(IPC_ISH_FWSTS);
+	return IPC_ISH_FWSTS;
 }
 
 /* set IPC link up */
 static inline void ish_fwst_set_ilup(void)
 {
-	REG32(IPC_ISH_FWSTS) |= (1<<IPC_ISH_FWSTS_ILUP_SHIFT);
+	IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_ILUP_SHIFT);
 }
 
 /* clear IPC link up */
 static inline void ish_fwst_clear_ilup(void)
 {
-	REG32(IPC_ISH_FWSTS) &= ~IPC_ISH_FWSTS_ILUP_MASK;
+	IPC_ISH_FWSTS &= ~IPC_ISH_FWSTS_ILUP_MASK;
 }
 
 /* return IPC link up state */
 static inline int ish_fwst_is_ilup_set(void)
 {
-	return !!(REG32(IPC_ISH_FWSTS) &= IPC_ISH_FWSTS_ILUP_MASK);
+	return !!(IPC_ISH_FWSTS &= IPC_ISH_FWSTS_ILUP_MASK);
 }
 
 /* set HECI up */
 static inline void ish_fwst_set_hup(void)
 {
-	REG32(IPC_ISH_FWSTS) |= (1<<IPC_ISH_FWSTS_HUP_SHIFT);
+	IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_HUP_SHIFT);
 }
 
 /* clear HECI up */
 static inline void ish_fwst_clear_hup(void)
 {
-	REG32(IPC_ISH_FWSTS) &= ~IPC_ISH_FWSTS_HUP_MASK;
+	IPC_ISH_FWSTS &= ~IPC_ISH_FWSTS_HUP_MASK;
 }
 
 /* get HECI up status */
 static inline int ish_fwst_is_hup_set(void)
 {
-	return !!(REG32(IPC_ISH_FWSTS) &= IPC_ISH_FWSTS_HUP_MASK);
+	return !!(IPC_ISH_FWSTS &= IPC_ISH_FWSTS_HUP_MASK);
 }
 
 /* set fw failure reason */
@@ -143,46 +143,46 @@ static inline void ish_fwst_set_fail_reason(uint32_t val)
 {
 	uint32_t fwst = REG32(IPC_ISH_FWSTS);
 
-	REG32(IPC_ISH_FWSTS) = (fwst & ~IPC_ISH_FWSTS_FAIL_REASON_MASK) |
-				    (val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT);
+	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FAIL_REASON_MASK) |
+		(val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT);
 }
 
 /* get fw failure reason */
 static inline uint32_t ish_fwst_get_fail_reason(void)
 {
-	return (REG32(IPC_ISH_FWSTS) & IPC_ISH_FWSTS_FAIL_REASON_MASK)
+	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK)
 		>> IPC_ISH_FWSTS_FAIL_REASON_SHIFT;
 }
 
 /* set reset id */
 static inline void ish_fwst_set_reset_id(uint32_t val)
 {
-	uint32_t fwst = REG32(IPC_ISH_FWSTS);
+	uint32_t fwst = IPC_ISH_FWSTS;
 
-	REG32(IPC_ISH_FWSTS) = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) |
-				    (val << IPC_ISH_FWSTS_RESET_ID_SHIFT);
+	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) |
+		(val << IPC_ISH_FWSTS_RESET_ID_SHIFT);
 }
 
 /* get reset id */
 static inline uint32_t ish_fwst_get_reset_id(void)
 {
-	return (REG32(IPC_ISH_FWSTS) & IPC_ISH_FWSTS_RESET_ID_MASK)
+	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK)
 		>> IPC_ISH_FWSTS_RESET_ID_SHIFT;
 }
 
 /* set general fw status */
 static inline void ish_fwst_set_fw_status(uint32_t val)
 {
-	uint32_t fwst = REG32(IPC_ISH_FWSTS);
+	uint32_t fwst = IPC_ISH_FWSTS;
 
-	REG32(IPC_ISH_FWSTS) = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) |
-				    (val << IPC_ISH_FWSTS_FW_STATUS_SHIFT);
+	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) |
+		(val << IPC_ISH_FWSTS_FW_STATUS_SHIFT);
 }
 
 /* get general fw status */
 static inline uint32_t ish_fwst_get_fw_status(void)
 {
-	return (REG32(IPC_ISH_FWSTS) & IPC_ISH_FWSTS_FW_STATUS_MASK)
+	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK)
 		>> IPC_ISH_FWSTS_FW_STATUS_SHIFT;
 }