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| author | Hu, Hebo <hebo.hu@intel.com> | 2019-03-08 15:34:21 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-04-08 02:51:29 -0700 |
| commit | 6a184d5019f0b45fe692da09a14e9ce7c853d68c (patch) | |
| tree | 541192356148342f09bacebb75bea95027e98e7d /chip/ish/power_mgt.h | |
| parent | d0a350e6691a9d93138051e2aa00e0d6c26151b5 (diff) | |
| download | chrome-ec-6a184d5019f0b45fe692da09a14e9ce7c853d68c.tar.gz | |
ish/ish5: implement AON low power management framework
AON PM framework including:
1: AON task skeleton
2: task switching between main FW and AON task
3: 'idlestats' console command for D0ix statistic information
4: D0ix entrance in idle task
BUG=b:122364080
BRANCH=none
TEST=tested on arcada
Change-Id: Iefa9e067892d5c42d9f0c795275fe88e5a36115b
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1510518
Commit-Ready: Rushikesh S Kadam <rushikesh.s.kadam@intel.com>
Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Diffstat (limited to 'chip/ish/power_mgt.h')
| -rw-r--r-- | chip/ish/power_mgt.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/chip/ish/power_mgt.h b/chip/ish/power_mgt.h new file mode 100644 index 0000000000..fe0c1b4539 --- /dev/null +++ b/chip/ish/power_mgt.h @@ -0,0 +1,43 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_POWER_MGT_H +#define __CROS_EC_POWER_MGT_H + +/* power states for ISH */ +enum { + /* D0 state: active mode */ + ISH_PM_STATE_D0 = 0, + /* sleep state: cpu halt */ + ISH_PM_STATE_D0I0, + /* deep sleep state 1: Trunk Clock Gating(TCG), cpu halt*/ + ISH_PM_STATE_D0I1, + /* deep sleep state 2: TCG, SRAM retention, cpu halt */ + ISH_PM_STATE_D0I2, + /* deep sleep state 3: TCG, SRAM power off, cpu halt*/ + ISH_PM_STATE_D0I3, + /* D3 state: power off state, on ISH5.0, can't do real power off, + * similar to D0I3, but will reset ISH + */ + ISH_PM_STATE_D3, + /* ISH received reset_prep interrupt during S0->Sx transition */ + ISH_PM_STATE_RESET_PREP, + ISH_PM_STATE_NUM +}; + +/* halt ISH cpu */ +static inline void ish_halt(void) +{ + /* make sure interrupts are enabled before halting */ + __asm__ volatile("sti;\n" + "hlt;"); +} + +/* ish low power management initialization, + * should be called at system init stage before RTOS task scheduling start + */ +void ish_pm_init(void); + +#endif /* __CROS_EC_POWER_MGT_H */ |