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| author | Leifu Zhao <leifu.zhao@intel.com> | 2020-02-14 10:53:48 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-02-27 00:29:05 +0000 |
| commit | 3f1dc59f201a5e3f52c1f0b6e72c8a166ea8dacf (patch) | |
| tree | c5a1f3b5ad72d32fb2746c00a67359aac06fcba2 /chip/ish/power_mgt.h | |
| parent | e225427d2a04449d65fbae72932caa8270f182c7 (diff) | |
| download | chrome-ec-3f1dc59f201a5e3f52c1f0b6e72c8a166ea8dacf.tar.gz | |
ish: chip level enablement for ish5.4 PM
Chip level power management enablement for ish5.4.
BUG=b:149238813
BRANCH=none
TEST=ISH can successfully enter into D0i1/D0i2/D0i3 on tgl rvp.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: Icc554a68fe57970bcaa7be457f56db34067858d9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055895
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Diffstat (limited to 'chip/ish/power_mgt.h')
| -rw-r--r-- | chip/ish/power_mgt.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/chip/ish/power_mgt.h b/chip/ish/power_mgt.h index d66bb96550..bb56191508 100644 --- a/chip/ish/power_mgt.h +++ b/chip/ish/power_mgt.h @@ -9,6 +9,10 @@ #include "common.h" #include "registers.h" +extern void uart_port_restore(void); +extern void uart_to_idle(void); +extern void clear_fabric_error(void); + /* power states for ISH */ enum ish_pm_state { /* D0 state: active mode */ |