diff options
| author | Leifu Zhao <leifu.zhao@intel.com> | 2019-10-08 13:28:20 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-11-09 00:24:06 +0000 |
| commit | d8db28afe8e93a358ab8e9b656cfcb4f4681a222 (patch) | |
| tree | cbe6d4829f3f59ea3b3ae9558e43ed0ae764c3f2 /chip/ish/registers.h | |
| parent | b70a82f452c0f1b62bd0c7d44981b72a6924852c (diff) | |
| download | chrome-ec-d8db28afe8e93a358ab8e9b656cfcb4f4681a222.tar.gz | |
ish: chip enablement of ish5.4 on tgl rvp platform
Chip level enablement of ish5.4 on tgl rvp platform.
BUG=b:141519691
BRANCH=none
TEST=tested on tgl rvp
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I3f6249e1816d81deec0420a12b093918ee7fbddc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846788
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 45 |
1 files changed, 44 insertions, 1 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index f9c4f1a272..d4ac2ea47a 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -32,6 +32,23 @@ enum ish_i2c_port { /* In ISH, the devices are mapped to pre-defined addresses in the 32-bit * linear address space. */ +#ifdef CHIP_VARIANT_ISH5P4 +#define ISH_I2C0_BASE 0x00000000 +#define ISH_I2C1_BASE 0x00002000 +#define ISH_I2C2_BASE 0x00004000 +#define ISH_UART_BASE 0x08100000 +#define ISH_GPIO_BASE 0x00100000 +#define ISH_PMU_BASE 0x04200000 +#define ISH_OCP_BASE 0xFFFFFFFF +#define ISH_MISC_BASE 0xFFFFFFFF +#define ISH_DMA_BASE 0x10100000 +#define ISH_CCU_BASE 0x04300000 +#define ISH_IPC_BASE 0x04100000 +#define ISH_WDT_BASE 0x04900000 +#define ISH_IOAPIC_BASE 0xFEC00000 +#define ISH_HPET_BASE 0x04700000 +#define ISH_LAPIC_BASE 0xFEE00000 +#else #define ISH_I2C0_BASE 0x00100000 #define ISH_I2C1_BASE 0x00102000 #define ISH_I2C2_BASE 0x00105000 @@ -47,8 +64,28 @@ enum ish_i2c_port { #define ISH_IOAPIC_BASE 0xFEC00000 #define ISH_HPET_BASE 0xFED00000 #define ISH_LAPIC_BASE 0xFEE00000 +#endif /* HW interrupt pins mapped to IOAPIC, from I/O sources */ +#ifdef CHIP_VARIANT_ISH5P4 +#define ISH_I2C0_IRQ 15 +#define ISH_I2C1_IRQ 16 +#define ISH_FABRIC_IRQ 12 +#define ISH_I2C2_IRQ 17 +#define ISH_WDT_IRQ 26 +#define ISH_GPIO_IRQ 13 +#define ISH_HPET_TIMER1_IRQ 14 +#define ISH_IPC_HOST2ISH_IRQ 0 +#define ISH_PMU_WAKEUP_IRQ 10 +#define ISH_D3_RISE_IRQ 9 +#define ISH_D3_FALL_IRQ 9 +#define ISH_BME_RISE_IRQ 9 +#define ISH_BME_FALL_IRQ 9 +#define ISH_IPC_ISH2HOST_CLR_IRQ 0 +#define ISH_UART0_IRQ 23 +#define ISH_UART1_IRQ 24 +#define ISH_RESET_PREP_IRQ 6 +#else #define ISH_I2C0_IRQ 0 #define ISH_I2C1_IRQ 1 #define ISH_FABRIC_IRQ 5 @@ -66,6 +103,7 @@ enum ish_i2c_port { #define ISH_UART0_IRQ 34 #define ISH_UART1_IRQ 35 #define ISH_RESET_PREP_IRQ 62 +#endif /* Interrupt vectors 0-31 are architecture reserved. * Vectors 32-255 are user-defined. @@ -281,7 +319,12 @@ enum ish_i2c_port { FABRIC_M_ERR_BIT) /* CSME Registers */ -#define ISH_RST_REG REG32(ISH_IPC_BASE + 0x44) +#ifdef CHIP_VARIANT_ISH5P4 +#define SEC_OFFSET 0x10000 +#else +#define SEC_OFFSET 0x0 +#endif +#define ISH_RST_REG REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44) /* IOAPIC registers */ #define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0) |