diff options
| author | Kyoung Kim <kyoung.il.kim@intel.com> | 2017-08-22 15:29:55 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-08-30 16:13:19 -0700 |
| commit | c07c76e9ca83db42a9be258e95cc519dfbf768cf (patch) | |
| tree | 5399a25c89890a47d039addb6e5491db22e776a2 /chip/ish/registers.h | |
| parent | f35ae8ab1cb26acaa6fc5a27e63568f04e22094e (diff) | |
| download | chrome-ec-c07c76e9ca83db42a9be258e95cc519dfbf768cf.tar.gz | |
ISH: correction for HPET1 interrupt routing
-Routing HPET1 timer requires HPET's General Config register's Legacy
routing bit should be set.
-For HPET0 interrupt, no need to set IRQ# to T0C register.
-change IRQ# back to default values.
BUG=None
BRANCH=master
TEST=`Build ISH and verify the timer interrupt via various
console cmds`
Change-Id: I9f83d62a1f7d999ebf6cedafd38691531ec91081
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/627628
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 32239d3975..056a4676cd 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -39,8 +39,8 @@ enum ish_i2c_port { /* HW interrupt pins mapped to IOAPIC, from I/O sources */ #define ISH_I2C0_IRQ 0 #define ISH_I2C1_IRQ 1 -#define ISH_HPET_TIMER0_IRQ 22 -#define ISH_HPET_TIMER1_IRQ 23 +#define ISH_HPET_TIMER0_IRQ 55 +#define ISH_HPET_TIMER1_IRQ 8 #define ISH_HPET_TIMER2_IRQ 11 #define ISH_IPC_HOST2ISH_IRQ 12 #define ISH_IPC_ISH2HOST_CLR_IRQ 24 |