diff options
| author | Hu, Hebo <hebo.hu@intel.com> | 2019-03-20 19:13:37 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-04-08 02:51:30 -0700 |
| commit | 014b6c86dfd1aa9ec9ffaba2647d4ca89baf1ef4 (patch) | |
| tree | 3038344894a47b863d96d266dc34a37884f0dfa1 /chip/ish/registers.h | |
| parent | 6a184d5019f0b45fe692da09a14e9ce7c853d68c (diff) | |
| download | chrome-ec-014b6c86dfd1aa9ec9ffaba2647d4ca89baf1ef4.tar.gz | |
ish/ish5: implement AON low power mode (D0i1-3)
1: D0i1(TCG) and D0i2(TCG + SRAM retention) implemented
2: D0i3 (TCG + SRAM power off) implemented
BUG=b:122364080
BRANCH=none
TEST=tested on arcada
Change-Id: I851d7c138b056a92d1616622e7cbfdfb94d86e5c
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1531772
Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index e8e9477e13..fad24b7778 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -126,6 +126,8 @@ enum ish_i2c_port { #define IPC_HOST2ISH_DOORBELL (ISH_IPC_BASE + 0x48) #define IPC_HOST2ISH_MSG_REGS (ISH_IPC_BASE + 0xE0) #define IPC_ISH2HOST_DOORBELL (ISH_IPC_BASE + 0x54) +#define IPC_ISH2PMC_DOORBELL (ISH_IPC_BASE + 0x58) +#define IPC_ISH2PMC_MSG_REGS (ISH_IPC_BASE + 0x260) #define IPC_BUSY_CLEAR (ISH_IPC_BASE + 0x378) #define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380) #define IPC_UMA_RANGE_LOWER_1 REG32(ISH_IPC_BASE + 0x384) @@ -133,6 +135,7 @@ enum ish_i2c_port { #define IPC_UMA_RANGE_UPPER_1 REG32(ISH_IPC_BASE + 0x38C) /* PMU Registers */ +#define PMU_SRAM_PG_EN REG32(ISH_PMU_BASE + 0x0) #define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c) #define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */ @@ -281,4 +284,32 @@ enum ish_i2c_port { #define LAPIC_ERR_RECV_ILLEGAL BIT(6) #define LAPIC_ICR_REG (ISH_LAPIC_BASE + 0x300) +/* SRAM control registers */ +#define ISH_SRAM_CTRL_BASE 0x00500000 +#define ISH_SRAM_CTRL_CSFGR REG32(ISH_SRAM_CTRL_BASE + 0x00) +#define ISH_SRAM_CTRL_INTR REG32(ISH_SRAM_CTRL_BASE + 0x04) +#define ISH_SRAM_CTRL_INTR_MASK REG32(ISH_SRAM_CTRL_BASE + 0x08) +#define ISH_SRAM_CTRL_ERASE_CTRL REG32(ISH_SRAM_CTRL_BASE + 0x0c) +#define ISH_SRAM_CTRL_ERASE_ADDR REG32(ISH_SRAM_CTRL_BASE + 0x10) +#define ISH_SRAM_CTRL_BANK_STATUS REG32(ISH_SRAM_CTRL_BASE + 0x2c) + +/* Software defined registers */ + +#if defined(CHIP_FAMILY_ISH3) +/* on ISH3, reused ISH2PMC IPC message registers */ +#define SNOWBALL_BASE IPC_ISH2PMC_MSG_REGS +#else +/* from ISH4, used reserved rom part of AON memory */ +#define SNOWBALL_BASE CONFIG_ISH_AON_SRAM_ROM_START +#endif + +/** + * registers about UMA/IMR DDR information and FW location in it + * ISH Bringup will set these registers' value at boot + */ +#define SNOWBALL_UMA_BASE_HI REG32(SNOWBALL_BASE + (4 * 28)) +#define SNOWBALL_UMA_BASE_LO REG32(SNOWBALL_BASE + (4 * 29)) +#define SNOWBALL_UMA_LIMIT REG32(SNOWBALL_BASE + (4 * 30)) +#define SNOWBALL_FW_OFFSET REG32(SNOWBALL_BASE + (4 * 31)) + #endif /* __CROS_EC_REGISTERS_H */ |