diff options
| author | Divagar Mohandass <divagar.mohandass@intel.com> | 2017-03-13 23:59:18 +0530 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-03-29 09:06:55 -0700 |
| commit | 598d580a63e5ee0df84196fb272c2d4643638069 (patch) | |
| tree | 5dfca5c8ffdc665008d2858ec762a73d363e76ba /chip/ish/registers.h | |
| parent | e388e9c74673d7c64cb791437858978bf2a3a142 (diff) | |
| download | chrome-ec-598d580a63e5ee0df84196fb272c2d4643638069.tar.gz | |
ISH: HPET Timer Configuration.
This change includes
- Configuring the HPET timer based on the spec
(IA-PC HPET (High Precision Event Timers) Specification 1.0a)
- Two timers used:
HPET Timer0 (free running periodic timer)
HPET Timer1 (event based non-periodic timer)
- HPET interrupts are routed to ISH via IOAPIC
- Both the timers are functional
BUG=None
BRANCH=None
TEST=`Build ISH and verify the timer interrupt via various console cmds`
Change-Id: Ib5ca24d05790868430a2cfa72ca73f5bd6a5fea3
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/453858
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index f92770ddbd..32239d3975 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -39,14 +39,14 @@ enum ish_i2c_port { /* HW interrupt pins mapped to IOAPIC, from I/O sources */ #define ISH_I2C0_IRQ 0 #define ISH_I2C1_IRQ 1 -#define ISH_HPET_TIMER1_IRQ 8 +#define ISH_HPET_TIMER0_IRQ 22 +#define ISH_HPET_TIMER1_IRQ 23 #define ISH_HPET_TIMER2_IRQ 11 #define ISH_IPC_HOST2ISH_IRQ 12 #define ISH_IPC_ISH2HOST_CLR_IRQ 24 #define ISH_UART0_IRQ 34 #define ISH_UART1_IRQ 35 #define ISH_I2C2_IRQ 40 -#define ISH_HPET_TIMER0_IRQ 55 /* Interrupt vectors 0-31 are architecture reserved. * Vectors 32-255 are user-defined. |