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author | Leifu Zhao <leifu.zhao@intel.com> | 2019-10-08 13:28:20 +0800 |
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committer | Commit Bot <commit-bot@chromium.org> | 2019-11-09 00:24:06 +0000 |
commit | d8db28afe8e93a358ab8e9b656cfcb4f4681a222 (patch) | |
tree | cbe6d4829f3f59ea3b3ae9558e43ed0ae764c3f2 /chip/ish/uart_defs.h | |
parent | b70a82f452c0f1b62bd0c7d44981b72a6924852c (diff) | |
download | chrome-ec-d8db28afe8e93a358ab8e9b656cfcb4f4681a222.tar.gz |
ish: chip enablement of ish5.4 on tgl rvp platform
Chip level enablement of ish5.4 on tgl rvp platform.
BUG=b:141519691
BRANCH=none
TEST=tested on tgl rvp
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I3f6249e1816d81deec0420a12b093918ee7fbddc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846788
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Diffstat (limited to 'chip/ish/uart_defs.h')
-rw-r--r-- | chip/ish/uart_defs.h | 172 |
1 files changed, 155 insertions, 17 deletions
diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h index ed37c47d13..b573ef7710 100644 --- a/chip/ish/uart_defs.h +++ b/chip/ish/uart_defs.h @@ -13,18 +13,20 @@ #define UART_ERROR -1 #define UART_BUSY -2 -#define HSU_BASE ISH_UART_BASE +#ifdef CHIP_VARIANT_ISH5P4 +#define UART0_OFFS (0x00) +#define UART1_OFFS (0x2000) +#define UART2_OFFS (0x4000) +#else #define UART0_OFFS (0x80) -#define UART0_BASE (ISH_UART_BASE + UART0_OFFS) -#define UART0_SIZE (0x80) - #define UART1_OFFS (0x100) -#define UART1_BASE (ISH_UART_BASE + UART1_OFFS) -#define UART1_SIZE (0x80) - #define UART2_OFFS (0x180) +#endif + +#define HSU_BASE ISH_UART_BASE +#define UART0_BASE (ISH_UART_BASE + UART0_OFFS) +#define UART1_BASE (ISH_UART_BASE + UART1_OFFS) #define UART2_BASE (ISH_UART_BASE + UART2_OFFS) -#define UART2_SIZE (0x80) #define UART_REG(size, name, n) \ REG##size(uart_ctx[n].base + \ @@ -33,22 +35,140 @@ /* Register accesses */ #define LSR(n) UART_REG(8, LSR, n) #define THR(n) UART_REG(8, THR, n) -#define FOR(n) UART_REG(32, FOR, n) #define RBR(n) UART_REG(8, RBR, n) #define DLL(n) UART_REG(8, DLL, n) #define DLH(n) UART_REG(8, DLH, n) -#define DLD(n) UART_REG(8, DLD, n) #define IER(n) UART_REG(8, IER, n) #define IIR(n) UART_REG(8, IIR, n) #define FCR(n) UART_REG(8, FCR, n) #define LCR(n) UART_REG(8, LCR, n) #define MCR(n) UART_REG(8, MCR, n) #define MSR(n) UART_REG(8, MSR, n) +#define DLF(n) UART_REG(8, DLF, n) +#define FOR(n) UART_REG(32, FOR, n) #define ABR(n) UART_REG(32, ABR, n) #define PS(n) UART_REG(32, PS, n) #define MUL(n) UART_REG(32, MUL, n) #define DIV(n) UART_REG(32, DIV, n) +#ifdef CONFIG_ISH_DW_UART +/* + * RBR: Receive Buffer register (BLAB bit = 0) + */ +#define UART_OFFSET_RBR (0x00) + +/* + * THR: Transmit Holding register (BLAB bit = 0) + */ +#define UART_OFFSET_THR (0x00) + +/* + * DLL: Divisor Latch Reg. low byte (BLAB bit = 1) + * baud rate = (serial clock freq) / (16 * divisor) + */ +#define UART_OFFSET_DLL (0x00) + +/* + * DLH: Divisor Latch Reg. high byte (BLAB bit = 1) + */ +#define UART_OFFSET_DLH (0x04) + +/* + * IER: Interrupt Enable register (BLAB bit = 0) + */ +#define UART_OFFSET_IER (0x04) + +#define IER_RECV (0x01) /* Receive Data Available */ +#define IER_TDRQ (0x02) /* Transmit Holding Register Empty */ +#define IER_LINE_STAT (0x04) /* Receiver Line Status */ +#define IER_MODEM (0x08) /* Modem Status */ +#define IER_PTIME (0x80) /* Programmable THRE Interrupt Mode Enable */ + +/* + * IIR: Interrupt ID register + */ +#define UART_OFFSET_IIR (0x08) + +#define IIR_MODEM (0x00) /* Prio: 4 */ +#define IIR_NO_INTR (0x01) +#define IIR_THRE (0x02) /* Prio: 3 */ +#define IIR_RECV_DATA (0x04) /* Prio: 2 */ +#define IIR_LINE_STAT (0x06) /* Prio: 1 */ +#define IIR_BUSY (0x07) /* Prio: 5 */ +#define IIR_TIME_OUT (0x0C) /* Prio: 2 */ +#define IIR_SOURCE (0x0F) + + +/* + * FCR: FIFO Control register (FIFO_MODE != NONE) + */ +#define UART_OFFSET_FCR (0x08) + +#define FIFO_SIZE 64 +#define FCR_FIFO_ENABLE (0x01) +#define FCR_RESET_RX (0x02) +#define FCR_RESET_TX (0x04) +#define FCR_DMA_MODE (0x08) + +/* + * LCR: Line Control register + */ +#define UART_OFFSET_LCR (0x0c) + +#define LCR_5BIT_CHR (0x00) +#define LCR_6BIT_CHR (0x01) +#define LCR_7BIT_CHR (0x02) +#define LCR_8BIT_CHR (0x03) +#define LCR_BIT_CHR_MASK (0x03) + +#define LCR_STOP BIT(2) /* 0: 1 stop bit, 1: 1.5/2 */ +#define LCR_PEN BIT(3) /* Parity Enable */ +#define LCR_EPS BIT(4) /* Even Parity Select */ +#define LCR_SP BIT(5) /* Stick Parity */ +#define LCR_BC BIT(6) /* Break Control */ +#define LCR_DLAB BIT(7) /* Divisor Latch Access */ + +/* + * MCR: Modem Control register + */ +#define UART_OFFSET_MCR (0x10) +#define MCR_DTR (0x1) /* Data terminal ready */ +#define MCR_RTS (0x2) /* Request to send */ +#define MCR_LOOP (0x10) /* LoopBack bit*/ + +#define MCR_INTR_ENABLE (0x08) /* User-designated OUT2 */ +#define MCR_AUTO_FLOW_EN (0x20) + +/* + * LSR: Line Status register + */ +#define UART_OFFSET_LSR (0x14) + +#define LSR_DR (0x01) /* Data Ready */ +#define LSR_OE (0x02) /* Overrun error */ +#define LSR_PE (0x04) /* Parity error */ +#define LSR_FE (0x08) /* Framing error */ +#define LSR_BI (0x10) /* Breaking interrupt */ +#define LSR_TDRQ (0x20) /* Transmit Holding Register Empty */ +#define LSR_TEMT (0x40) /* Transmitter empty */ + +/* + * MSR: Modem Status register + */ +#define UART_OFFSET_MSR (0x18) + +#define MSR_CTS BIT(4) /* Clear To Send signal */ + +/* + * TFL: Transmit FIFO Level + */ +#define UART_OFFSET_TFL (0x80) + +/* + * RFL: Receive FIFO Level + */ +#define UART_OFFSET_RFL (0x84) +#else /* RBR: Receive Buffer register (BLAB bit = 0) */ #define UART_OFFSET_RBR (0) /* THR: Transmit Holding register (BLAB bit = 0) */ @@ -56,10 +176,6 @@ /* IER: Interrupt Enable register (BLAB bit = 0) */ #define UART_OFFSET_IER (1) -#define FCR_FIFO_SIZE_16 (0x00) -#define FCR_FIFO_SIZE_64 (0x20) -#define FCR_ITL_FIFO_64_BYTES_1 (0x00) - /* FCR: FIFO Control register */ #define UART_OFFSET_FCR (2) #define FCR_FIFO_ENABLE BIT(0) @@ -112,9 +228,12 @@ /* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */ #define UART_OFFSET_DLH (1) +#endif -/* DLH: Divisor Latch Fractional. (BLAB bit = 1) */ -#define UART_OFFSET_DLD (2) +/* + * DLF: Divisor Latch Fraction Register + */ +#define UART_OFFSET_DLF (0xC0) /* FOR: Fifo O Register (ISH only) */ #define UART_OFFSET_FOR (0x20) @@ -132,6 +251,22 @@ #define UART_OFFSET_MUL (0x34) #define UART_OFFSET_DIV (0x38) +#define FCR_FIFO_SIZE_16 (0x00) +#define FCR_FIFO_SIZE_64 (0x20) +#define FCR_ITL_FIFO_64_BYTES_1 (0x00) + +/* tx empty trigger(TET) */ +#define FCR_TET_EMPTY (0x00) +#define FCR_TET_2CHAR (0x10) +#define FCR_TET_QTR_FULL (0x20) +#define FCR_TET_HALF_FULL (0x30) + +/* receive trigger(RT) */ +#define FCR_RT_1CHAR (0x00) +#define FCR_RT_QTR_FULL (0x40) +#define FCR_RT_HALF_FULL (0x80) +#define FCR_RT_2LESS_FULL (0xc0) + /* G_IEN: Global Interrupt Enable (ISH only) */ #define HSU_REG_GIEN REG32(HSU_BASE + 0x0) #define HSU_REG_GIST REG32(HSU_BASE + 0x4) @@ -185,7 +320,10 @@ /* KHZ, MHZ */ #define KHZ(x) ((x) * 1000) #define MHZ(x) (KHZ(x) * 1000) -#if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5) +#if defined(CHIP_VARIANT_ISH5P4) +/* Change to 100MHZ in real silicon platform */ +#define UART_ISH_INPUT_FREQ MHZ(100) +#elif defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5) #define UART_ISH_INPUT_FREQ MHZ(120) #elif defined(CHIP_FAMILY_ISH4) #define UART_ISH_INPUT_FREQ MHZ(100) |