Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-releasefirmware-fpmcu-bloonchipper-release

Generated by: ./util/update_release_branch.py --board bloonchipper
--relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware-
fpmcu-bloonchipper-release

Relevant changes:

git log --oneline e5fb0b9ba4..28712dae9d -- board/hatch_fp
board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dc3e9008b8 board/hatch_fp/board.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:246424843 b:234181908 b:244781166 b:234181908 b:244387210
BUG=b:242720240 chromium:1098010 b:180945056 b:236025198 b:234181908
BUG=b:234181908 b:237344361 b:131913998 b:236386294 b:234143158
BUG=b:234781655 b:215613183 b:242720910
TEST=`make -j buildall`
TEST=./test/run_device_tests.py --board bloonchipper
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "stm32f_rtc": PASSED
     Test "panic_data_bloonchipper_v2.0.4277": PASSED
     Test "panic_data_bloonchipper_v2.0.5938": PASSED

Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I264ad0ffe7afcd507a1e483c6e934a9c4fea47c3

1 files changed, 190 insertions, 203 deletions

diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h
index 5bfc7b9a6b..1fc36b7adc 100644
--- a/chip/ish/uart_defs.h
+++ b/chip/ish/uart_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,344 +12,331 @@
 #include <stddef.h>
 #include "atomic.h"
 
-#define UART_ERROR		-1
-#define UART_BUSY		-2
+#define UART_ERROR -1
+#define UART_BUSY -2
 #ifdef CHIP_VARIANT_ISH5P4
-#define UART0_OFFS		(0x00)
-#define UART1_OFFS		(0x2000)
-#define UART2_OFFS		(0x4000)
+#define UART0_OFFS (0x00)
+#define UART1_OFFS (0x2000)
+#define UART2_OFFS (0x4000)
 #else
-#define UART0_OFFS		(0x80)
-#define UART1_OFFS		(0x100)
-#define UART2_OFFS		(0x180)
+#define UART0_OFFS (0x80)
+#define UART1_OFFS (0x100)
+#define UART2_OFFS (0x180)
 #endif
 
-#define HSU_BASE		ISH_UART_BASE
-#define UART0_BASE		(ISH_UART_BASE + UART0_OFFS)
-#define UART1_BASE		(ISH_UART_BASE + UART1_OFFS)
-#define UART2_BASE		(ISH_UART_BASE + UART2_OFFS)
+#define HSU_BASE ISH_UART_BASE
+#define UART0_BASE (ISH_UART_BASE + UART0_OFFS)
+#define UART1_BASE (ISH_UART_BASE + UART1_OFFS)
+#define UART2_BASE (ISH_UART_BASE + UART2_OFFS)
 
-#define UART_REG(size, name, n)					\
-	REG##size(uart_ctx[n].base +					\
+#define UART_REG(size, name, n)      \
+	REG##size(uart_ctx[n].base + \
 		  UART_OFFSET_##name * uart_ctx[n].addr_interval)
 
 /* Register accesses */
-#define LSR(n)			UART_REG(8, LSR, n)
-#define THR(n)			UART_REG(8, THR, n)
-#define RBR(n)			UART_REG(8, RBR, n)
-#define DLL(n)			UART_REG(8, DLL, n)
-#define DLH(n)			UART_REG(8, DLH, n)
-#define IER(n)			UART_REG(8, IER, n)
-#define IIR(n)			UART_REG(8, IIR, n)
-#define FCR(n)			UART_REG(8, FCR, n)
-#define LCR(n)			UART_REG(8, LCR, n)
-#define MCR(n)			UART_REG(8, MCR, n)
-#define MSR(n)			UART_REG(8, MSR, n)
-#define DLF(n)			UART_REG(8, DLF, n)
-#define FOR(n)			UART_REG(32, FOR, n)
-#define ABR(n)			UART_REG(32, ABR, n)
-#define PS(n)			UART_REG(32, PS, n)
-#define MUL(n)			UART_REG(32, MUL, n)
-#define DIV(n)			UART_REG(32, DIV, n)
+#define LSR(n) UART_REG(8, LSR, n)
+#define THR(n) UART_REG(8, THR, n)
+#define RBR(n) UART_REG(8, RBR, n)
+#define DLL(n) UART_REG(8, DLL, n)
+#define DLH(n) UART_REG(8, DLH, n)
+#define IER(n) UART_REG(8, IER, n)
+#define IIR(n) UART_REG(8, IIR, n)
+#define FCR(n) UART_REG(8, FCR, n)
+#define LCR(n) UART_REG(8, LCR, n)
+#define MCR(n) UART_REG(8, MCR, n)
+#define MSR(n) UART_REG(8, MSR, n)
+#define DLF(n) UART_REG(8, DLF, n)
+#define FOR(n) UART_REG(32, FOR, n)
+#define ABR(n) UART_REG(32, ABR, n)
+#define PS(n) UART_REG(32, PS, n)
+#define MUL(n) UART_REG(32, MUL, n)
+#define DIV(n) UART_REG(32, DIV, n)
 
 #ifdef CONFIG_ISH_DW_UART
 /*
  * RBR: Receive Buffer register     (BLAB bit = 0)
  */
-#define UART_OFFSET_RBR		(0x00)
+#define UART_OFFSET_RBR (0x00)
 
 /*
  * THR: Transmit Holding register   (BLAB bit = 0)
  */
-#define UART_OFFSET_THR		(0x00)
+#define UART_OFFSET_THR (0x00)
 
 /*
  * DLL: Divisor Latch Reg. low byte  (BLAB bit = 1)
  * baud rate = (serial clock freq) / (16 * divisor)
  */
-#define UART_OFFSET_DLL		(0x00)
+#define UART_OFFSET_DLL (0x00)
 
 /*
  * DLH: Divisor Latch Reg. high byte (BLAB bit = 1)
  */
-#define UART_OFFSET_DLH		(0x04)
+#define UART_OFFSET_DLH (0x04)
 
 /*
  * IER: Interrupt Enable register   (BLAB bit = 0)
  */
-#define UART_OFFSET_IER		(0x04)
+#define UART_OFFSET_IER (0x04)
 
-#define IER_RECV		(0x01)  /* Receive Data Available */
-#define IER_TDRQ		(0x02)  /* Transmit Holding Register Empty */
-#define IER_LINE_STAT		(0x04)  /* Receiver Line Status */
-#define IER_MODEM		(0x08)  /* Modem Status */
-#define IER_PTIME		(0x80)  /* Programmable THRE Interrupt Mode Enable */
+#define IER_RECV (0x01) /* Receive Data Available */
+#define IER_TDRQ (0x02) /* Transmit Holding Register Empty */
+#define IER_LINE_STAT (0x04) /* Receiver Line Status */
+#define IER_MODEM (0x08) /* Modem Status */
+#define IER_PTIME (0x80) /* Programmable THRE Interrupt Mode Enable */
 
 /*
  * IIR: Interrupt ID register
  */
-#define UART_OFFSET_IIR		(0x08)
-
-#define IIR_MODEM		(0x00)  /* Prio: 4 */
-#define IIR_NO_INTR		(0x01)
-#define IIR_THRE		(0x02)  /* Prio: 3 */
-#define IIR_RECV_DATA		(0x04)  /* Prio: 2 */
-#define IIR_LINE_STAT		(0x06)  /* Prio: 1 */
-#define IIR_BUSY		(0x07)  /* Prio: 5 */
-#define IIR_TIME_OUT		(0x0C)  /* Prio: 2 */
-#define IIR_SOURCE		(0x0F)
+#define UART_OFFSET_IIR (0x08)
 
+#define IIR_MODEM (0x00) /* Prio: 4 */
+#define IIR_NO_INTR (0x01)
+#define IIR_THRE (0x02) /* Prio: 3 */
+#define IIR_RECV_DATA (0x04) /* Prio: 2 */
+#define IIR_LINE_STAT (0x06) /* Prio: 1 */
+#define IIR_BUSY (0x07) /* Prio: 5 */
+#define IIR_TIME_OUT (0x0C) /* Prio: 2 */
+#define IIR_SOURCE (0x0F)
 
 /*
  * FCR: FIFO Control register (FIFO_MODE != NONE)
  */
-#define UART_OFFSET_FCR		(0x08)
+#define UART_OFFSET_FCR (0x08)
 
-#define FIFO_SIZE		64
-#define FCR_FIFO_ENABLE		(0x01)
-#define FCR_RESET_RX		(0x02)
-#define FCR_RESET_TX		(0x04)
-#define FCR_DMA_MODE		(0x08)
+#define FIFO_SIZE 64
+#define FCR_FIFO_ENABLE (0x01)
+#define FCR_RESET_RX (0x02)
+#define FCR_RESET_TX (0x04)
+#define FCR_DMA_MODE (0x08)
 
 /*
  * LCR: Line Control register
  */
-#define UART_OFFSET_LCR		(0x0c)
+#define UART_OFFSET_LCR (0x0c)
 
-#define LCR_5BIT_CHR		(0x00)
-#define LCR_6BIT_CHR		(0x01)
-#define LCR_7BIT_CHR		(0x02)
-#define LCR_8BIT_CHR		(0x03)
-#define LCR_BIT_CHR_MASK	(0x03)
+#define LCR_5BIT_CHR (0x00)
+#define LCR_6BIT_CHR (0x01)
+#define LCR_7BIT_CHR (0x02)
+#define LCR_8BIT_CHR (0x03)
+#define LCR_BIT_CHR_MASK (0x03)
 
-#define LCR_STOP		BIT(2)  /* 0: 1 stop bit, 1: 1.5/2 */
-#define LCR_PEN			BIT(3)  /* Parity Enable */
-#define LCR_EPS			BIT(4)  /* Even Parity Select */
-#define LCR_SP			BIT(5)  /* Stick Parity */
-#define LCR_BC			BIT(6)  /* Break Control */
-#define LCR_DLAB		BIT(7)  /* Divisor Latch Access */
+#define LCR_STOP BIT(2) /* 0: 1 stop bit, 1: 1.5/2 */
+#define LCR_PEN BIT(3) /* Parity Enable */
+#define LCR_EPS BIT(4) /* Even Parity Select */
+#define LCR_SP BIT(5) /* Stick Parity */
+#define LCR_BC BIT(6) /* Break Control */
+#define LCR_DLAB BIT(7) /* Divisor Latch Access */
 
 /*
  * MCR: Modem Control register
  */
-#define UART_OFFSET_MCR		(0x10)
-#define MCR_DTR			(0x1)     /* Data terminal ready */
-#define MCR_RTS			(0x2)     /* Request to send */
-#define MCR_LOOP		(0x10)    /* LoopBack bit*/
+#define UART_OFFSET_MCR (0x10)
+#define MCR_DTR (0x1) /* Data terminal ready */
+#define MCR_RTS (0x2) /* Request to send */
+#define MCR_LOOP (0x10) /* LoopBack bit*/
 
-#define MCR_INTR_ENABLE		(0x08)    /* User-designated OUT2 */
-#define MCR_AUTO_FLOW_EN	(0x20)
+#define MCR_INTR_ENABLE (0x08) /* User-designated OUT2 */
+#define MCR_AUTO_FLOW_EN (0x20)
 
 /*
  * LSR: Line Status register
  */
-#define UART_OFFSET_LSR		(0x14)
+#define UART_OFFSET_LSR (0x14)
 
-#define LSR_DR			(0x01)         /* Data Ready */
-#define LSR_OE			(0x02)         /* Overrun error */
-#define LSR_PE			(0x04)         /* Parity error */
-#define LSR_FE			(0x08)         /* Framing error */
-#define LSR_BI			(0x10)         /* Breaking interrupt */
-#define LSR_TDRQ		(0x20)       /* Transmit Holding Register Empty */
-#define LSR_TEMT		(0x40)       /* Transmitter empty */
+#define LSR_DR (0x01) /* Data Ready */
+#define LSR_OE (0x02) /* Overrun error */
+#define LSR_PE (0x04) /* Parity error */
+#define LSR_FE (0x08) /* Framing error */
+#define LSR_BI (0x10) /* Breaking interrupt */
+#define LSR_TDRQ (0x20) /* Transmit Holding Register Empty */
+#define LSR_TEMT (0x40) /* Transmitter empty */
 
 /*
  * MSR: Modem Status register
  */
-#define UART_OFFSET_MSR		(0x18)
+#define UART_OFFSET_MSR (0x18)
 
-#define MSR_CTS			BIT(4) /* Clear To Send signal */
+#define MSR_CTS BIT(4) /* Clear To Send signal */
 
 /*
  * TFL: Transmit FIFO Level
  */
-#define UART_OFFSET_TFL		(0x80)
+#define UART_OFFSET_TFL (0x80)
 
 /*
  * RFL: Receive FIFO Level
  */
-#define UART_OFFSET_RFL		(0x84)
+#define UART_OFFSET_RFL (0x84)
 #else
 /* RBR: Receive Buffer register     (BLAB bit = 0)  */
-#define UART_OFFSET_RBR	(0)
+#define UART_OFFSET_RBR (0)
 /* THR: Transmit Holding register   (BLAB bit = 0)  */
-#define UART_OFFSET_THR	(0)
+#define UART_OFFSET_THR (0)
 /* IER: Interrupt Enable register   (BLAB bit = 0)  */
-#define UART_OFFSET_IER	(1)
+#define UART_OFFSET_IER (1)
 
 /* FCR: FIFO Control register */
-#define UART_OFFSET_FCR	(2)
-#define FCR_FIFO_ENABLE	BIT(0)
-#define FCR_RESET_RX		BIT(1)
-#define FCR_RESET_TX		BIT(2)
+#define UART_OFFSET_FCR (2)
+#define FCR_FIFO_ENABLE BIT(0)
+#define FCR_RESET_RX BIT(1)
+#define FCR_RESET_TX BIT(2)
 
 /* LCR: Line Control register */
-#define UART_OFFSET_LCR	(3)
-#define LCR_DLAB		(0x80)
-#define LCR_5BIT_CHR		(0x00)
-#define LCR_6BIT_CHR		(0x01)
-#define LCR_7BIT_CHR		(0x02)
-#define LCR_8BIT_CHR		(0x03)
-#define LCR_BIT_CHR_MASK	(0x03)
-#define LCR_SB			(0x40)	/* Set Break */
+#define UART_OFFSET_LCR (3)
+#define LCR_DLAB (0x80)
+#define LCR_5BIT_CHR (0x00)
+#define LCR_6BIT_CHR (0x01)
+#define LCR_7BIT_CHR (0x02)
+#define LCR_8BIT_CHR (0x03)
+#define LCR_BIT_CHR_MASK (0x03)
+#define LCR_SB (0x40) /* Set Break */
 
 /* MCR: Modem Control register */
-#define UART_OFFSET_MCR	(4)
-#define MCR_DTR		BIT(0)
-#define MCR_RTS		BIT(1)
-#define MCR_LOO		BIT(4)
-#define MCR_INTR_ENABLE	BIT(3)
-#define MCR_AUTO_FLOW_EN	BIT(5)
+#define UART_OFFSET_MCR (4)
+#define MCR_DTR BIT(0)
+#define MCR_RTS BIT(1)
+#define MCR_LOO BIT(4)
+#define MCR_INTR_ENABLE BIT(3)
+#define MCR_AUTO_FLOW_EN BIT(5)
 
 /* LSR: Line Status register */
-#define UART_OFFSET_LSR	(5)
-#define LSR_DR			BIT(0)	/* Data Ready */
-#define LSR_OE			BIT(1)	/* Overrun error */
-#define LSR_PE			BIT(2)	/* Parity error */
-#define LSR_FE			BIT(3)	/* Framing error */
-#define LSR_BI			BIT(4)	/* Breaking interrupt */
-#define LSR_THR_EMPTY		BIT(5)	/* Non FIFO mode: Transmit holding
-					 * register empty
-					 */
-#define LSR_TDRQ		BIT(5)	/* FIFO mode: Transmit Data request */
-#define LSR_TEMT		BIT(6)	/* Transmitter empty */
+#define UART_OFFSET_LSR (5)
+#define LSR_DR BIT(0) /* Data Ready */
+#define LSR_OE BIT(1) /* Overrun error */
+#define LSR_PE BIT(2) /* Parity error */
+#define LSR_FE BIT(3) /* Framing error */
+#define LSR_BI BIT(4) /* Breaking interrupt */
+#define LSR_THR_EMPTY                             \
+	BIT(5) /* Non FIFO mode: Transmit holding \
+		* register empty                  \
+		*/
+#define LSR_TDRQ BIT(5) /* FIFO mode: Transmit Data request */
+#define LSR_TEMT BIT(6) /* Transmitter empty */
 
 #define FCR_ITL_FIFO_64_BYTES_56 (BIT(6) | BIT(7))
 
-#define IER_RECV		BIT(0)
-#define IER_TDRQ		BIT(1)
-#define IER_LINE_STAT		BIT(2)
+#define IER_RECV BIT(0)
+#define IER_TDRQ BIT(1)
+#define IER_LINE_STAT BIT(2)
 
-#define UART_OFFSET_IIR	(2)
+#define UART_OFFSET_IIR (2)
 /* MSR: Modem Status register */
-#define UART_OFFSET_MSR	(6)
+#define UART_OFFSET_MSR (6)
 
 /* DLL: Divisor Latch Reg. low byte  (BLAB bit = 1) */
-#define UART_OFFSET_DLL	(0)
+#define UART_OFFSET_DLL (0)
 
 /* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */
-#define UART_OFFSET_DLH	(1)
+#define UART_OFFSET_DLH (1)
 #endif
 
 /*
  * DLF: Divisor Latch Fraction Register
  */
-#define UART_OFFSET_DLF		(0xC0)
+#define UART_OFFSET_DLF (0xC0)
 
 /* FOR: Fifo O Register (ISH only) */
-#define UART_OFFSET_FOR	(0x20)
-#define FOR_OCCUPANCY_OFFS	0
-#define FOR_OCCUPANCY_MASK	0x7F
+#define UART_OFFSET_FOR (0x20)
+#define FOR_OCCUPANCY_OFFS 0
+#define FOR_OCCUPANCY_MASK 0x7F
 
 /* ABR: Auto-Baud Control Register (ISH only) */
-#define UART_OFFSET_ABR	(0x24)
-#define ABR_UUE		BIT(4)
+#define UART_OFFSET_ABR (0x24)
+#define ABR_UUE BIT(4)
 
 /* Pre-Scalar Register (ISH only) */
-#define UART_OFFSET_PS		(0x30)
+#define UART_OFFSET_PS (0x30)
 
 /* DDS registers (ISH only) */
-#define UART_OFFSET_MUL	(0x34)
-#define UART_OFFSET_DIV	(0x38)
+#define UART_OFFSET_MUL (0x34)
+#define UART_OFFSET_DIV (0x38)
 
-#define FCR_FIFO_SIZE_16	(0x00)
-#define FCR_FIFO_SIZE_64	(0x20)
-#define FCR_ITL_FIFO_64_BYTES_1	(0x00)
+#define FCR_FIFO_SIZE_16 (0x00)
+#define FCR_FIFO_SIZE_64 (0x20)
+#define FCR_ITL_FIFO_64_BYTES_1 (0x00)
 
 /* tx empty trigger(TET) */
-#define FCR_TET_EMPTY		(0x00)
-#define FCR_TET_2CHAR		(0x10)
-#define FCR_TET_QTR_FULL	(0x20)
-#define FCR_TET_HALF_FULL	(0x30)
+#define FCR_TET_EMPTY (0x00)
+#define FCR_TET_2CHAR (0x10)
+#define FCR_TET_QTR_FULL (0x20)
+#define FCR_TET_HALF_FULL (0x30)
 
 /* receive trigger(RT) */
-#define FCR_RT_1CHAR		(0x00)
-#define FCR_RT_QTR_FULL		(0x40)
-#define FCR_RT_HALF_FULL	(0x80)
-#define FCR_RT_2LESS_FULL	(0xc0)
+#define FCR_RT_1CHAR (0x00)
+#define FCR_RT_QTR_FULL (0x40)
+#define FCR_RT_HALF_FULL (0x80)
+#define FCR_RT_2LESS_FULL (0xc0)
 
 /* G_IEN: Global Interrupt Enable  (ISH only) */
-#define HSU_REG_GIEN		REG32(HSU_BASE + 0x0)
-#define HSU_REG_GIST		REG32(HSU_BASE + 0x4)
-
-#define GIEN_PWR_MGMT		BIT(24)
-#define GIEN_DMA_EN		BIT(5)
-#define GIEN_UART2_EN		BIT(2)
-#define GIEN_UART1_EN		BIT(1)
-#define GIEN_UART0_EN		BIT(0)
-#define GIST_DMA_EN		BIT(5)
-#define GIST_UART2_EN		BIT(2)
-#define GIST_UART1_EN		BIT(1)
-#define GIST_UART0_EN		BIT(0)
-#define GIST_UARTx_EN		(GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN)
+#define HSU_REG_GIEN REG32(HSU_BASE + 0x0)
+#define HSU_REG_GIST REG32(HSU_BASE + 0x4)
+
+#define GIEN_PWR_MGMT BIT(24)
+#define GIEN_DMA_EN BIT(5)
+#define GIEN_UART2_EN BIT(2)
+#define GIEN_UART1_EN BIT(1)
+#define GIEN_UART0_EN BIT(0)
+#define GIST_DMA_EN BIT(5)
+#define GIST_UART2_EN BIT(2)
+#define GIST_UART1_EN BIT(1)
+#define GIST_UART0_EN BIT(0)
+#define GIST_UARTx_EN (GIST_UART0_EN | GIST_UART1_EN | GIST_UART2_EN)
 
 /* UART config flag, send to sc_io_control if the current UART line has HW
  * flow control lines connected.
  */
-#define UART_CONFIG_HW_FLOW_CONTROL		BIT(0)
+#define UART_CONFIG_HW_FLOW_CONTROL BIT(0)
 
 /* UART config flag for sc_io_control.  If defined a sc_io_event_rx_msg is
  * raised only when the rx buffer is completely full. Otherwise, the event
  * is raised after a timeout is received on the UART line,
  * and all data received until now is provided.
  */
-#define UART_CONFIG_DELIVER_FULL_RX_BUF	BIT(1)
+#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1)
 
 /* UART config flag for sc_io_control.  If defined a sc_io_event_rx_buf_depleted
  * is raised when all rx buffers that were added are full. Otherwise, no
  * event is raised.
  */
-#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF	BIT(2)
-
-#define UART_INT_DEVICES		3
-#define UART_EXT_DEVICES		8
-#define UART_DEVICES			UART_INT_DEVICES
-#define UART_ISH_ADDR_INTERVAL		1
-
-#define B9600				0x0000d
-#define B57600				0x00000018
-#define B115200			0x00000011
-#define B921600			0x00000012
-#define B2000000			0x00000013
-#define B3000000			0x00000014
-#define B3250000			0x00000015
-#define B3500000			0x00000016
-#define B4000000			0x00000017
-#define B19200				0x0000e
-#define B38400				0x0000f
+#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2)
+
+#define UART_INT_DEVICES 3
+#define UART_EXT_DEVICES 8
+#define UART_DEVICES UART_INT_DEVICES
+#define UART_ISH_ADDR_INTERVAL 1
+
+#define B9600 0x0000d
+#define B57600 0x00000018
+#define B115200 0x00000011
+#define B921600 0x00000012
+#define B2000000 0x00000013
+#define B3000000 0x00000014
+#define B3250000 0x00000015
+#define B3500000 0x00000016
+#define B4000000 0x00000017
+#define B19200 0x0000e
+#define B38400 0x0000f
 
 /* KHZ, MHZ */
-#define KHZ(x)				((x) * 1000)
-#define MHZ(x)				(KHZ(x) * 1000)
+#define KHZ(x) ((x)*1000)
+#define MHZ(x) (KHZ(x) * 1000)
 #if defined(CHIP_VARIANT_ISH5P4)
 /* Change to 100MHZ in real silicon platform */
-#define UART_ISH_INPUT_FREQ		MHZ(100)
+#define UART_ISH_INPUT_FREQ MHZ(100)
 #elif defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
-#define UART_ISH_INPUT_FREQ		MHZ(120)
+#define UART_ISH_INPUT_FREQ MHZ(120)
 #elif defined(CHIP_FAMILY_ISH4)
-#define UART_ISH_INPUT_FREQ		MHZ(100)
+#define UART_ISH_INPUT_FREQ MHZ(100)
 #endif
-#define UART_DEFAULT_BAUD_RATE		115200
-#define UART_STATE_CG			BIT(UART_OP_CG)
+#define UART_DEFAULT_BAUD_RATE 115200
+#define UART_STATE_CG BIT(UART_OP_CG)
 
-enum UART_PORT {
-	UART_PORT_0,
-	UART_PORT_1,
-	UART_PORT_MAX
-};
+enum UART_PORT { UART_PORT_0, UART_PORT_1, UART_PORT_MAX };
 
-enum UART_OP {
-	UART_OP_READ,
-	UART_OP_WRITE,
-	UART_OP_CG,
-	UART_OP_MAX
-};
+enum UART_OP { UART_OP_READ, UART_OP_WRITE, UART_OP_CG, UART_OP_MAX };
 
-enum {
-	BAUD_IDX,
-	BAUD_SPEED,
-	BAUD_TABLE_MAX
-};
+enum { BAUD_IDX, BAUD_SPEED, BAUD_TABLE_MAX };
 
 struct uart_ctx {
 	uint32_t id;