diff options
| author | Tom Hughes <tomhughes@chromium.org> | 2022-09-21 14:08:36 -0700 |
|---|---|---|
| committer | Tom Hughes <tomhughes@chromium.org> | 2022-09-22 12:59:38 -0700 |
| commit | c453fd704268ef72de871b0c5ac7a989de662334 (patch) | |
| tree | fcf6ce5810f9ff9e3c8cce434812dd75492269ed /chip/ish | |
| parent | 6c1587ca70f558b4f96b3f0b18ad8b027d3ba99d (diff) | |
| parent | 28712dae9d7ed1e694f7622cc083afa71090d4d5 (diff) | |
| download | chrome-ec-c453fd704268ef72de871b0c5ac7a989de662334.tar.gz | |
Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release
Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release
Relevant changes:
git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh
ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header
BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
Test "aes": PASSED
Test "cec": PASSED
Test "cortexm_fpu": PASSED
Test "crc": PASSED
Test "flash_physical": PASSED
Test "flash_write_protect": PASSED
Test "fpsensor_hw": PASSED
Test "fpsensor_spi_ro": PASSED
Test "fpsensor_spi_rw": PASSED
Test "fpsensor_uart_ro": PASSED
Test "fpsensor_uart_rw": PASSED
Test "mpu_ro": PASSED
Test "mpu_rw": PASSED
Test "mutex": PASSED
Test "pingpong": PASSED
Test "printf": PASSED
Test "queue": PASSED
Test "rollback_region0": PASSED
Test "rollback_region1": PASSED
Test "rollback_entropy": PASSED
Test "rtc": PASSED
Test "sha256": PASSED
Test "sha256_unrolled": PASSED
Test "static_if": PASSED
Test "stdlib": PASSED
Test "system_is_locked_wp_on": PASSED
Test "system_is_locked_wp_off": PASSED
Test "timer_dos": PASSED
Test "utils": PASSED
Test "utils_str": PASSED
Test "panic_data_dartmonkey_v2.0.2887": PASSED
Test "panic_data_nocturne_fp_v2.2.64": PASSED
Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7
Diffstat (limited to 'chip/ish')
38 files changed, 1314 insertions, 1420 deletions
diff --git a/chip/ish/aontaskfw/ipapg.S b/chip/ish/aontaskfw/ipapg.S index f0d3f8c554..305b9a0fb6 100755 --- a/chip/ish/aontaskfw/ipapg.S +++ b/chip/ish/aontaskfw/ipapg.S @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/ish/aontaskfw/ish_aon_defs.h b/chip/ish/aontaskfw/ish_aon_defs.h index 3cc3a491c0..0b3990100a 100644 --- a/chip/ish/aontaskfw/ish_aon_defs.h +++ b/chip/ish/aontaskfw/ish_aon_defs.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/ish/aontaskfw/ish_aon_share.h b/chip/ish/aontaskfw/ish_aon_share.h index 20b36ec2b2..b986150b73 100644 --- a/chip/ish/aontaskfw/ish_aon_share.h +++ b/chip/ish/aontaskfw/ish_aon_share.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,13 +11,12 @@ #include "power_mgt.h" /* magic ID for valid aontask image check */ -#define AON_MAGIC_ID 0x544E4F41 /*"AONT"*/ +#define AON_MAGIC_ID 0x544E4F41 /*"AONT"*/ /* aontask error code */ -#define AON_SUCCESS 0 -#define AON_ERROR_NOT_SUPPORT_POWER_MODE 1 -#define AON_ERROR_DMA_FAILED 2 - +#define AON_SUCCESS 0 +#define AON_ERROR_NOT_SUPPORT_POWER_MODE 1 +#define AON_ERROR_DMA_FAILED 2 /* shared data structure between main FW and aontask */ struct ish_aon_share { diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c index e2106abf0a..d167f3f5df 100644 --- a/chip/ish/aontaskfw/ish_aontask.c +++ b/chip/ish/aontaskfw/ish_aontask.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -64,9 +64,9 @@ * AON_IDT_ENTRY_VEC_FIRST ~ AON_IDT_ENTRY_VEC_LAST */ #ifdef CONFIG_ISH_NEW_PM -#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC +#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC #else -#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC +#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC #endif #ifdef CONFIG_ISH_PM_RESET_PREP @@ -76,16 +76,16 @@ * (if CONFIG_ISH_PM_RESET_PREP defined) */ #ifdef CONFIG_ISH_NEW_PM -#define AON_IDT_ENTRY_VEC_FIRST ISH_RESET_PREP_VEC +#define AON_IDT_ENTRY_VEC_FIRST ISH_RESET_PREP_VEC #else -#define AON_IDT_ENTRY_VEC_LAST ISH_RESET_PREP_VEC +#define AON_IDT_ENTRY_VEC_LAST ISH_RESET_PREP_VEC #endif #else /* only need handle single PMU wakeup interrupt */ #ifdef CONFIG_ISH_NEW_PM -#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC +#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC #else -#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC +#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC #endif #endif @@ -101,7 +101,7 @@ static void pmu_wakeup_isr(void) IOAPIC_EOI_REG = ISH_PMU_WAKEUP_VEC; LAPIC_EOI_REG = 0x0; - __asm__ volatile ("iret;"); + __asm__ volatile("iret;"); __builtin_unreachable(); } @@ -157,14 +157,15 @@ static void reset_prep_isr(void) * --------------------------- */ -static struct idt_entry aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST + 1]; +static struct idt_entry + aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST + 1]; static struct idt_header aon_idt_hdr = { .limit = (sizeof(struct idt_entry) * (AON_IDT_ENTRY_VEC_LAST + 1)) - 1, .entries = (struct idt_entry *)((uint32_t)&aon_idt - - (sizeof(struct idt_entry) * AON_IDT_ENTRY_VEC_FIRST)) + (sizeof(struct idt_entry) * + AON_IDT_ENTRY_VEC_FIRST)) }; /** @@ -245,13 +246,9 @@ static ldt_entry aon_ldt[2] = { * limit: 0xFFFFFFFF * flag: 0x9B, Present = 1, DPL = 0, code segment */ - { - .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, - GDT_DESC_CODE_FLAGS), + { .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, GDT_DESC_CODE_FLAGS), - .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, - GDT_DESC_CODE_FLAGS) - }, + .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, GDT_DESC_CODE_FLAGS) }, /** * entry 1 for data segment @@ -259,16 +256,11 @@ static ldt_entry aon_ldt[2] = { * limit: 0xFFFFFFFF * flag: 0x93, Present = 1, DPL = 0, data segment */ - { - .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, - GDT_DESC_DATA_FLAGS), + { .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, GDT_DESC_DATA_FLAGS), - .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, - GDT_DESC_DATA_FLAGS) - } + .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, GDT_DESC_DATA_FLAGS) } }; - /* shared data structure between main FW and aon task */ struct ish_aon_share aon_share = { .magic_id = AON_MAGIC_ID, @@ -282,15 +274,14 @@ struct ish_aon_share aon_share = { /* snowball structure */ #if defined(CHIP_FAMILY_ISH3) /* on ISH3, reused ISH2PMC IPC message registers */ -#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE +#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE #else /* from ISH4, used reserved rom part of AON memory */ -#define SNOWBALL_BASE (CONFIG_AON_PERSISTENT_BASE + 256) +#define SNOWBALL_BASE (CONFIG_AON_PERSISTENT_BASE + 256) #endif struct snowball_struct *snowball = (void *)SNOWBALL_BASE; - /* In IMR DDR, ISH FW image has a manifest header */ #define ISH_FW_IMAGE_MANIFEST_HEADER_SIZE (0x1000) @@ -324,30 +315,24 @@ static int store_main_fw(void) uint64_t imr_fw_rw_addr; imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) + - snowball->uma_base_lo + - snowball->fw_offset + + snowball->uma_base_lo + snowball->fw_offset + ISH_FW_IMAGE_MANIFEST_HEADER_SIZE); - imr_fw_rw_addr = (imr_fw_addr - + aon_share.main_fw_rw_addr - - CONFIG_RAM_BASE); + imr_fw_rw_addr = + (imr_fw_addr + aon_share.main_fw_rw_addr - CONFIG_RAM_BASE); /* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */ disable_dma_bcg(); /* store main FW's read and write data region to IMR/UMA DDR */ - ret = ish_dma_copy( - PAGING_CHAN, - imr_fw_rw_addr, - aon_share.main_fw_rw_addr, - aon_share.main_fw_rw_size, - SRAM_TO_UMA); + ret = ish_dma_copy(PAGING_CHAN, imr_fw_rw_addr, + aon_share.main_fw_rw_addr, aon_share.main_fw_rw_size, + SRAM_TO_UMA); /* enable BCG for DMA, DMA can't be accessed now */ enable_dma_bcg(); if (ret != DMA_RC_OK) { - aon_share.last_error = AON_ERROR_DMA_FAILED; aon_share.error_count++; @@ -365,31 +350,24 @@ static int restore_main_fw(void) uint64_t imr_fw_rw_addr; imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) + - snowball->uma_base_lo + - snowball->fw_offset + + snowball->uma_base_lo + snowball->fw_offset + ISH_FW_IMAGE_MANIFEST_HEADER_SIZE); - imr_fw_ro_addr = (imr_fw_addr - + aon_share.main_fw_ro_addr - - CONFIG_RAM_BASE); + imr_fw_ro_addr = + (imr_fw_addr + aon_share.main_fw_ro_addr - CONFIG_RAM_BASE); - imr_fw_rw_addr = (imr_fw_addr - + aon_share.main_fw_rw_addr - - CONFIG_RAM_BASE); + imr_fw_rw_addr = + (imr_fw_addr + aon_share.main_fw_rw_addr - CONFIG_RAM_BASE); /* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */ disable_dma_bcg(); /* restore main FW's read only code and data region from IMR/UMA DDR */ - ret = ish_dma_copy( - PAGING_CHAN, - aon_share.main_fw_ro_addr, - imr_fw_ro_addr, - aon_share.main_fw_ro_size, - UMA_TO_SRAM); + ret = ish_dma_copy(PAGING_CHAN, aon_share.main_fw_ro_addr, + imr_fw_ro_addr, aon_share.main_fw_ro_size, + UMA_TO_SRAM); if (ret != DMA_RC_OK) { - aon_share.last_error = AON_ERROR_DMA_FAILED; aon_share.error_count++; @@ -400,19 +378,14 @@ static int restore_main_fw(void) } /* restore main FW's read and write data region from IMR/UMA DDR */ - ret = ish_dma_copy( - PAGING_CHAN, - aon_share.main_fw_rw_addr, - imr_fw_rw_addr, - aon_share.main_fw_rw_size, - UMA_TO_SRAM - ); + ret = ish_dma_copy(PAGING_CHAN, aon_share.main_fw_rw_addr, + imr_fw_rw_addr, aon_share.main_fw_rw_size, + UMA_TO_SRAM); /* enable BCG for DMA, DMA can't be accessed now */ enable_dma_bcg(); if (ret != DMA_RC_OK) { - aon_share.last_error = AON_ERROR_DMA_FAILED; aon_share.error_count++; @@ -424,10 +397,10 @@ static int restore_main_fw(void) #if defined(CHIP_FAMILY_ISH3) /* on ISH3, the last SRAM bank is reserved for AON use */ -#define SRAM_POWER_OFF_BANKS (CONFIG_RAM_BANKS - 1) +#define SRAM_POWER_OFF_BANKS (CONFIG_RAM_BANKS - 1) #elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5) /* ISH4 and ISH5 have separate AON memory, can power off entire main SRAM */ -#define SRAM_POWER_OFF_BANKS CONFIG_RAM_BANKS +#define SRAM_POWER_OFF_BANKS CONFIG_RAM_BANKS #else #error "CHIP_FAMILY_ISH(3|4|5) must be defined" #endif @@ -436,33 +409,33 @@ static int restore_main_fw(void) * check SRAM bank i power gated status in PMU_SRAM_PG_EN register * 1: power gated 0: not power gated */ -#define BANK_PG_STATUS(i) (PMU_SRAM_PG_EN & (0x1 << (i))) +#define BANK_PG_STATUS(i) (PMU_SRAM_PG_EN & (0x1 << (i))) /* enable power gate of a SRAM bank */ -#define BANK_PG_ENABLE(i) (PMU_SRAM_PG_EN |= (0x1 << (i))) +#define BANK_PG_ENABLE(i) (PMU_SRAM_PG_EN |= (0x1 << (i))) /* disable power gate of a SRAM bank */ -#define BANK_PG_DISABLE(i) (PMU_SRAM_PG_EN &= ~(0x1 << (i))) +#define BANK_PG_DISABLE(i) (PMU_SRAM_PG_EN &= ~(0x1 << (i))) /** * check SRAM bank i disabled status in ISH_SRAM_CTRL_CSFGR register * 1: disabled 0: enabled */ -#define BANK_DISABLE_STATUS(i) (ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4))) +#define BANK_DISABLE_STATUS(i) (ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4))) /* enable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */ -#define BANK_ENABLE(i) (ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4))) +#define BANK_ENABLE(i) (ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4))) /* disable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */ -#define BANK_DISABLE(i) (ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4))) +#define BANK_DISABLE(i) (ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4))) /* SRAM needs time to warm up after power on */ -#define SRAM_WARM_UP_DELAY_CNT 10 +#define SRAM_WARM_UP_DELAY_CNT 10 /* SRAM needs time to enter retention mode */ -#define CYCLES_PER_US 100 -#define SRAM_RETENTION_US_DELAY 5 -#define SRAM_RETENTION_CYCLES_DELAY (SRAM_RETENTION_US_DELAY * CYCLES_PER_US) +#define CYCLES_PER_US 100 +#define SRAM_RETENTION_US_DELAY 5 +#define SRAM_RETENTION_CYCLES_DELAY (SRAM_RETENTION_US_DELAY * CYCLES_PER_US) static void sram_power(int on) { @@ -485,10 +458,9 @@ static void sram_power(int on) erase_cfg = (((bank_size - 4) >> 2) << 2) | 0x1; for (i = 0; i < SRAM_POWER_OFF_BANKS; i++) { - - if (on && (BANK_PG_STATUS(i) || (!IS_ENABLED(CONFIG_ISH_NEW_PM) - && BANK_DISABLE_STATUS(i)))) { - + if (on && + (BANK_PG_STATUS(i) || (!IS_ENABLED(CONFIG_ISH_NEW_PM) && + BANK_DISABLE_STATUS(i)))) { /* power on and enable a bank */ BANK_PG_DISABLE(i); @@ -519,13 +491,12 @@ static void sram_power(int on) * booting ISH */ ISH_SRAM_CTRL_INTR = 0xFFFFFFFF; - } } #define RTC_TICKS_IN_SECOND 32768 -static __maybe_unused uint64_t get_rtc(void) +static __maybe_unused uint64_t get_rtc(void) { uint32_t lower; uint32_t upper; @@ -645,8 +616,7 @@ static void handle_d0i2(void) } /* set main SRAM into retention mode*/ - PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT - | PMU_LDO_RETENTION_BIT; + PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT | PMU_LDO_RETENTION_BIT; /* delay some cycles before halt */ delay(SRAM_RETENTION_CYCLES_DELAY); @@ -670,7 +640,8 @@ static void handle_d0i2(void) clear_vnnred_aoncg(); - if (IS_ENABLED(CONFIG_ISH_NEW_PM) && (PMU_RST_PREP & PMU_RST_PREP_AVAIL)) + if (IS_ENABLED(CONFIG_ISH_NEW_PM) && + (PMU_RST_PREP & PMU_RST_PREP_AVAIL)) handle_reset(ISH_PM_STATE_RESET_PREP); /* set main SRAM intto normal mode */ @@ -728,7 +699,8 @@ static void handle_d0i3(void) clear_vnnred_aoncg(); - if (IS_ENABLED(CONFIG_ISH_NEW_PM) && (PMU_RST_PREP & PMU_RST_PREP_AVAIL)) + if (IS_ENABLED(CONFIG_ISH_NEW_PM) && + (PMU_RST_PREP & PMU_RST_PREP_AVAIL)) handle_reset(ISH_PM_STATE_RESET_PREP); /* power on main SRAM */ @@ -809,7 +781,6 @@ static void handle_reset(enum ish_pm_state pm_state) */ if (IS_ENABLED(CONFIG_ISH_NEW_PM) || (IPC_ISH_RMP2 & DMA_ENABLED_MASK)) { - /* clear ISH2HOST doorbell register */ *IPC_ISH2HOST_DOORBELL_ADDR = 0; @@ -834,7 +805,6 @@ static void handle_reset(enum ish_pm_state pm_state) ish_mia_halt(); } - } static void handle_unknown_state(void) @@ -847,22 +817,21 @@ static void handle_unknown_state(void) void ish_aon_main(void) { - /* set PMU wakeup interrupt gate using LDT code segment selector(0x4) */ if (IS_ENABLED(CONFIG_ISH_NEW_PM)) { - aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST].dword_lo = + aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST] + .dword_lo = GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS); - aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST].dword_up = + aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST] + .dword_up = GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS); } else { - aon_idt[0].dword_lo = GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, - IDT_DESC_FLAGS); + aon_idt[0].dword_lo = + GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS); - aon_idt[0].dword_up = GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, - IDT_DESC_FLAGS); + aon_idt[0].dword_up = + GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS); } if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) { @@ -871,39 +840,34 @@ void ish_aon_main(void) * selector(0x4) */ if (IS_ENABLED(CONFIG_ISH_NEW_PM)) { - aon_idt[0].dword_lo = GEN_IDT_DESC_LO(&reset_prep_isr, - 0x4, IDT_DESC_FLAGS); + aon_idt[0].dword_lo = GEN_IDT_DESC_LO( + &reset_prep_isr, 0x4, IDT_DESC_FLAGS); - aon_idt[0].dword_up = GEN_IDT_DESC_UP(&reset_prep_isr, - 0x4, IDT_DESC_FLAGS); + aon_idt[0].dword_up = GEN_IDT_DESC_UP( + &reset_prep_isr, 0x4, IDT_DESC_FLAGS); } else { - aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST].dword_lo = - GEN_IDT_DESC_LO(&reset_prep_isr, 0x4, - IDT_DESC_FLAGS); - - aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST].dword_up = - GEN_IDT_DESC_UP(&reset_prep_isr, 0x4, - IDT_DESC_FLAGS); + aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST] + .dword_lo = GEN_IDT_DESC_LO( + &reset_prep_isr, 0x4, IDT_DESC_FLAGS); + + aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST] + .dword_up = GEN_IDT_DESC_UP( + &reset_prep_isr, 0x4, IDT_DESC_FLAGS); } } while (1) { - /** * will start to run from here when switched to aontask from * the second time */ /* save main FW's IDT and load aontask's IDT */ - __asm__ volatile ( - "sidtl %0;\n" - "lidtl %1;\n" - : - : "m" (aon_share.main_fw_idt_hdr), - "m" (aon_idt_hdr) - ); + __asm__ volatile("sidtl %0;\n" + "lidtl %1;\n" + : + : "m"(aon_share.main_fw_idt_hdr), + "m"(aon_idt_hdr)); aon_share.last_error = AON_SUCCESS; @@ -934,11 +898,9 @@ void ish_aon_main(void) } /* restore main FW's IDT and switch back to main FW */ - __asm__ volatile( - "lidtl %0;\n" - : - : "m" (aon_share.main_fw_idt_hdr) - ); + __asm__ volatile("lidtl %0;\n" + : + : "m"(aon_share.main_fw_idt_hdr)); if (IS_ENABLED(CONFIG_ISH_IPAPG) && aon_share.pg_exit) { mainfw_gdt.entries[tr / sizeof(struct gdt_entry)] @@ -946,6 +908,6 @@ void ish_aon_main(void) pg_exit_restore_ctx(); } - __asm__ volatile ("iret;"); + __asm__ volatile("iret;"); } } diff --git a/chip/ish/aontaskfw/ish_aontask.lds.S b/chip/ish/aontaskfw/ish_aontask.lds.S index ca5f54f705..306beef5e9 100644 --- a/chip/ish/aontaskfw/ish_aontask.lds.S +++ b/chip/ish/aontaskfw/ish_aontask.lds.S @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/ish/build.mk b/chip/ish/build.mk index 8072a20791..3777f9f4ce 100644 --- a/chip/ish/build.mk +++ b/chip/ish/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2016 The Chromium OS Authors. All rights reserved. +# Copyright 2016 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/chip/ish/clock.c b/chip/ish/clock.c index ac818f5733..e46c4278b7 100644 --- a/chip/ish/clock.c +++ b/chip/ish/clock.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,8 +12,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) void clock_init(void) { diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h index 4c884d00cc..b76c302f4e 100644 --- a/chip/ish/config_chip.h +++ b/chip/ish/config_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,18 +15,18 @@ #endif /* Number of IRQ vectors on the ISH */ -#define CONFIG_IRQ_COUNT (VEC_TO_IRQ(255) + 1) +#define CONFIG_IRQ_COUNT (VEC_TO_IRQ(255) + 1) /* Use a bigger console output buffer */ #undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 +#define CONFIG_UART_TX_BUF_SIZE 2048 /* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL_MS 250 +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* Maximum number of deferrable functions */ -#define DEFERRABLE_MAX_COUNT 8 +#define DEFERRABLE_MAX_COUNT 8 /* this macro causes 'pause' and reduces loop counts inside loop. */ #define CPU_RELAX() asm volatile("rep; nop" ::: "memory") @@ -36,49 +36,48 @@ /*****************************************************************************/ #ifdef CHIP_VARIANT_ISH5P4 -#define CONFIG_RAM_BASE 0xFF200000 +#define CONFIG_RAM_BASE 0xFF200000 #else -#define CONFIG_RAM_BASE 0xFF000000 +#define CONFIG_RAM_BASE 0xFF000000 #endif -#define CONFIG_RAM_SIZE 0x000A0000 +#define CONFIG_RAM_SIZE 0x000A0000 #ifdef CHIP_VARIANT_ISH5P4 -#define CONFIG_RAM_BANK_SIZE 0x00010000 +#define CONFIG_RAM_BANK_SIZE 0x00010000 #else -#define CONFIG_RAM_BANK_SIZE 0x00008000 +#define CONFIG_RAM_BANK_SIZE 0x00008000 #endif #if defined(CHIP_FAMILY_ISH3) /* On ISH3, there is no separate AON memory; use last 4KB of SRAM */ -#define CONFIG_AON_RAM_BASE 0xFF09F000 -#define CONFIG_AON_RAM_SIZE 0x00001000 +#define CONFIG_AON_RAM_BASE 0xFF09F000 +#define CONFIG_AON_RAM_SIZE 0x00001000 #elif defined(CHIP_FAMILY_ISH4) -#define CONFIG_AON_RAM_BASE 0xFF800000 -#define CONFIG_AON_RAM_SIZE 0x00001000 +#define CONFIG_AON_RAM_BASE 0xFF800000 +#define CONFIG_AON_RAM_SIZE 0x00001000 #elif defined(CHIP_FAMILY_ISH5) -#define CONFIG_AON_RAM_BASE 0xFF800000 -#define CONFIG_AON_RAM_SIZE 0x00002000 +#define CONFIG_AON_RAM_BASE 0xFF800000 +#define CONFIG_AON_RAM_SIZE 0x00002000 #else #error "CHIP_FAMILY_ISH(3|4|5) must be defined" #endif /* The end of the AON memory is reserved for read-only use */ -#define CONFIG_AON_PERSISTENT_SIZE 0x180 -#define CONFIG_AON_PERSISTENT_BASE (CONFIG_AON_RAM_BASE \ - + CONFIG_AON_RAM_SIZE \ - - CONFIG_AON_PERSISTENT_SIZE) +#define CONFIG_AON_PERSISTENT_SIZE 0x180 +#define CONFIG_AON_PERSISTENT_BASE \ + (CONFIG_AON_RAM_BASE + CONFIG_AON_RAM_SIZE - CONFIG_AON_PERSISTENT_SIZE) /* Store persistent panic data in AON memory. */ -#define CONFIG_PANIC_DATA_BASE (&(ish_persistent_data.panic_data)) +#define CONFIG_PANIC_DATA_BASE (&(ish_persistent_data.panic_data)) /* System stack size */ -#define CONFIG_STACK_SIZE 1024 +#define CONFIG_STACK_SIZE 1024 /* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 640 -#define LARGER_TASK_STACK_SIZE 1024 -#define HUGE_TASK_STACK_SIZE 2048 +#define IDLE_TASK_STACK_SIZE 640 +#define LARGER_TASK_STACK_SIZE 1024 +#define HUGE_TASK_STACK_SIZE 2048 /* Default task stack size */ -#define TASK_STACK_SIZE 640 +#define TASK_STACK_SIZE 640 /****************************************************************************/ /* Define our flash layout. */ @@ -87,13 +86,13 @@ */ /* Protect bank size 4K bytes */ -#define CONFIG_FLASH_BANK_SIZE 0x00001000 +#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* Sector erase size 4K bytes */ -#define CONFIG_FLASH_ERASE_SIZE 0x00000000 +#define CONFIG_FLASH_ERASE_SIZE 0x00000000 /* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000000 +#define CONFIG_FLASH_WRITE_SIZE 0x00000000 /* Program memory base address */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 +#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 #include "config_flash_layout.h" @@ -101,16 +100,16 @@ /* Watchdog Timer Configuration */ /*****************************************************************************/ #if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5) -#define WDT_CLOCK_HZ (120000000) /* 120 MHz */ +#define WDT_CLOCK_HZ (120000000) /* 120 MHz */ #elif defined(CHIP_FAMILY_ISH4) -#define WDT_CLOCK_HZ (100000000) /* 100 MHz */ +#define WDT_CLOCK_HZ (100000000) /* 100 MHz */ #else #error "CHIP_FAMILY_ISH(3|4|5) must be defined" #endif /* Provide WDT vec number to Minute-IA core implementation */ #undef CONFIG_MIA_WDT_VEC -#define CONFIG_MIA_WDT_VEC ISH_WDT_VEC +#define CONFIG_MIA_WDT_VEC ISH_WDT_VEC /****************************************************************************/ /* Customize the build */ @@ -133,4 +132,4 @@ #define CONFIG_ISH_CLEAR_FABRIC_ERRORS #endif -#endif /* __CROS_EC_CONFIG_CHIP_H */ +#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/ish/config_flash_layout.h b/chip/ish/config_flash_layout.h index 9a6cc4f28b..4e4b7ad90b 100644 --- a/chip/ish/config_flash_layout.h +++ b/chip/ish/config_flash_layout.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,14 +8,14 @@ /* Mem-mapped, No external SPI for ISH */ #undef CONFIG_EXTERNAL_STORAGE -#define CONFIG_MAPPED_STORAGE -#undef CONFIG_FLASH_PSTATE +#define CONFIG_MAPPED_STORAGE +#undef CONFIG_FLASH_PSTATE #undef CONFIG_SPI_FLASH #ifdef CHIP_VARIANT_ISH5P4 -#define CONFIG_ISH_BOOT_START 0xFF200000 +#define CONFIG_ISH_BOOT_START 0xFF200000 #else -#define CONFIG_ISH_BOOT_START 0xFF000000 +#define CONFIG_ISH_BOOT_START 0xFF000000 #endif /*****************************************************************************/ @@ -24,40 +24,37 @@ * turn off SPI and flash, making these unnecessary. */ -#define CONFIG_MAPPED_STORAGE_BASE 0x0 +#define CONFIG_MAPPED_STORAGE_BASE 0x0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) +#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 /* Unused for ISH - loader is external to ISH FW */ -#define CONFIG_LOADER_MEM_OFF 0 -#define CONFIG_LOADER_SIZE 0xC00 - +#define CONFIG_LOADER_MEM_OFF 0 +#define CONFIG_LOADER_SIZE 0xC00 /* RO/RW images - not relevant for ISH */ -#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \ - CONFIG_LOADER_SIZE) -#define CONFIG_RO_SIZE (97 * 1024) -#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF -#define CONFIG_RW_SIZE CONFIG_RO_SIZE +#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + CONFIG_LOADER_SIZE) +#define CONFIG_RO_SIZE (97 * 1024) +#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF +#define CONFIG_RW_SIZE CONFIG_RO_SIZE /*****************************************************************************/ /* Not relevant for ISH */ -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240 +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 +#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240 -#define CONFIG_LOADER_STORAGE_OFF (CONFIG_BOOT_HEADER_STORAGE_OFF + \ - CONFIG_BOOT_HEADER_STORAGE_SIZE) +#define CONFIG_LOADER_STORAGE_OFF \ + (CONFIG_BOOT_HEADER_STORAGE_OFF + CONFIG_BOOT_HEADER_STORAGE_SIZE) /* RO image immediately follows the loader image */ -#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + \ - CONFIG_LOADER_SIZE) +#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + CONFIG_LOADER_SIZE) /* RW image starts at the beginning of SPI */ -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ diff --git a/chip/ish/dma.c b/chip/ish/dma.c index b9744fd234..48a27a0463 100644 --- a/chip/ish/dma.c +++ b/chip/ish/dma.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -112,8 +112,8 @@ int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length, mode |= NON_SNOOP; MISC_DMA_CTL_REG(chan) = mode; /* Set transfer direction */ - DMA_CFG_REG = DMA_ENABLE; /* Enable DMA module */ - DMA_LLP(chan_reg) = 0; /* Linked lists are not used */ + DMA_CFG_REG = DMA_ENABLE; /* Enable DMA module */ + DMA_LLP(chan_reg) = 0; /* Linked lists are not used */ DMA_CTL_LOW(chan_reg) = 0 /* Set transfer parameters */ | (DMA_CTL_TT_FC_M2M_DMAC << DMA_CTL_TT_FC_SHIFT) | @@ -126,24 +126,27 @@ int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length, interrupt_unlock(eflags); while (length) { - chunk = (length > DMA_MAX_BLOCK_SIZE) ? DMA_MAX_BLOCK_SIZE - : length; + chunk = (length > DMA_MAX_BLOCK_SIZE) ? DMA_MAX_BLOCK_SIZE : + length; if (rc != DMA_RC_OK) break; eflags = interrupt_lock(); MISC_CHID_CFG_REG = chan; /* Set channel to configure */ - DMA_CTL_HIGH(chan_reg) = - chunk; /* Set number of bytes to transfer */ + DMA_CTL_HIGH(chan_reg) = chunk; /* Set number of bytes to + transfer */ DMA_DAR(chan_reg) = dst; /* Destination address */ DMA_SAR(chan_reg) = src; /* Source address */ DMA_EN_REG = DMA_CH_EN_BIT(chan) | - DMA_CH_EN_WE_BIT(chan); /* Enable the channel */ + DMA_CH_EN_WE_BIT(chan); /* Enable + the + channel + */ interrupt_unlock(eflags); - rc = ish_wait_for_dma_done( - chan); /* Wait for trans completion */ + rc = ish_wait_for_dma_done(chan); /* Wait for trans completion + */ dst += chunk; src += chunk; diff --git a/chip/ish/flash.c b/chip/ish/flash.c index 2a1b9c0793..c9c4a132d9 100644 --- a/chip/ish/flash.c +++ b/chip/ish/flash.c @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,7 +6,6 @@ #include "common.h" #include "flash.h" - /** * Initialize the module. * diff --git a/chip/ish/gpio.c b/chip/ish/gpio.c index 6c7a27e1e7..287e7a375b 100644 --- a/chip/ish/gpio.c +++ b/chip/ish/gpio.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -24,7 +24,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal) if (g->port == UNIMPLEMENTED_GPIO_BANK) return 0; - return !!(ISH_GPIO_GPLR & g->mask); + return !!(ISH_GPIO_GPLR & g->mask); } void gpio_set_level(enum gpio_signal signal, int value) @@ -55,8 +55,8 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) } /* ISH 3 can't support both rising and falling edge */ - if (IS_ENABLED(CHIP_FAMILY_ISH3) && - (flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) { + if (IS_ENABLED(CHIP_FAMILY_ISH3) && (flags & GPIO_INT_F_RISING) && + (flags & GPIO_INT_F_FALLING)) { ccprintf("\n\nISH 2/3 does not support both rising & falling " "edge for %d 0x%02x\n\n", port, mask); @@ -65,7 +65,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* GPSR/GPCR Output high/low */ if (flags & GPIO_HIGH) /* Output high */ ISH_GPIO_GPSR |= mask; - else if (flags & GPIO_LOW) /* output low */ + else if (flags & GPIO_LOW) /* output low */ ISH_GPIO_GPCR |= mask; /* GPDR pin direction 1 = output, 0 = input*/ @@ -123,7 +123,6 @@ void gpio_pre_init(void) const struct gpio_info *g = gpio_list; for (i = 0; i < GPIO_COUNT; i++, g++) { - flags = g->flags; if (flags & GPIO_DEFAULT) diff --git a/chip/ish/hbm.h b/chip/ish/hbm.h index edfb587d21..d666f748c8 100644 --- a/chip/ish/hbm.h +++ b/chip/ish/hbm.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,65 +11,64 @@ #include "heci_client.h" -#define HBM_MAJOR_VERSION 1 +#define HBM_MAJOR_VERSION 1 #ifdef HECI_ENABLE_DMA -#define HBM_MINOR_VERSION 2 +#define HBM_MINOR_VERSION 2 #else -#define HBM_MINOR_VERSION 0 +#define HBM_MINOR_VERSION 0 #endif #define __packed __attribute__((packed)) -#define HECI_MSG_REPONSE_FLAG 0x80 +#define HECI_MSG_REPONSE_FLAG 0x80 enum HECI_BUS_MSG { /* requests */ - HECI_BUS_MSG_VERSION_REQ = 1, - HECI_BUS_MSG_HOST_STOP_REQ = 2, - HECI_BUS_MSG_ME_STOP_REQ = 3, - HECI_BUS_MSG_HOST_ENUM_REQ = 4, - HECI_BUS_MSG_HOST_CLIENT_PROP_REQ = 5, - HECI_BUS_MSG_CLIENT_CONNECT_REQ = 6, - HECI_BUS_MSG_CLIENT_DISCONNECT_REQ = 7, - HECI_BUS_MSG_FLOW_CONTROL = 8, - HECI_BUS_MSG_RESET_REQ = 9, - HECI_BUS_MSG_ADD_CLIENT_REQ = 0x0A, - HECI_BUS_MSG_DMA_REQ = 0x10, - HECI_BUS_MSG_DMA_ALLOC_NOTIFY = 0x11, - HECI_BUS_MSG_DMA_XFER_REQ = 0x12, + HECI_BUS_MSG_VERSION_REQ = 1, + HECI_BUS_MSG_HOST_STOP_REQ = 2, + HECI_BUS_MSG_ME_STOP_REQ = 3, + HECI_BUS_MSG_HOST_ENUM_REQ = 4, + HECI_BUS_MSG_HOST_CLIENT_PROP_REQ = 5, + HECI_BUS_MSG_CLIENT_CONNECT_REQ = 6, + HECI_BUS_MSG_CLIENT_DISCONNECT_REQ = 7, + HECI_BUS_MSG_FLOW_CONTROL = 8, + HECI_BUS_MSG_RESET_REQ = 9, + HECI_BUS_MSG_ADD_CLIENT_REQ = 0x0A, + HECI_BUS_MSG_DMA_REQ = 0x10, + HECI_BUS_MSG_DMA_ALLOC_NOTIFY = 0x11, + HECI_BUS_MSG_DMA_XFER_REQ = 0x12, /* responses */ - HECI_BUS_MSG_VERSION_RESP = + HECI_BUS_MSG_VERSION_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_VERSION_REQ), - HECI_BUS_MSG_HOST_STOP_RESP = + HECI_BUS_MSG_HOST_STOP_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_STOP_REQ), - HECI_BUS_MSG_HOST_ENUM_RESP = + HECI_BUS_MSG_HOST_ENUM_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_ENUM_REQ), - HECI_BUS_MSG_HOST_CLIENT_PROP_RESP = + HECI_BUS_MSG_HOST_CLIENT_PROP_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_CLIENT_PROP_REQ), - HECI_BUS_MSG_CLIENT_CONNECT_RESP = + HECI_BUS_MSG_CLIENT_CONNECT_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_CONNECT_REQ), - HECI_BUS_MSG_CLIENT_DISCONNECT_RESP = + HECI_BUS_MSG_CLIENT_DISCONNECT_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_DISCONNECT_REQ), - HECI_BUS_MSG_RESET_RESP = + HECI_BUS_MSG_RESET_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_RESET_REQ), - HECI_BUS_MSG_ADD_CLIENT_RESP = + HECI_BUS_MSG_ADD_CLIENT_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_ADD_CLIENT_REQ), - HECI_BUS_MSG_DMA_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_REQ), - HECI_BUS_MSG_DMA_ALLOC_RESP = + HECI_BUS_MSG_DMA_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_REQ), + HECI_BUS_MSG_DMA_ALLOC_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_ALLOC_NOTIFY), - HECI_BUS_MSG_DMA_XFER_RESP = + HECI_BUS_MSG_DMA_XFER_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_XFER_REQ) }; enum { - HECI_CONNECT_STATUS_SUCCESS = 0, - HECI_CONNECT_STATUS_CLIENT_NOT_FOUND = 1, - HECI_CONNECT_STATUS_ALREADY_EXISTS = 2, - HECI_CONNECT_STATUS_REJECTED = 3, + HECI_CONNECT_STATUS_SUCCESS = 0, + HECI_CONNECT_STATUS_CLIENT_NOT_FOUND = 1, + HECI_CONNECT_STATUS_ALREADY_EXISTS = 2, + HECI_CONNECT_STATUS_REJECTED = 3, HECI_CONNECT_STATUS_INVALID_PARAMETER = 4, - HECI_CONNECT_STATUS_INACTIVE_CLIENT = 5, + HECI_CONNECT_STATUS_INACTIVE_CLIENT = 5, }; struct hbm_version { @@ -101,14 +100,14 @@ struct hbm_client_prop_req { uint8_t reserved[2]; } __packed; -#define CLIENT_DMA_ENABLE 0x80 +#define CLIENT_DMA_ENABLE 0x80 struct hbm_client_properties { struct heci_guid protocol_name; /* heci client protocol ID */ - uint8_t protocol_version; /* protocol version */ + uint8_t protocol_version; /* protocol version */ /* max connection from host to client. currently only 1 is allowed */ uint8_t max_number_of_connections; - uint8_t fixed_address; /* not yet supported */ + uint8_t fixed_address; /* not yet supported */ uint8_t single_recv_buf; /* not yet supported */ uint32_t max_msg_length; /* max payload size */ /* not yet supported. [7] enable/disable, [6:0] dma length */ @@ -168,13 +167,13 @@ struct hbm_host_stop_res { struct hbm_h2i { uint8_t cmd; union { - struct hbm_version_req ver_req; - struct hbm_enum_req enum_req; - struct hbm_client_prop_req client_prop_req; - struct hbm_client_connect_req client_connect_req; - struct hbm_flow_control flow_ctrl; - struct hbm_client_disconnect_req client_disconnect_req; - struct hbm_host_stop_req host_stop_req; + struct hbm_version_req ver_req; + struct hbm_enum_req enum_req; + struct hbm_client_prop_req client_prop_req; + struct hbm_client_connect_req client_connect_req; + struct hbm_flow_control flow_ctrl; + struct hbm_client_disconnect_req client_disconnect_req; + struct hbm_host_stop_req host_stop_req; } data; } __packed; @@ -182,13 +181,13 @@ struct hbm_h2i { struct hbm_i2h { uint8_t cmd; union { - struct hbm_version_res ver_res; - struct hbm_enum_res enum_res; - struct hbm_client_prop_res client_prop_res; - struct hbm_client_connect_res client_connect_res; - struct hbm_flow_control flow_ctrl; - struct hbm_client_disconnect_res client_disconnect_res; - struct hbm_host_stop_res host_stop_res; + struct hbm_version_res ver_res; + struct hbm_enum_res enum_res; + struct hbm_client_prop_res client_prop_res; + struct hbm_client_connect_res client_connect_res; + struct hbm_flow_control flow_ctrl; + struct hbm_client_disconnect_res client_disconnect_res; + struct hbm_host_stop_res host_stop_res; } data; } __packed; diff --git a/chip/ish/heci.c b/chip/ish/heci.c index 4a9bc9551b..6f99a486e7 100644 --- a/chip/ish/heci.c +++ b/chip/ish/heci.c @@ -1,9 +1,10 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ #include "atomic.h" +#include "builtin/assert.h" #include "compile_time_macros.h" #include "console.h" #include "hbm.h" @@ -15,19 +16,19 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) struct heci_header { uint8_t fw_addr; uint8_t host_addr; uint16_t length; /* [8:0] length, [14:9] reserved, [15] msg_complete */ } __packed; -#define HECI_MSG_CMPL_SHIFT 15 -#define HECI_MSG_LENGTH_MASK 0x01FF -#define HECI_MSG_LENGTH(length) ((length) & HECI_MSG_LENGTH_MASK) +#define HECI_MSG_CMPL_SHIFT 15 +#define HECI_MSG_LENGTH_MASK 0x01FF +#define HECI_MSG_LENGTH(length) ((length)&HECI_MSG_LENGTH_MASK) #define HECI_MSG_IS_COMPLETED(length) \ - (!!((length) & (0x01 << HECI_MSG_CMPL_SHIFT))) + (!!((length) & (0x01 << HECI_MSG_CMPL_SHIFT))) BUILD_ASSERT(HECI_IPC_PAYLOAD_SIZE == (IPC_MAX_PAYLOAD_SIZE - sizeof(struct heci_header))); @@ -38,26 +39,26 @@ struct heci_msg { } __packed; /* HECI addresses */ -#define HECI_HBM_ADDRESS 0 /* HECI Bus Message */ -#define HECI_DYN_CLIENT_ADDR_START 0x20 /* Dynamic client start addr */ +#define HECI_HBM_ADDRESS 0 /* HECI Bus Message */ +#define HECI_DYN_CLIENT_ADDR_START 0x20 /* Dynamic client start addr */ /* A fw client has the same value for both handle and fw address */ -#define TO_FW_ADDR(handle) ((uintptr_t)(handle)) -#define TO_HECI_HANDLE(fw_addr) ((heci_handle_t)(uintptr_t)(fw_addr)) +#define TO_FW_ADDR(handle) ((uintptr_t)(handle)) +#define TO_HECI_HANDLE(fw_addr) ((heci_handle_t)(uintptr_t)(fw_addr)) /* convert client fw address to client context index */ -#define TO_CLIENT_CTX_IDX(fw_addr) ((fw_addr) - HECI_DYN_CLIENT_ADDR_START) +#define TO_CLIENT_CTX_IDX(fw_addr) ((fw_addr)-HECI_DYN_CLIENT_ADDR_START) /* should be less than HECI_INVALID_HANDLE - 1 */ BUILD_ASSERT(HECI_MAX_NUM_OF_CLIENTS < 0x0FE); struct heci_client_connect { - uint8_t is_connected; /* client is connected to host */ - uint8_t host_addr; /* connected host address */ + uint8_t is_connected; /* client is connected to host */ + uint8_t host_addr; /* connected host address */ /* receiving message */ uint8_t ignore_rx_msg; - uint8_t rx_msg[HECI_MAX_MSG_SIZE]; - size_t rx_msg_length; + uint8_t rx_msg[HECI_MAX_MSG_SIZE]; + size_t rx_msg_length; uint32_t flow_ctrl_creds; /* flow control */ struct mutex lock; /* protects against 2 writers */ @@ -67,7 +68,7 @@ struct heci_client_connect { struct heci_client_context { const struct heci_client *client; - void *data; /* client specific data */ + void *data; /* client specific data */ struct heci_client_connect connect; /* connection context */ struct ss_subsys_device ss_device; /* system state receiver device */ @@ -82,7 +83,7 @@ struct heci_bus_context { /* declare heci bus */ struct heci_bus_context heci_bus_ctx = { - .ipc_handle = IPC_INVALID_HANDLE, + .ipc_handle = IPC_INVALID_HANDLE, }; static inline struct heci_client_context * @@ -118,11 +119,14 @@ static inline int heci_is_valid_handle(const heci_handle_t handle) /* find heci device that contains this system state device in it */ #define ss_device_to_heci_client_context(ss_dev) \ - ((struct heci_client_context *)((void *)(ss_dev) - \ - (void *)(&(((struct heci_client_context *)0)->ss_device)))) -#define client_context_to_handle(cli_ctx) \ - ((heci_handle_t)((uint32_t)((cli_ctx) - &heci_bus_ctx.client_ctxs[0]) \ - / sizeof(heci_bus_ctx.client_ctxs[0]) + 1)) + ((struct heci_client_context \ + *)((void *)(ss_dev) - \ + (void *)(&( \ + ((struct heci_client_context *)0)->ss_device)))) +#define client_context_to_handle(cli_ctx) \ + ((heci_handle_t)((uint32_t)((cli_ctx) - &heci_bus_ctx.client_ctxs[0]) / \ + sizeof(heci_bus_ctx.client_ctxs[0]) + \ + 1)) /* * each heci device registered as system state device which gets @@ -132,7 +136,7 @@ static inline int heci_is_valid_handle(const heci_handle_t handle) static int heci_client_suspend(struct ss_subsys_device *ss_device) { struct heci_client_context *cli_ctx = - ss_device_to_heci_client_context(ss_device); + ss_device_to_heci_client_context(ss_device); heci_handle_t handle = client_context_to_handle(cli_ctx); if (cli_ctx->client->cbs->suspend) @@ -144,7 +148,7 @@ static int heci_client_suspend(struct ss_subsys_device *ss_device) static int heci_client_resume(struct ss_subsys_device *ss_device) { struct heci_client_context *cli_ctx = - ss_device_to_heci_client_context(ss_device); + ss_device_to_heci_client_context(ss_device); heci_handle_t handle = client_context_to_handle(cli_ctx); if (cli_ctx->client->cbs->resume) @@ -239,8 +243,8 @@ static int heci_send_heci_msg_timestamp(struct heci_msg *msg, timestamp); if (written != length) { - CPRINTF("%s error : len = %d err = %d\n", __func__, - (int)length, written); + CPRINTF("%s error : len = %d err = %d\n", __func__, (int)length, + written); return -EC_ERROR_UNKNOWN; } @@ -381,7 +385,6 @@ int heci_send_msg(const heci_handle_t handle, uint8_t *buf, return heci_send_msg_timestamp(handle, buf, buf_size, NULL); } - int heci_send_msgs(const heci_handle_t handle, const struct heci_msg_list *msg_list) { @@ -453,8 +456,8 @@ int heci_send_msgs(const heci_handle_t handle, /* no leftovers, send the last msg here */ if (msg_sent == total_size) { - msg.hdr.length |= - (uint16_t)1 << HECI_MSG_CMPL_SHIFT; + msg.hdr.length |= (uint16_t)1 + << HECI_MSG_CMPL_SHIFT; } heci_send_heci_msg(&msg); @@ -488,7 +491,6 @@ err_locked: mutex_unlock(&connect->lock); return total_size; - } /* For now, we only support fixed client payload size < IPC payload size */ @@ -535,9 +537,9 @@ static int handle_version_req(struct hbm_version_req *ver_req) return EC_SUCCESS; } -#define BITS_PER_BYTE 8 +#define BITS_PER_BYTE 8 /* get number of bits for one element of "valid_addresses" array */ -#define BITS_PER_ELEMENT \ +#define BITS_PER_ELEMENT \ (sizeof(((struct hbm_enum_res *)0)->valid_addresses[0]) * BITS_PER_BYTE) static int handle_enum_req(struct hbm_enum_req *enum_req) @@ -604,11 +606,11 @@ static int handle_client_prop_req(struct hbm_client_prop_req *client_prop_req) client_prop->protocol_name = client->protocol_id; client_prop->protocol_version = client->protocol_ver; client_prop->max_number_of_connections = - client->max_n_of_connections; + client->max_n_of_connections; client_prop->max_msg_length = client->max_msg_size; client_prop->dma_hdr_len = client->dma_header_length; - client_prop->dma_hdr_len |= client->dma_enabled ? - CLIENT_DMA_ENABLE : 0; + client_prop->dma_hdr_len |= + client->dma_enabled ? CLIENT_DMA_ENABLE : 0; } heci_send_heci_msg(&heci_msg); @@ -642,8 +644,8 @@ static int heci_send_flow_control(uint8_t fw_addr) return EC_SUCCESS; } -static int handle_client_connect_req( - struct hbm_client_connect_req *client_connect_req) +static int +handle_client_connect_req(struct hbm_client_connect_req *client_connect_req) { struct hbm_client_connect_res *client_connect_res; struct heci_msg heci_msg; @@ -663,7 +665,7 @@ static int handle_client_connect_req( client_connect_res->host_addr = client_connect_req->host_addr; if (!heci_is_valid_client_addr(client_connect_req->fw_addr)) { client_connect_res->status = - HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; + HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; } else if (!client_connect_req->host_addr) { client_connect_res->status = HECI_CONNECT_STATUS_INVALID_PARAMETER; @@ -671,7 +673,7 @@ static int handle_client_connect_req( connect = heci_get_client_connect(client_connect_req->fw_addr); if (connect->is_connected) { client_connect_res->status = - HECI_CONNECT_STATUS_ALREADY_EXISTS; + HECI_CONNECT_STATUS_ALREADY_EXISTS; } else { connect->is_connected = 1; connect->host_addr = client_connect_req->host_addr; @@ -729,8 +731,7 @@ static void heci_handle_client_msg(struct heci_msg *msg, size_t length) connect = &cli_ctx->connect; payload_size = HECI_MSG_LENGTH(msg->hdr.length); - if (connect->is_connected && - msg->hdr.host_addr == connect->host_addr) { + if (connect->is_connected && msg->hdr.host_addr == connect->host_addr) { if (!connect->ignore_rx_msg && connect->rx_msg_length + payload_size > HECI_MAX_MSG_SIZE) { connect->ignore_rx_msg = 1; /* too big. discard */ @@ -760,7 +761,7 @@ static void heci_handle_client_msg(struct heci_msg *msg, size_t length) } static int handle_client_disconnect_req( - struct hbm_client_disconnect_req *client_disconnect_req) + struct hbm_client_disconnect_req *client_disconnect_req) { struct hbm_client_disconnect_res *client_disconnect_res; struct heci_msg heci_msg; @@ -772,8 +773,9 @@ static int handle_client_disconnect_req( CPRINTS("Got HECI disconnect request"); - heci_build_hbm_header(&heci_msg.hdr, sizeof(i2h->cmd) + - sizeof(*client_disconnect_res)); + heci_build_hbm_header(&heci_msg.hdr, + sizeof(i2h->cmd) + + sizeof(*client_disconnect_res)); i2h = (struct hbm_i2h *)heci_msg.payload; i2h->cmd = HECI_BUS_MSG_CLIENT_DISCONNECT_RESP; @@ -789,7 +791,7 @@ static int handle_client_disconnect_req( if (!heci_is_valid_client_addr(fw_addr) || !heci_is_client_connected(fw_addr)) { client_disconnect_res->status = - HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; + HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; } else { connect = heci_get_client_connect(fw_addr); if (connect->host_addr != host_addr) { @@ -891,8 +893,8 @@ static int is_hbm_validity(struct hbm_h2i *h2i, size_t length) } if (valid_msg_len != length) { - CPRINTF("invalid cmd(%d) valid : %d, cur : %zd\n", - h2i->cmd, valid_msg_len, length); + CPRINTF("invalid cmd(%d) valid : %d, cur : %zd\n", h2i->cmd, + valid_msg_len, length); /* TODO: invalid cmd. not sure to reply with error ? */ return 0; } @@ -922,7 +924,7 @@ static void heci_handle_hbm(struct hbm_h2i *h2i, size_t length) case HECI_BUS_MSG_CLIENT_CONNECT_REQ: handle_client_connect_req( - (struct hbm_client_connect_req *)data); + (struct hbm_client_connect_req *)data); break; case HECI_BUS_MSG_FLOW_CONTROL: @@ -931,7 +933,7 @@ static void heci_handle_hbm(struct hbm_h2i *h2i, size_t length) case HECI_BUS_MSG_CLIENT_DISCONNECT_REQ: handle_client_disconnect_req( - (struct hbm_client_disconnect_req *)data); + (struct hbm_client_disconnect_req *)data); break; case HECI_BUS_MSG_HOST_STOP_REQ: @@ -991,7 +993,7 @@ static void heci_handle_heci_msg(struct heci_msg *heci_msg, size_t msg_length) } /* event flag for HECI msg */ -#define EVENT_FLAG_BIT_HECI_MSG TASK_EVENT_CUSTOM_BIT(0) +#define EVENT_FLAG_BIT_HECI_MSG TASK_EVENT_CUSTOM_BIT(0) void heci_rx_task(void) { @@ -1017,8 +1019,9 @@ void heci_rx_task(void) continue; } - if (HECI_MSG_LENGTH(heci_msg.hdr.length) + sizeof(heci_msg.hdr) - == msg_len) + if (HECI_MSG_LENGTH(heci_msg.hdr.length) + + sizeof(heci_msg.hdr) == + msg_len) heci_handle_heci_msg(&heci_msg, msg_len); else CPRINTS("msg len mismatch.. discard.."); diff --git a/chip/ish/heci_client.h b/chip/ish/heci_client.h index 9dca4bff90..951b82c6d9 100644 --- a/chip/ish/heci_client.h +++ b/chip/ish/heci_client.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,21 +11,21 @@ #include "hooks.h" -#define HECI_MAX_NUM_OF_CLIENTS 2 +#define HECI_MAX_NUM_OF_CLIENTS 2 -#define HECI_MAX_MSG_SIZE 4960 -#define HECI_IPC_PAYLOAD_SIZE (IPC_MAX_PAYLOAD_SIZE - 4) -#define HECI_MAX_MSGS 3 +#define HECI_MAX_MSG_SIZE 4960 +#define HECI_IPC_PAYLOAD_SIZE (IPC_MAX_PAYLOAD_SIZE - 4) +#define HECI_MAX_MSGS 3 enum HECI_ERR { - HECI_ERR_TOO_MANY_MSG_ITEMS = EC_ERROR_INTERNAL_FIRST + 0, - HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST = EC_ERROR_INTERNAL_FIRST + 1, - HECI_ERR_CLIENT_IS_NOT_CONNECTED = EC_ERROR_INTERNAL_FIRST + 2, + HECI_ERR_TOO_MANY_MSG_ITEMS = EC_ERROR_INTERNAL_FIRST + 0, + HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST = EC_ERROR_INTERNAL_FIRST + 1, + HECI_ERR_CLIENT_IS_NOT_CONNECTED = EC_ERROR_INTERNAL_FIRST + 2, }; -typedef void * heci_handle_t; +typedef void *heci_handle_t; -#define HECI_INVALID_HANDLE NULL +#define HECI_INVALID_HANDLE NULL struct heci_guid { uint32_t data1; @@ -57,8 +57,8 @@ struct heci_client { uint32_t max_msg_size; uint8_t protocol_ver; uint8_t max_n_of_connections; - uint8_t dma_header_length :7; - uint8_t dma_enabled :1; + uint8_t dma_header_length : 7; + uint8_t dma_enabled : 1; const struct heci_client_callbacks *cbs; }; @@ -91,7 +91,7 @@ void *heci_get_client_data(const heci_handle_t handle); int heci_send_msg(const heci_handle_t handle, uint8_t *buf, const size_t buf_size); int heci_send_msg_timestamp(const heci_handle_t handle, uint8_t *buf, - const size_t buf_size, uint32_t *timestamp); + const size_t buf_size, uint32_t *timestamp); /* * send client msgs(using list of buffer&size). * heci_msg_item with size == 0 is not acceptable. @@ -102,11 +102,11 @@ int heci_send_msgs(const heci_handle_t handle, int heci_send_fixed_client_msg(const uint8_t fw_addr, uint8_t *buf, const size_t buf_size); -#define HECI_CLIENT_ENTRY(heci_client) \ - void _heci_entry_##heci_client(void) \ - { \ +#define HECI_CLIENT_ENTRY(heci_client) \ + void _heci_entry_##heci_client(void) \ + { \ heci_register_client(&(heci_client)); \ - } \ + } \ DECLARE_HOOK(HOOK_INIT, _heci_entry_##heci_client, HOOK_PRIO_LAST - 1) #endif /* __HECI_CLIENT_H */ diff --git a/chip/ish/hid_device.h b/chip/ish/hid_device.h index 0a32e305af..ba7722f5bb 100644 --- a/chip/ish/hid_device.h +++ b/chip/ish/hid_device.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,15 +11,15 @@ #include "hooks.h" -#define HID_SUBSYS_MAX_PAYLOAD_SIZE 4954 +#define HID_SUBSYS_MAX_PAYLOAD_SIZE 4954 enum HID_SUBSYS_ERR { - HID_SUBSYS_ERR_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0, - HID_SUBSYS_ERR_TOO_MANY_HID_DEVICES = EC_ERROR_INTERNAL_FIRST + 1, + HID_SUBSYS_ERR_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0, + HID_SUBSYS_ERR_TOO_MANY_HID_DEVICES = EC_ERROR_INTERNAL_FIRST + 1, }; -typedef void * hid_handle_t; -#define HID_INVALID_HANDLE NULL +typedef void *hid_handle_t; +#define HID_INVALID_HANDLE NULL struct hid_callbacks { /* @@ -73,11 +73,11 @@ int hid_subsys_set_device_data(const hid_handle_t handle, void *data); /* retrieve HID device specific data */ void *hid_subsys_get_device_data(const hid_handle_t handle); -#define HID_DEVICE_ENTRY(hid_dev) \ - void _hid_dev_entry_##hid_dev(void) \ - { \ +#define HID_DEVICE_ENTRY(hid_dev) \ + void _hid_dev_entry_##hid_dev(void) \ + { \ hid_subsys_register_device(&(hid_dev)); \ - } \ + } \ DECLARE_HOOK(HOOK_INIT, _hid_dev_entry_##hid_dev, HOOK_PRIO_LAST - 2) #endif /* __HID_DEVICE_H */ diff --git a/chip/ish/hid_subsys.c b/chip/ish/hid_subsys.c index bd3f331fdc..555af9046a 100644 --- a/chip/ish/hid_subsys.c +++ b/chip/ish/hid_subsys.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,8 +11,8 @@ #ifdef HID_SUBSYS_DEBUG #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) #else #define CPUTS(outstr) #define CPRINTS(format, args...) @@ -21,10 +21,15 @@ #define __packed __attribute__((packed)) -#define HECI_CLIENT_HID_GUID { 0x33AECD58, 0xB679, 0x4E54,\ - { 0x9B, 0xD9, 0xA0, 0x4D, 0x34, 0xF0, 0xC2, 0x26 } } +#define HECI_CLIENT_HID_GUID \ + { \ + 0x33AECD58, 0xB679, 0x4E54, \ + { \ + 0x9B, 0xD9, 0xA0, 0x4D, 0x34, 0xF0, 0xC2, 0x26 \ + } \ + } -#define HID_SUBSYS_MAX_HID_DEVICES 3 +#define HID_SUBSYS_MAX_HID_DEVICES 3 /* * the following enum values and data structures with __packed are used for @@ -55,13 +60,13 @@ struct hid_device_info { uint16_t vid; } __packed; -struct hid_enum_payload { +struct hid_enum_payload { uint8_t num_of_hid_devices; struct hid_device_info dev_info[0]; } __packed; -#define COMMAND_MASK 0x7F -#define RESPONSE_FLAG 0x80 +#define COMMAND_MASK 0x7F +#define RESPONSE_FLAG 0x80 struct hid_msg_hdr { uint8_t command; /* bit 7 is used to indicate "response" */ uint8_t device_id; @@ -94,8 +99,8 @@ static struct hid_subsystem hid_subsys_ctx = { .heci_handle = HECI_INVALID_HANDLE, }; -#define handle_to_dev_id(_handle) ((uintptr_t)(_handle)) -#define dev_id_to_handle(_dev_id) ((hid_handle_t)(uintptr_t)(_dev_id)) +#define handle_to_dev_id(_handle) ((uintptr_t)(_handle)) +#define dev_id_to_handle(_dev_id) ((hid_handle_t)(uintptr_t)(_dev_id)) static inline hid_handle_t device_index_to_handle(int device_index) { @@ -108,8 +113,8 @@ static inline int is_valid_handle(hid_handle_t handle) (uintptr_t)handle <= hid_subsys_ctx.num_of_hid_devices; } -static inline -struct hid_subsys_hid_device *handle_to_hid_device(hid_handle_t handle) +static inline struct hid_subsys_hid_device * +handle_to_hid_device(hid_handle_t handle) { if (!is_valid_handle(handle)) return NULL; @@ -117,7 +122,6 @@ struct hid_subsys_hid_device *handle_to_hid_device(hid_handle_t handle) return &hid_subsys_ctx.hid_devices[(uintptr_t)handle - 1]; } - hid_handle_t hid_subsys_register_device(const struct hid_device *dev_info) { struct hid_subsys_hid_device *hid_device; @@ -156,7 +160,7 @@ int hid_subsys_send_input_report(const hid_handle_t handle, uint8_t *buf, const size_t buf_size) { struct hid_subsys_hid_device *hid_device; - struct hid_msg_hdr hid_msg_hdr = {0}; + struct hid_msg_hdr hid_msg_hdr = { 0 }; struct heci_msg_item msg_item[2]; struct heci_msg_list msg_list; @@ -253,7 +257,7 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg) * re-use hid_msg from host for reply. */ switch (hid_msg->hdr.command & COMMAND_MASK) { - case HID_GET_HID_DESCRIPTOR: + case HID_GET_HID_DESCRIPTOR: if (cbs->get_hid_descriptor) ret = cbs->get_hid_descriptor(handle, payload, buf_size); @@ -277,10 +281,8 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg) case HID_SET_FEATURE_REPORT: if (cbs->set_feature_report) { - ret = cbs->set_feature_report(handle, - payload[0], - payload, - payload_size); + ret = cbs->set_feature_report(handle, payload[0], + payload, payload_size); /* * if no error, reply only with the report id. * re-use the first byte of payload @@ -293,8 +295,8 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg) break; case HID_GET_INPUT_REPORT: if (cbs->get_input_report) - ret = cbs->get_input_report(handle, payload[0], - payload, buf_size); + ret = cbs->get_input_report(handle, payload[0], payload, + buf_size); break; @@ -331,21 +333,21 @@ static int handle_hid_subsys_msg(struct hid_msg *hid_msg) struct hid_enum_payload *enum_payload; switch (hid_msg->hdr.command & COMMAND_MASK) { - case HID_DM_ENUM_DEVICES: + case HID_DM_ENUM_DEVICES: enum_payload = (struct hid_enum_payload *)hid_msg->payload; for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) { enum_payload->dev_info[i] = - hid_subsys_ctx.hid_devices[i].info; + hid_subsys_ctx.hid_devices[i].info; } enum_payload->num_of_hid_devices = - hid_subsys_ctx.num_of_hid_devices; + hid_subsys_ctx.num_of_hid_devices; /* reply payload size */ size = sizeof(enum_payload->num_of_hid_devices); size += enum_payload->num_of_hid_devices * - sizeof(enum_payload->dev_info[0]); + sizeof(enum_payload->dev_info[0]); break; @@ -408,7 +410,7 @@ static int hid_subsys_resume(const heci_handle_t heci_handle) for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) { if (hid_subsys_ctx.hid_devices[i].cbs->resume) ret |= hid_subsys_ctx.hid_devices[i].cbs->resume( - device_index_to_handle(i)); + device_index_to_handle(i)); } return ret; @@ -422,7 +424,7 @@ static int hid_subsys_suspend(const heci_handle_t heci_handle) for (i = hid_subsys_ctx.num_of_hid_devices - 1; i >= 0; i--) { if (hid_subsys_ctx.hid_devices[i].cbs->suspend) ret |= hid_subsys_ctx.hid_devices[i].cbs->suspend( - device_index_to_handle(i)); + device_index_to_handle(i)); } return ret; diff --git a/chip/ish/host_command_heci.c b/chip/ish/host_command_heci.c index de1485417b..ede615804c 100644 --- a/chip/ish/host_command_heci.c +++ b/chip/ish/host_command_heci.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,11 +13,16 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) - -#define HECI_CLIENT_CROS_EC_ISH_GUID { 0x7b7154d0, 0x56f4, 0x4bdc,\ - { 0xb0, 0xd8, 0x9e, 0x7c, 0xda, 0xe0, 0xd6, 0xa0 } } +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) + +#define HECI_CLIENT_CROS_EC_ISH_GUID \ + { \ + 0x7b7154d0, 0x56f4, 0x4bdc, \ + { \ + 0xb0, 0xd8, 0x9e, 0x7c, 0xda, 0xe0, 0xd6, 0xa0 \ + } \ + } /* Handle for all heci cros_ec interactions */ static heci_handle_t heci_cros_ec_handle = HECI_INVALID_HANDLE; @@ -33,7 +38,7 @@ static heci_handle_t heci_cros_ec_handle = HECI_INVALID_HANDLE; struct cros_ec_ishtp_msg_hdr { uint8_t channel; uint8_t status; - uint8_t id; /* Pairs up request and responses */ + uint8_t id; /* Pairs up request and responses */ uint8_t reserved; } __ec_align4; @@ -88,10 +93,11 @@ static void heci_send_hostcmd_response(struct host_packet *pkt) } static void cros_ec_ishtp_subsys_new_msg_received(const heci_handle_t handle, - uint8_t *msg, const size_t msg_size) + uint8_t *msg, + const size_t msg_size) { - struct cros_ec_ishtp_msg *in = (void *) msg; - struct cros_ec_ishtp_msg *out = (void *) response_buffer; + struct cros_ec_ishtp_msg *in = (void *)msg; + struct cros_ec_ishtp_msg *out = (void *)response_buffer; if (in->hdr.channel != CROS_EC_COMMAND) { CPRINTS("Unknown HECI packet 0x%02x", in->hdr.channel); @@ -140,7 +146,7 @@ static enum ec_status heci_get_protocol_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, heci_get_protocol_info, -EC_VER_MASK(0)); + EC_VER_MASK(0)); static int cros_ec_ishtp_subsys_initialize(const heci_handle_t heci_handle) { diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h index 06738fafb1..7438f42949 100644 --- a/chip/ish/hpet.h +++ b/chip/ish/hpet.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,61 +10,58 @@ /* ISH HPET config and timer registers */ -#define TIMER0_CONF_CAP_REG 0x100 -#define TIMER0_COMP_VAL_REG 0x108 - +#define TIMER0_CONF_CAP_REG 0x100 +#define TIMER0_COMP_VAL_REG 0x108 /* HPET_GENERAL_CONFIG settings */ -#define HPET_GENERAL_CONFIG REG32(ISH_HPET_BASE + 0x10) -#define HPET_ENABLE_CNF BIT(0) -#define HPET_LEGACY_RT_CNF BIT(1) +#define HPET_GENERAL_CONFIG REG32(ISH_HPET_BASE + 0x10) +#define HPET_ENABLE_CNF BIT(0) +#define HPET_LEGACY_RT_CNF BIT(1) /* Interrupt status acknowledge register */ -#define HPET_INTR_CLEAR REG32(ISH_HPET_BASE + 0x20) +#define HPET_INTR_CLEAR REG32(ISH_HPET_BASE + 0x20) /* Main counter register. 64-bit */ -#define HPET_MAIN_COUNTER_64 REG64(ISH_HPET_BASE + 0xF0) -#define HPET_MAIN_COUNTER_64_LO REG32(ISH_HPET_BASE + 0xF0) -#define HPET_MAIN_COUNTER_64_HI REG32(ISH_HPET_BASE + 0xF4) +#define HPET_MAIN_COUNTER_64 REG64(ISH_HPET_BASE + 0xF0) +#define HPET_MAIN_COUNTER_64_LO REG32(ISH_HPET_BASE + 0xF0) +#define HPET_MAIN_COUNTER_64_HI REG32(ISH_HPET_BASE + 0xF4) /* HPET Timer 0/1/2 configuration*/ -#define HPET_TIMER_CONF_CAP(x) REG32(ISH_HPET_BASE + 0x100 + ((x) * 0x20)) -#define HPET_Tn_INT_TYPE_CNF BIT(1) -#define HPET_Tn_INT_ENB_CNF BIT(2) -#define HPET_Tn_TYPE_CNF BIT(3) -#define HPET_Tn_VAL_SET_CNF BIT(6) -#define HPET_Tn_32MODE_CNF BIT(8) -#define HPET_Tn_INT_ROUTE_CNF_SHIFT 0x9 -#define HPET_Tn_INT_ROUTE_CNF_MASK (0x1f << 9) +#define HPET_TIMER_CONF_CAP(x) REG32(ISH_HPET_BASE + 0x100 + ((x)*0x20)) +#define HPET_Tn_INT_TYPE_CNF BIT(1) +#define HPET_Tn_INT_ENB_CNF BIT(2) +#define HPET_Tn_TYPE_CNF BIT(3) +#define HPET_Tn_VAL_SET_CNF BIT(6) +#define HPET_Tn_32MODE_CNF BIT(8) +#define HPET_Tn_INT_ROUTE_CNF_SHIFT 0x9 +#define HPET_Tn_INT_ROUTE_CNF_MASK (0x1f << 9) /* * HPET Timer 0/1/2 comparator values. 1/2 are always 32-bit. 0 can be * configured as 64-bit. */ -#define HPET_TIMER_COMP(x) REG32(ISH_HPET_BASE + 0x108 + ((x) * 0x20)) -#define HPET_TIMER0_COMP_64 REG64(ISH_HPET_BASE + 0x108) +#define HPET_TIMER_COMP(x) REG32(ISH_HPET_BASE + 0x108 + ((x)*0x20)) +#define HPET_TIMER0_COMP_64 REG64(ISH_HPET_BASE + 0x108) /* ISH 4/5: Special status register * Use this register to see HPET timer are settled after a write. */ -#define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + 0x160) -#define HPET_INT_STATUS_SETTLING BIT(1) -#define HPET_MAIN_COUNTER_SETTLING (BIT(2) | BIT(3)) -#define HPET_T0_CAP_SETTLING BIT(4) -#define HPET_T1_CAP_SETTLING BIT(5) -#define HPET_T0_CMP_SETTLING (BIT(7) | BIT(8)) -#define HPET_T1_CMP_SETTLING BIT(9) -#define HPET_MAIN_COUNTER_VALID BIT(13) -#define HPET_T1_SETTLING (HPET_T1_CAP_SETTLING | \ - HPET_T1_CMP_SETTLING) -#define HPET_T0_SETTLING (HPET_T0_CAP_SETTLING | \ - HPET_T0_CMP_SETTLING) -#define HPET_ANY_SETTLING (BIT(12) - 1) +#define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + 0x160) +#define HPET_INT_STATUS_SETTLING BIT(1) +#define HPET_MAIN_COUNTER_SETTLING (BIT(2) | BIT(3)) +#define HPET_T0_CAP_SETTLING BIT(4) +#define HPET_T1_CAP_SETTLING BIT(5) +#define HPET_T0_CMP_SETTLING (BIT(7) | BIT(8)) +#define HPET_T1_CMP_SETTLING BIT(9) +#define HPET_MAIN_COUNTER_VALID BIT(13) +#define HPET_T1_SETTLING (HPET_T1_CAP_SETTLING | HPET_T1_CMP_SETTLING) +#define HPET_T0_SETTLING (HPET_T0_CAP_SETTLING | HPET_T0_CMP_SETTLING) +#define HPET_ANY_SETTLING (BIT(12) - 1) #if defined(CHIP_FAMILY_ISH3) -#define ISH_HPET_CLK_FREQ 12000000 /* 12 MHz clock */ +#define ISH_HPET_CLK_FREQ 12000000 /* 12 MHz clock */ #elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5) -#define ISH_HPET_CLK_FREQ 32768 /* 32.768 KHz clock */ +#define ISH_HPET_CLK_FREQ 32768 /* 32.768 KHz clock */ #endif #endif /* __CROS_EC_HPET_H */ diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c index 1259dae7f4..57049a63b3 100644 --- a/chip/ish/hwtimer.c +++ b/chip/ish/hwtimer.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,8 +14,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args) static uint32_t last_deadline; @@ -37,7 +37,7 @@ static uint32_t last_deadline; /* Scaling helper methods for different ISH chip variants */ #ifdef CHIP_FAMILY_ISH3 #define CLOCK_FACTOR 12 -BUILD_ASSERT(CLOCK_FACTOR * SECOND == ISH_HPET_CLK_FREQ); +BUILD_ASSERT(CLOCK_FACTOR *SECOND == ISH_HPET_CLK_FREQ); static inline uint64_t scale_us2ticks(uint64_t us) { @@ -239,8 +239,7 @@ int __hw_clock_source_init64(uint64_t start_t) /* Timer 1 - IRQ routing */ timer1_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK; - timer1_config |= (ISH_HPET_TIMER1_IRQ << - HPET_Tn_INT_ROUTE_CNF_SHIFT); + timer1_config |= (ISH_HPET_TIMER1_IRQ << HPET_Tn_INT_ROUTE_CNF_SHIFT); /* Level triggered interrupt */ timer1_config |= HPET_Tn_INT_TYPE_CNF; diff --git a/chip/ish/i2c.c b/chip/ish/i2c.c index 11f3e0a0b1..e26bcd70e5 100644 --- a/chip/ish/i2c.c +++ b/chip/ish/i2c.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,65 +19,53 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) /*25MHz, 50MHz, 100MHz, 120MHz, 40MHz, 20MHz, 37MHz*/ -static uint16_t default_hcnt_scl_100[] = { - 4000, 4420, 4920, 4400, 4000, 4000, 4300 -}; +static uint16_t default_hcnt_scl_100[] = { 4000, 4420, 4920, 4400, + 4000, 4000, 4300 }; -static uint16_t default_lcnt_scl_100[] = { - 4720, 5180, 4990, 5333, 4700, 5200, 4950 -}; +static uint16_t default_lcnt_scl_100[] = { 4720, 5180, 4990, 5333, + 4700, 5200, 4950 }; -static uint16_t default_hcnt_scl_400[] = { - 600, 820, 1120, 800, 600, 600, 450 -}; +static uint16_t default_hcnt_scl_400[] = { 600, 820, 1120, 800, 600, 600, 450 }; -static uint16_t default_lcnt_scl_400[] = { - 1320, 1380, 1300, 1550, 1300, 1200, 1250 -}; +static uint16_t default_lcnt_scl_400[] = { 1320, 1380, 1300, 1550, + 1300, 1200, 1250 }; -static uint16_t default_hcnt_scl_1000[] = { - 260, 260, 260, 305, 260, 260, 260 -}; +static uint16_t default_hcnt_scl_1000[] = { 260, 260, 260, 305, 260, 260, 260 }; -static uint16_t default_lcnt_scl_1000[] = { - 500, 500, 500, 525, 500, 500, 500 -}; +static uint16_t default_lcnt_scl_1000[] = { 500, 500, 500, 525, 500, 500, 500 }; static uint16_t default_hcnt_scl_hs[] = { 160, 300, 160, 166, 175, 150, 162 }; static uint16_t default_lcnt_scl_hs[] = { 320, 340, 320, 325, 325, 300, 297 }; - #ifdef CHIP_VARIANT_ISH5P4 /* Change to I2C_FREQ_100 in real silicon platform */ -static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { - I2C_FREQ_100, I2C_FREQ_100, I2C_FREQ_100 -}; +static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { I2C_FREQ_100, I2C_FREQ_100, + I2C_FREQ_100 }; #else -static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { - I2C_FREQ_120, I2C_FREQ_120, I2C_FREQ_120 -}; +static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { I2C_FREQ_120, I2C_FREQ_120, + I2C_FREQ_120 }; #endif static struct i2c_context i2c_ctxs[ISH_I2C_PORT_COUNT] = { { .bus = 0, - .base = (uint32_t *) ISH_I2C0_BASE, + .base = (uint32_t *)ISH_I2C0_BASE, .speed = I2C_SPEED_400KHZ, .int_pin = ISH_I2C0_IRQ, }, { .bus = 1, - .base = (uint32_t *) ISH_I2C1_BASE, + .base = (uint32_t *)ISH_I2C1_BASE, .speed = I2C_SPEED_400KHZ, .int_pin = ISH_I2C1_IRQ, }, { .bus = 2, - .base = (uint32_t *) ISH_I2C2_BASE, + .base = (uint32_t *)ISH_I2C2_BASE, .speed = I2C_SPEED_400KHZ, .int_pin = ISH_I2C2_IRQ, }, @@ -104,22 +92,20 @@ static struct i2c_bus_info board_config[ISH_I2C_PORT_COUNT] = { .fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST, .fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS, .high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH, - }, + }, }; -static inline void i2c_mmio_write(uint32_t *base, uint8_t offset, - uint32_t data) +static inline void i2c_mmio_write(uint32_t *base, uint8_t offset, uint32_t data) { - REG32((uint32_t) ((uint8_t *)base + offset)) = data; + REG32((uint32_t)((uint8_t *)base + offset)) = data; } static inline uint32_t i2c_mmio_read(uint32_t *base, uint8_t offset) { - return REG32((uint32_t) ((uint8_t *)base + offset)); + return REG32((uint32_t)((uint8_t *)base + offset)); } -static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg, - uint8_t offset) +static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg, uint8_t offset) { uint32_t ret = i2c_mmio_read(addr, reg) >> offset; @@ -129,7 +115,6 @@ static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg, static void i2c_intr_switch(uint32_t *base, int mode) { switch (mode) { - case ENABLE_WRITE_INT: i2c_mmio_write(base, IC_INTR_MASK, IC_INTR_WRITE_MASK_VAL); break; @@ -157,8 +142,8 @@ static void i2c_intr_switch(uint32_t *base, int mode) } } -static void i2c_init_transaction(struct i2c_context *ctx, - uint16_t addr, uint8_t flags) +static void i2c_init_transaction(struct i2c_context *ctx, uint16_t addr, + uint8_t flags) { uint32_t con_value; uint32_t *base = ctx->base; @@ -169,64 +154,64 @@ static void i2c_init_transaction(struct i2c_context *ctx, i2c_intr_switch(base, DISABLE_INT); i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE); - i2c_mmio_write(base, IC_TAR, (addr << IC_TAR_OFFSET) | - TAR_SPECIAL_VAL | IC_10BITADDR_MASTER_VAL); + i2c_mmio_write(base, IC_TAR, + (addr << IC_TAR_OFFSET) | TAR_SPECIAL_VAL | + IC_10BITADDR_MASTER_VAL); /* set Clock SCL Count */ switch (ctx->speed) { - case I2C_SPEED_100KHZ: i2c_mmio_write(base, IC_SS_SCL_HCNT, - NS_2_COUNTERS(bus_info->std_speed.hcnt, + NS_2_COUNTERS(bus_info->std_speed.hcnt, clk_in_val)); i2c_mmio_write(base, IC_SS_SCL_LCNT, - NS_2_COUNTERS(bus_info->std_speed.lcnt, + NS_2_COUNTERS(bus_info->std_speed.lcnt, clk_in_val)); i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->std_speed.sda_hold, + NS_2_COUNTERS(bus_info->std_speed.sda_hold, clk_in_val)); break; case I2C_SPEED_400KHZ: i2c_mmio_write(base, IC_FS_SCL_HCNT, - NS_2_COUNTERS(bus_info->fast_speed.hcnt, + NS_2_COUNTERS(bus_info->fast_speed.hcnt, clk_in_val)); i2c_mmio_write(base, IC_FS_SCL_LCNT, - NS_2_COUNTERS(bus_info->fast_speed.lcnt, + NS_2_COUNTERS(bus_info->fast_speed.lcnt, clk_in_val)); i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->fast_speed.sda_hold, + NS_2_COUNTERS(bus_info->fast_speed.sda_hold, clk_in_val)); break; case I2C_SPEED_1MHZ: i2c_mmio_write(base, IC_FS_SCL_HCNT, - NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt, + NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt, clk_in_val)); i2c_mmio_write(base, IC_FS_SCL_LCNT, - NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt, + NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt, clk_in_val)); i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold, + NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold, clk_in_val)); break; case I2C_SPEED_3M4HZ: i2c_mmio_write(base, IC_HS_SCL_HCNT, - NS_2_COUNTERS(bus_info->high_speed.hcnt, + NS_2_COUNTERS(bus_info->high_speed.hcnt, clk_in_val)); i2c_mmio_write(base, IC_HS_SCL_LCNT, - NS_2_COUNTERS(bus_info->high_speed.lcnt, + NS_2_COUNTERS(bus_info->high_speed.lcnt, clk_in_val)); i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->high_speed.sda_hold, + NS_2_COUNTERS(bus_info->high_speed.sda_hold, clk_in_val)); i2c_mmio_write(base, IC_FS_SCL_HCNT, - NS_2_COUNTERS(bus_info->fast_speed.hcnt, + NS_2_COUNTERS(bus_info->fast_speed.hcnt, clk_in_val)); i2c_mmio_write(base, IC_FS_SCL_LCNT, - NS_2_COUNTERS(bus_info->fast_speed.lcnt, + NS_2_COUNTERS(bus_info->fast_speed.lcnt, clk_in_val)); break; @@ -248,15 +233,13 @@ static void i2c_init_transaction(struct i2c_context *ctx, i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_ENABLE); } -static void i2c_write_buffer(uint32_t *base, uint8_t len, - const uint8_t *buffer, ssize_t *cur_index, - ssize_t total_len) +static void i2c_write_buffer(uint32_t *base, uint8_t len, const uint8_t *buffer, + ssize_t *cur_index, ssize_t total_len) { int i; uint16_t out; for (i = 0; i < len; i++) { - ++(*cur_index); out = (buffer[i] << DATA_CMD_DAT_OFFSET) | DATA_CMD_WRITE_VAL; @@ -270,7 +253,7 @@ static void i2c_write_buffer(uint32_t *base, uint8_t len, } static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data, - unsigned restart_flag) + unsigned restart_flag) { /* this routine just set RX FIFO's control bit(s), * READ command or RESTART */ @@ -293,9 +276,8 @@ static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data, } } -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { int i; ssize_t total_len; @@ -333,8 +315,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, /* Write W data */ if (out_size) - i2c_write_buffer(ctx->base, out_size, out, - &curr_index, total_len); + i2c_write_buffer(ctx->base, out_size, out, &curr_index, + total_len); /* Wait here until Tx is completed so that FIFO becomes empty. * This is optimized for smaller Tx data size. @@ -344,10 +326,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * */ expire_ts = __hw_clock_source_read() + I2C_TX_FLUSH_TIMEOUT_USEC; if (in_size > (ISH_I2C_FIFO_SIZE - out_size)) { - while ((i2c_mmio_read(ctx->base, IC_STATUS) & BIT(IC_STATUS_TFE)) == 0) { - if (__hw_clock_source_read() >= expire_ts) { ctx->error_flag = 1; break; @@ -358,7 +338,7 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, begin_indx = 0; while (in_size) { - int rd_size; /* read size for on i2c transaction */ + int rd_size; /* read size for on i2c transaction */ /* * check if in_size > ISH_I2C_FIFO_SIZE, then try to read @@ -383,11 +363,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * set R commands bit, start to read */ i2c_write_read_commands(ctx->base, rd_size, in_size, - (begin_indx == 0) && (repeat_start != 0)); - + (begin_indx == 0) && + (repeat_start != 0)); /* need timeout in case no ACK from peripheral */ - task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2*MSEC); + task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2 * MSEC); if (ctx->interrupts & M_TX_ABRT) { ctx->error_flag = 1; @@ -396,8 +376,7 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, /* read data */ for (i = begin_indx; i < begin_indx + rd_size; i++) - in[i] = i2c_read_byte(ctx->base, - IC_DATA_CMD, 0); + in[i] = i2c_read_byte(ctx->base, IC_DATA_CMD, 0); begin_indx += rd_size; } /* while (in_size) */ @@ -411,7 +390,6 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, while ((i2c_mmio_read(ctx->base, IC_STATUS) & (BIT(IC_STATUS_MASTER_ACTIVITY) | BIT(IC_STATUS_TFE))) != BIT(IC_STATUS_TFE)) { - if (__hw_clock_source_read() >= expire_ts) { ctx->error_flag = 1; break; @@ -432,12 +410,12 @@ static void i2c_interrupt_handler(struct i2c_context *ctx) uint32_t raw_intr; if (IS_ENABLED(INTR_DEBUG)) - raw_intr = 0x0000FFFF & i2c_mmio_read(ctx->base, - IC_RAW_INTR_STAT); + raw_intr = 0x0000FFFF & + i2c_mmio_read(ctx->base, IC_RAW_INTR_STAT); /* check interrupts */ ctx->interrupts = i2c_mmio_read(ctx->base, IC_INTR_STAT); - ctx->reason = (uint16_t) i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE); + ctx->reason = (uint16_t)i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE); if (IS_ENABLED(INTR_DEBUG)) CPRINTS("INTR_STAT = 0x%04x, TX_ABORT_SRC = 0x%04x, " @@ -467,9 +445,8 @@ static void i2c_isr_bus2(void) } DECLARE_IRQ(ISH_I2C2_IRQ, i2c_isr_bus2); -static void i2c_config_speed(struct i2c_context *ctx, int kbps) +static void i2c_config_speed(struct i2c_context *ctx, int kbps) { - if (kbps > 1000) ctx->speed = I2C_SPEED_3M4HZ; else if (kbps > 400) @@ -478,7 +455,6 @@ static void i2c_config_speed(struct i2c_context *ctx, int kbps) ctx->speed = I2C_SPEED_400KHZ; else ctx->speed = I2C_SPEED_100KHZ; - } static void i2c_init_hardware(struct i2c_context *ctx) @@ -486,8 +462,8 @@ static void i2c_init_hardware(struct i2c_context *ctx) static const uint8_t speed_val_arr[] = { [I2C_SPEED_100KHZ] = STD_SPEED_VAL, [I2C_SPEED_400KHZ] = FAST_SPEED_VAL, - [I2C_SPEED_1MHZ] = FAST_SPEED_VAL, - [I2C_SPEED_3M4HZ] = HIGH_SPEED_VAL, + [I2C_SPEED_1MHZ] = FAST_SPEED_VAL, + [I2C_SPEED_3M4HZ] = HIGH_SPEED_VAL, }; uint32_t *base = ctx->base; @@ -495,19 +471,20 @@ static void i2c_init_hardware(struct i2c_context *ctx) /* disable interrupts */ i2c_intr_switch(base, DISABLE_INT); i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE); - i2c_mmio_write(base, IC_CON, (MASTER_MODE_VAL - | speed_val_arr[ctx->speed] - | IC_RESTART_EN_VAL - | IC_SLAVE_DISABLE_VAL)); + i2c_mmio_write(base, IC_CON, + (MASTER_MODE_VAL | speed_val_arr[ctx->speed] | + IC_RESTART_EN_VAL | IC_SLAVE_DISABLE_VAL)); i2c_mmio_write(base, IC_FS_SPKLEN, spkln[bus_freq[ctx->bus]]); i2c_mmio_write(base, IC_HS_SPKLEN, spkln[bus_freq[ctx->bus]]); /* get RX_FIFO and TX_FIFO depth */ - ctx->max_rx_depth = i2c_read_byte(base, IC_COMP_PARAM_1, - RX_BUFFER_DEPTH_OFFSET) + 1; - ctx->max_tx_depth = i2c_read_byte(base, IC_COMP_PARAM_1, - TX_BUFFER_DEPTH_OFFSET) + 1; + ctx->max_rx_depth = + i2c_read_byte(base, IC_COMP_PARAM_1, RX_BUFFER_DEPTH_OFFSET) + + 1; + ctx->max_tx_depth = + i2c_read_byte(base, IC_COMP_PARAM_1, TX_BUFFER_DEPTH_OFFSET) + + 1; } static void i2c_initial_board_config(struct i2c_context *ctx) diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c index 9553e195c4..1fd81e3d3f 100644 --- a/chip/ish/ipc_heci.c +++ b/chip/ish/ipc_heci.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,6 +23,7 @@ * - Doorbell Clear Status Register (DB CSR) */ +#include "builtin/assert.h" #include "registers.h" #include "console.h" #include "task.h" @@ -34,8 +35,8 @@ #include "hwtimer.h" #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) /* * comminucation protocol is defined in Linux Documentation @@ -44,57 +45,55 @@ /* MNG commands */ /* The ipc_mng_task manages IPC link. It should be the highest priority */ -#define MNG_RX_CMPL_ENABLE 0 -#define MNG_RX_CMPL_DISABLE 1 -#define MNG_RX_CMPL_INDICATION 2 -#define MNG_RESET_NOTIFY 3 -#define MNG_RESET_NOTIFY_ACK 4 -#define MNG_SYNC_FW_CLOCK 5 -#define MNG_ILLEGAL_CMD 0xFF +#define MNG_RX_CMPL_ENABLE 0 +#define MNG_RX_CMPL_DISABLE 1 +#define MNG_RX_CMPL_INDICATION 2 +#define MNG_RESET_NOTIFY 3 +#define MNG_RESET_NOTIFY_ACK 4 +#define MNG_SYNC_FW_CLOCK 5 +#define MNG_ILLEGAL_CMD 0xFF /* Doorbell */ -#define IPC_DB_MSG_LENGTH_FIELD 0x3FF -#define IPC_DB_MSG_LENGTH_SHIFT 0 +#define IPC_DB_MSG_LENGTH_FIELD 0x3FF +#define IPC_DB_MSG_LENGTH_SHIFT 0 #define IPC_DB_MSG_LENGTH_MASK \ - (IPC_DB_MSG_LENGTH_FIELD << IPC_DB_MSG_LENGTH_SHIFT) + (IPC_DB_MSG_LENGTH_FIELD << IPC_DB_MSG_LENGTH_SHIFT) -#define IPC_DB_PROTOCOL_FIELD 0x0F -#define IPC_DB_PROTOCOL_SHIFT 10 +#define IPC_DB_PROTOCOL_FIELD 0x0F +#define IPC_DB_PROTOCOL_SHIFT 10 #define IPC_DB_PROTOCOL_MASK (IPC_DB_PROTOCOL_FIELD << IPC_DB_PROTOCOL_SHIFT) -#define IPC_DB_CMD_FIELD 0x0F -#define IPC_DB_CMD_SHIFT 16 -#define IPC_DB_CMD_MASK (IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT) +#define IPC_DB_CMD_FIELD 0x0F +#define IPC_DB_CMD_SHIFT 16 +#define IPC_DB_CMD_MASK (IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT) -#define IPC_DB_BUSY_SHIFT 31 -#define IPC_DB_BUSY_MASK BIT(IPC_DB_BUSY_SHIFT) +#define IPC_DB_BUSY_SHIFT 31 +#define IPC_DB_BUSY_MASK BIT(IPC_DB_BUSY_SHIFT) #define IPC_DB_MSG_LENGTH(drbl) \ - (((drbl) & IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT) + (((drbl)&IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT) #define IPC_DB_PROTOCOL(drbl) \ - (((drbl) & IPC_DB_PROTOCOL_MASK) >> IPC_DB_PROTOCOL_SHIFT) -#define IPC_DB_CMD(drbl) \ - (((drbl) & IPC_DB_CMD_MASK) >> IPC_DB_CMD_SHIFT) -#define IPC_DB_BUSY(drbl) (!!((drbl) & IPC_DB_BUSY_MASK)) + (((drbl)&IPC_DB_PROTOCOL_MASK) >> IPC_DB_PROTOCOL_SHIFT) +#define IPC_DB_CMD(drbl) (((drbl)&IPC_DB_CMD_MASK) >> IPC_DB_CMD_SHIFT) +#define IPC_DB_BUSY(drbl) (!!((drbl)&IPC_DB_BUSY_MASK)) -#define IPC_BUILD_DB(length, proto, cmd, busy) \ +#define IPC_BUILD_DB(length, proto, cmd, busy) \ (((busy) << IPC_DB_BUSY_SHIFT) | ((cmd) << IPC_DB_CMD_SHIFT) | \ - ((proto) << IPC_DB_PROTOCOL_SHIFT) | \ - ((length) << IPC_DB_MSG_LENGTH_SHIFT)) + ((proto) << IPC_DB_PROTOCOL_SHIFT) | \ + ((length) << IPC_DB_MSG_LENGTH_SHIFT)) #define IPC_BUILD_MNG_DB(cmd, length) \ IPC_BUILD_DB(length, IPC_PROTOCOL_MNG, cmd, 1) -#define IPC_BUILD_HECI_DB(length) \ - IPC_BUILD_DB(length, IPC_PROTOCOL_HECI, 0, 1) +#define IPC_BUILD_HECI_DB(length) IPC_BUILD_DB(length, IPC_PROTOCOL_HECI, 0, 1) -#define IPC_MSG_MAX_SIZE 0x80 -#define IPC_HOST_MSG_QUEUE_SIZE 8 -#define IPC_PMC_MSG_QUEUE_SIZE 2 +#define IPC_MSG_MAX_SIZE 0x80 +#define IPC_HOST_MSG_QUEUE_SIZE 8 +#define IPC_PMC_MSG_QUEUE_SIZE 2 -#define IPC_HANDLE_PEER_ID_SHIFT 4 -#define IPC_HANDLE_PROTOCOL_SHIFT 0 -#define IPC_HANDLE_PROTOCOL_MASK 0x0F +#define IPC_HANDLE_PEER_ID_SHIFT 4 +#define IPC_HANDLE_PROTOCOL_SHIFT 0 +#define IPC_HANDLE_PROTOCOL_MASK 0x0F #define IPC_BUILD_HANDLE(peer_id, protocol) \ ((ipc_handle_t)(((peer_id) << IPC_HANDLE_PEER_ID_SHIFT) | (protocol))) #define IPC_BUILD_MNG_HANDLE(peer_id) \ @@ -103,10 +102,10 @@ #define IPC_HANDLE_PEER_ID(handle) \ ((uint32_t)(handle) >> IPC_HANDLE_PEER_ID_SHIFT) #define IPC_HANDLE_PROTOCOL(handle) \ - ((uint32_t)(handle) & IPC_HANDLE_PROTOCOL_MASK) -#define IPC_IS_VALID_HANDLE(handle) \ + ((uint32_t)(handle)&IPC_HANDLE_PROTOCOL_MASK) +#define IPC_IS_VALID_HANDLE(handle) \ (IPC_HANDLE_PEER_ID(handle) < IPC_PEERS_COUNT && \ - IPC_HANDLE_PROTOCOL(handle) < IPC_PROTOCOL_COUNT) + IPC_HANDLE_PROTOCOL(handle) < IPC_PROTOCOL_COUNT) struct ipc_msg { uint32_t drbl; @@ -191,21 +190,20 @@ static inline void ipc_disable_pimr_db_interrupt(const struct ipc_if_ctx *ctx) IPC_PIMR &= ~ctx->pimr_2ish_bit; } -static inline void ipc_enable_pimr_clearing_interrupt( - const struct ipc_if_ctx *ctx) +static inline void +ipc_enable_pimr_clearing_interrupt(const struct ipc_if_ctx *ctx) { IPC_PIMR |= ctx->pimr_2host_clearing_bit; } -static inline void ipc_disable_pimr_clearing_interrupt( - const struct ipc_if_ctx *ctx) +static inline void +ipc_disable_pimr_clearing_interrupt(const struct ipc_if_ctx *ctx) { IPC_PIMR &= ~ctx->pimr_2host_clearing_bit; } static void write_payload_and_ring_drbl(const struct ipc_if_ctx *ctx, - uint32_t drbl, - const uint8_t *payload, + uint32_t drbl, const uint8_t *payload, size_t payload_size) { memcpy((void *)(ctx->out_msg_reg), payload, payload_size); @@ -280,7 +278,7 @@ static int ipc_send_reset_notify(const ipc_handle_t handle) static int ipc_send_cmpl_indication(struct ipc_if_ctx *ctx) { - struct ipc_msg msg = {0}; + struct ipc_msg msg = { 0 }; msg.drbl = IPC_BUILD_MNG_DB(MNG_RX_CMPL_INDICATION, 0); ipc_write_raw(ctx, msg.drbl, msg.payload, IPC_DB_MSG_LENGTH(msg.drbl)); @@ -289,8 +287,8 @@ static int ipc_send_cmpl_indication(struct ipc_if_ctx *ctx) } static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx, - const uint32_t protocol, - uint8_t *buf, const size_t buf_size) + const uint32_t protocol, uint8_t *buf, + const size_t buf_size) { int len = 0, payload_size; uint8_t *src = NULL, *dest = NULL; @@ -325,9 +323,8 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx, } if (IS_ENABLED(IPC_HECI_DEBUG)) - CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n", - protocol, drbl_val, - IPC_DB_MSG_LENGTH(drbl_val)); + CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n", protocol, + drbl_val, IPC_DB_MSG_LENGTH(drbl_val)); switch (protocol) { case IPC_PROTOCOL_HECI: @@ -340,7 +337,7 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx, msg->drbl = drbl_val; dest = msg->payload; break; - default : + default: break; } @@ -544,13 +541,11 @@ int ipc_write_timestamp(const ipc_handle_t handle, const void *buf, } ipc_handle_t ipc_open(const enum ipc_peer_id peer_id, - const enum ipc_protocol protocol, - const uint32_t event) + const enum ipc_protocol protocol, const uint32_t event) { struct ipc_if_ctx *ctx; - if (protocol >= IPC_PROTOCOL_COUNT || - peer_id >= IPC_PEERS_COUNT) + if (protocol >= IPC_PROTOCOL_COUNT || peer_id >= IPC_PEERS_COUNT) return IPC_INVALID_HANDLE; ctx = ipc_get_if_ctx(peer_id); @@ -564,9 +559,9 @@ ipc_handle_t ipc_open(const enum ipc_peer_id peer_id, ctx->msg_events[protocol].enabled = 1; ctx->msg_events[protocol].event = event; - /* For HECI protocol, set HECI UP status when IPC link is ready */ - if (peer_id == IPC_PEER_ID_HOST && - protocol == IPC_PROTOCOL_HECI && ish_fwst_is_ilup_set()) + /* For HECI protocol, set HECI UP status when IPC link is ready */ + if (peer_id == IPC_PEER_ID_HOST && protocol == IPC_PROTOCOL_HECI && + ish_fwst_is_ilup_set()) ish_fwst_set_hup(); if (ctx->initialized == 0) { @@ -686,7 +681,7 @@ int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size, } /* event flag for MNG msg */ -#define EVENT_FLAG_BIT_MNG_MSG TASK_EVENT_CUSTOM_BIT(0) +#define EVENT_FLAG_BIT_MNG_MSG TASK_EVENT_CUSTOM_BIT(0) /* * This task handles MNG messages diff --git a/chip/ish/ipc_heci.h b/chip/ish/ipc_heci.h index 183e6a2c6b..f9372aefa3 100644 --- a/chip/ish/ipc_heci.h +++ b/chip/ish/ipc_heci.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,16 +8,16 @@ #define __IPC_HECI_H enum IPC_ERR { - IPC_ERR_IPC_IS_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0, - IPC_ERR_TOO_SMALL_BUFFER = EC_ERROR_INTERNAL_FIRST + 1, - IPC_ERR_TX_QUEUE_FULL = EC_ERROR_INTERNAL_FIRST + 2, - IPC_ERR_INVALID_TASK = EC_ERROR_INTERNAL_FIRST + 3, - IPC_ERR_MSG_NOT_AVAILABLE = EC_ERROR_INTERNAL_FIRST + 4, - IPC_ERR_INVALID_MSG = EC_ERROR_INTERNAL_FIRST + 5, + IPC_ERR_IPC_IS_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0, + IPC_ERR_TOO_SMALL_BUFFER = EC_ERROR_INTERNAL_FIRST + 1, + IPC_ERR_TX_QUEUE_FULL = EC_ERROR_INTERNAL_FIRST + 2, + IPC_ERR_INVALID_TASK = EC_ERROR_INTERNAL_FIRST + 3, + IPC_ERR_MSG_NOT_AVAILABLE = EC_ERROR_INTERNAL_FIRST + 4, + IPC_ERR_INVALID_MSG = EC_ERROR_INTERNAL_FIRST + 5, }; enum ipc_peer_id { - IPC_PEER_ID_HOST = 0, /* x64 host */ + IPC_PEER_ID_HOST = 0, /* x64 host */ #if 0 /* other peers are not implemented yet */ IPC_PEER_ID_PMC = 1, /* Power Management Controller */ IPC_PEER_ID_CSME = 2, /* Converged Security Management Engine */ @@ -33,11 +33,11 @@ enum ipc_peer_id { BUILD_ASSERT(IPC_PEERS_COUNT <= 0x0F); enum ipc_protocol { - IPC_PROTOCOL_BOOT = 0, /* Not supported */ - IPC_PROTOCOL_HECI, /* Host Embedded Controller Interface */ - IPC_PROTOCOL_MCTP, /* not supported */ - IPC_PROTOCOL_MNG, /* Management protocol */ - IPC_PROTOCOL_ECP, /* EC Protocol. not supported */ + IPC_PROTOCOL_BOOT = 0, /* Not supported */ + IPC_PROTOCOL_HECI, /* Host Embedded Controller Interface */ + IPC_PROTOCOL_MCTP, /* not supported */ + IPC_PROTOCOL_MNG, /* Management protocol */ + IPC_PROTOCOL_ECP, /* EC Protocol. not supported */ IPC_PROTOCOL_COUNT }; /* @@ -46,10 +46,10 @@ enum ipc_protocol { */ BUILD_ASSERT(IPC_PROTOCOL_COUNT <= 0x0F); -typedef void * ipc_handle_t; +typedef void *ipc_handle_t; -#define IPC_MAX_PAYLOAD_SIZE 128 -#define IPC_INVALID_HANDLE NULL +#define IPC_MAX_PAYLOAD_SIZE 128 +#define IPC_INVALID_HANDLE NULL /* * Open ipc channel @@ -61,8 +61,7 @@ typedef void * ipc_handle_t; * @return ipc handle or IPC_INVALID_HANDLE if there's error */ ipc_handle_t ipc_open(const enum ipc_peer_id peer_id, - const enum ipc_protocol protocol, - const uint32_t event); + const enum ipc_protocol protocol, const uint32_t event); void ipc_close(const ipc_handle_t handle); /* @@ -74,10 +73,10 @@ void ipc_close(const ipc_handle_t handle); * if > 0, wait for the specified microsecond duration time */ int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size, - int timeout_us); + int timeout_us); /* Write message to ipc channel. */ int ipc_write_timestamp(const ipc_handle_t handle, const void *buf, - const size_t buf_size, uint32_t *timestamp); + const size_t buf_size, uint32_t *timestamp); #endif /* __IPC_HECI_H */ diff --git a/chip/ish/ish_dma.h b/chip/ish/ish_dma.h index 2c76c7d319..fb9c4f4f06 100644 --- a/chip/ish/ish_dma.h +++ b/chip/ish/ish_dma.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/ish/ish_fwst.h b/chip/ish/ish_fwst.h index c114db3241..999546ca34 100644 --- a/chip/ish/ish_fwst.h +++ b/chip/ish/ish_fwst.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,84 +17,84 @@ * IPC link is up(ready) * IPC can be used by other protocols */ -#define IPC_ISH_FWSTS_ILUP_FIELD 0x01 -#define IPC_ISH_FWSTS_ILUP_SHIFT 0 -#define IPC_ISH_FWSTS_ILUP_MASK \ - (IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT) +#define IPC_ISH_FWSTS_ILUP_FIELD 0x01 +#define IPC_ISH_FWSTS_ILUP_SHIFT 0 +#define IPC_ISH_FWSTS_ILUP_MASK \ + (IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT) /* * HECI layer is up(ready) */ -#define IPC_ISH_FWSTS_HUP_FIELD 0x01 -#define IPC_ISH_FWSTS_HUP_SHIFT 1 +#define IPC_ISH_FWSTS_HUP_FIELD 0x01 +#define IPC_ISH_FWSTS_HUP_SHIFT 1 #define IPC_ISH_FWSTS_HUP_MASK \ - (IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT) + (IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT) /* * ISH FW reason reason */ -#define IPC_ISH_FWSTS_FAIL_REASON_FIELD 0x0F -#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT 2 +#define IPC_ISH_FWSTS_FAIL_REASON_FIELD 0x0F +#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT 2 #define IPC_ISH_FWSTS_FAIL_REASON_MASK \ - (IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT) + (IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT) /* * ISH FW reset ID */ -#define IPC_ISH_FWSTS_RESET_ID_FIELD 0x0F -#define IPC_ISH_FWSTS_RESET_ID_SHIFT 8 +#define IPC_ISH_FWSTS_RESET_ID_FIELD 0x0F +#define IPC_ISH_FWSTS_RESET_ID_SHIFT 8 #define IPC_ISH_FWSTS_RESET_ID_MASK \ - (IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT) + (IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT) /* * ISH FW status type */ enum { - FWSTS_AFTER_RESET = 0, - FWSTS_WAIT_FOR_HOST = 4, - FWSTS_START_KERNEL_DMA = 5, - FWSTS_FW_IS_RUNNING = 7, - FWSTS_SENSOR_APP_LOADED = 8, - FWSTS_SENSOR_APP_RUNNING = 15 + FWSTS_AFTER_RESET = 0, + FWSTS_WAIT_FOR_HOST = 4, + FWSTS_START_KERNEL_DMA = 5, + FWSTS_FW_IS_RUNNING = 7, + FWSTS_SENSOR_APP_LOADED = 8, + FWSTS_SENSOR_APP_RUNNING = 15 }; /* * General ISH FW status */ -#define IPC_ISH_FWSTS_FW_STATUS_FIELD 0x0F -#define IPC_ISH_FWSTS_FW_STATUS_SHIFT 12 +#define IPC_ISH_FWSTS_FW_STATUS_FIELD 0x0F +#define IPC_ISH_FWSTS_FW_STATUS_SHIFT 12 #define IPC_ISH_FWSTS_FW_STATUS_MASK \ - (IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT) + (IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT) -#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT 16 +#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD 0x01 +#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT 16 #define IPC_ISH_FWSTS_DMA0_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT) + (IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT) -#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT 17 +#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD 0x01 +#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT 17 #define IPC_ISH_FWSTS_DMA1_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT) + (IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT) -#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT 18 +#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD 0x01 +#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT 18 #define IPC_ISH_FWSTS_DMA2_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT) + (IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT) -#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT 19 +#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD 0x01 +#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT 19 #define IPC_ISH_FWSTS_DMA3_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT) + (IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT) -#define IPC_ISH_FWSTS_POWER_STATE_FIELD 0x0F -#define IPC_ISH_FWSTS_POWER_STATE_SHIFT 20 +#define IPC_ISH_FWSTS_POWER_STATE_FIELD 0x0F +#define IPC_ISH_FWSTS_POWER_STATE_SHIFT 20 #define IPC_ISH_FWSTS_POWER_STATE_MASK \ - (IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT) + (IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT) -#define IPC_ISH_FWSTS_AON_CHECK_FIELD 0x07 -#define IPC_ISH_FWSTS_AON_CHECK_SHIFT 24 +#define IPC_ISH_FWSTS_AON_CHECK_FIELD 0x07 +#define IPC_ISH_FWSTS_AON_CHECK_SHIFT 24 #define IPC_ISH_FWSTS_AON_CHECK_MASK \ - (IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT) + (IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT) /* get ISH FW status register */ static inline uint32_t ish_fwst_get(void) @@ -105,7 +105,7 @@ static inline uint32_t ish_fwst_get(void) /* set IPC link up */ static inline void ish_fwst_set_ilup(void) { - IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_ILUP_SHIFT); + IPC_ISH_FWSTS |= (1 << IPC_ISH_FWSTS_ILUP_SHIFT); } /* clear IPC link up */ @@ -123,7 +123,7 @@ static inline int ish_fwst_is_ilup_set(void) /* set HECI up */ static inline void ish_fwst_set_hup(void) { - IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_HUP_SHIFT); + IPC_ISH_FWSTS |= (1 << IPC_ISH_FWSTS_HUP_SHIFT); } /* clear HECI up */ @@ -144,14 +144,14 @@ static inline void ish_fwst_set_fail_reason(uint32_t val) uint32_t fwst = IPC_ISH_FWSTS; IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FAIL_REASON_MASK) | - (val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT); + (val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT); } /* get fw failure reason */ static inline uint32_t ish_fwst_get_fail_reason(void) { - return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK) - >> IPC_ISH_FWSTS_FAIL_REASON_SHIFT; + return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK) >> + IPC_ISH_FWSTS_FAIL_REASON_SHIFT; } /* set reset id */ @@ -160,14 +160,14 @@ static inline void ish_fwst_set_reset_id(uint32_t val) uint32_t fwst = IPC_ISH_FWSTS; IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) | - (val << IPC_ISH_FWSTS_RESET_ID_SHIFT); + (val << IPC_ISH_FWSTS_RESET_ID_SHIFT); } /* get reset id */ static inline uint32_t ish_fwst_get_reset_id(void) { - return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK) - >> IPC_ISH_FWSTS_RESET_ID_SHIFT; + return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK) >> + IPC_ISH_FWSTS_RESET_ID_SHIFT; } /* set general fw status */ @@ -176,14 +176,14 @@ static inline void ish_fwst_set_fw_status(uint32_t val) uint32_t fwst = IPC_ISH_FWSTS; IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) | - (val << IPC_ISH_FWSTS_FW_STATUS_SHIFT); + (val << IPC_ISH_FWSTS_FW_STATUS_SHIFT); } /* get general fw status */ static inline uint32_t ish_fwst_get_fw_status(void) { - return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK) - >> IPC_ISH_FWSTS_FW_STATUS_SHIFT; + return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK) >> + IPC_ISH_FWSTS_FW_STATUS_SHIFT; } #endif /* __ISH_FWST_H */ diff --git a/chip/ish/ish_i2c.h b/chip/ish/ish_i2c.h index 5b30de775c..c24f4e0cdc 100644 --- a/chip/ish/ish_i2c.h +++ b/chip/ish/ish_i2c.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,23 +9,22 @@ #include <stdint.h> #include "task.h" -#define I2C_TSC_TIMEOUT 2000000 -#define I2C_CALIB_ADDRESS 0x3 -#define I2C_INTERRUPT_TIMEOUT (TICKFREQ / 20) -#define NS_IN_SEC 1000 -#define DEFAULT_SDA_HOLD 240 -#define DEFAULT_SDA_HOLD_STD 2400 -#define DEFAULT_SDA_HOLD_FAST 600 -#define DEFAULT_SDA_HOLD_FAST_PLUS 300 -#define DEFAULT_SDA_HOLD_HIGH 140 -#define NS_2_COUNTERS(ns, clk) ((ns * clk)/NS_IN_SEC) -#define COUNTERS_2_NS(counters, clk) (counters * (NANOSECONDS_IN_SEC / \ - (clk * HZ_IN_MEGAHZ))) -#define I2C_TX_FLUSH_TIMEOUT_USEC 200 +#define I2C_TSC_TIMEOUT 2000000 +#define I2C_CALIB_ADDRESS 0x3 +#define I2C_INTERRUPT_TIMEOUT (TICKFREQ / 20) +#define NS_IN_SEC 1000 +#define DEFAULT_SDA_HOLD 240 +#define DEFAULT_SDA_HOLD_STD 2400 +#define DEFAULT_SDA_HOLD_FAST 600 +#define DEFAULT_SDA_HOLD_FAST_PLUS 300 +#define DEFAULT_SDA_HOLD_HIGH 140 +#define NS_2_COUNTERS(ns, clk) ((ns * clk) / NS_IN_SEC) +#define COUNTERS_2_NS(counters, clk) \ + (counters * (NANOSECONDS_IN_SEC / (clk * HZ_IN_MEGAHZ))) +#define I2C_TX_FLUSH_TIMEOUT_USEC 200 #define ISH_I2C_FIFO_SIZE 64 - enum { /* freq mode values */ I2C_FREQ_25 = 0, @@ -38,29 +37,18 @@ enum { }; const unsigned int clk_in[] = { - [I2C_FREQ_25] = 25, - [I2C_FREQ_50] = 50, - [I2C_FREQ_100] = 100, - [I2C_FREQ_120] = 120, - [I2C_FREQ_40] = 40, - [I2C_FREQ_20] = 20, + [I2C_FREQ_25] = 25, [I2C_FREQ_50] = 50, [I2C_FREQ_100] = 100, + [I2C_FREQ_120] = 120, [I2C_FREQ_40] = 40, [I2C_FREQ_20] = 20, [I2C_FREQ_37] = 37, }; const uint8_t spkln[] = { - [I2C_FREQ_25] = 2, - [I2C_FREQ_50] = 3, - [I2C_FREQ_100] = 5, - [I2C_FREQ_120] = 6, - [I2C_FREQ_40] = 2, - [I2C_FREQ_20] = 1, + [I2C_FREQ_25] = 2, [I2C_FREQ_50] = 3, [I2C_FREQ_100] = 5, + [I2C_FREQ_120] = 6, [I2C_FREQ_40] = 2, [I2C_FREQ_20] = 1, [I2C_FREQ_37] = 2, }; -enum { - I2C_READ, - I2C_WRITE -}; +enum { I2C_READ, I2C_WRITE }; enum { /* REGISTERS */ @@ -125,7 +113,7 @@ enum { IC_10BITADDR_MASTER = 0, /* IC_TAR WRITE VALUES */ IC_10BITADDR_MASTER_VAL = - (IC_10BITADDR_MASTER << IC_10BITADDR_MASTER_OFFSET), + (IC_10BITADDR_MASTER << IC_10BITADDR_MASTER_OFFSET), TAR_SPECIAL_VAL = (TAR_SPECIAL << SPECIAL_OFFSET), /* IC_DATA_CMD OFFSETS */ DATA_CMD_DAT_OFFSET = 0, @@ -180,13 +168,13 @@ struct i2c_bus_info { struct i2c_bus_data fast_speed; struct i2c_bus_data fast_plus_speed; struct i2c_bus_data high_speed; -} __attribute__ ((__packed__)); +} __attribute__((__packed__)); enum i2c_speed { - I2C_SPEED_100KHZ, /* 100kHz */ - I2C_SPEED_400KHZ, /* 400kHz */ - I2C_SPEED_1MHZ, /* 1MHz */ - I2C_SPEED_3M4HZ, /* 3.4MHz */ + I2C_SPEED_100KHZ, /* 100kHz */ + I2C_SPEED_400KHZ, /* 400kHz */ + I2C_SPEED_1MHZ, /* 1MHz */ + I2C_SPEED_3M4HZ, /* 3.4MHz */ }; struct i2c_context { diff --git a/chip/ish/ish_persistent_data.c b/chip/ish/ish_persistent_data.c index 003f781d5f..149acaeade 100644 --- a/chip/ish/ish_persistent_data.c +++ b/chip/ish/ish_persistent_data.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,7 +16,7 @@ struct ish_persistent_data ish_persistent_data = { .magic = PERSISTENT_DATA_MAGIC, .reset_flags = EC_RESET_FLAG_POWER_ON, .watchdog_counter = 0, - .panic_data = {0}, + .panic_data = { 0 }, }; /* @@ -40,8 +40,7 @@ void ish_persistent_data_init(void) { if (ish_persistent_data_aon.magic == PERSISTENT_DATA_MAGIC) { /* Stored data is valid, load a copy */ - memcpy(&ish_persistent_data, - &ish_persistent_data_aon, + memcpy(&ish_persistent_data, &ish_persistent_data_aon, sizeof(struct ish_persistent_data)); /* Invalidate stored data, in case commit fails to happen */ @@ -54,7 +53,6 @@ void ish_persistent_data_init(void) void ish_persistent_data_commit(void) { - memcpy(&ish_persistent_data_aon, - &ish_persistent_data, + memcpy(&ish_persistent_data_aon, &ish_persistent_data, sizeof(struct ish_persistent_data)); } diff --git a/chip/ish/ish_persistent_data.h b/chip/ish/ish_persistent_data.h index 0fd973e1bb..60aa6b94ae 100644 --- a/chip/ish/ish_persistent_data.h +++ b/chip/ish/ish_persistent_data.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c index 70c3b35aa5..83ef0fc91b 100644 --- a/chip/ish/power_mgt.c +++ b/chip/ish/power_mgt.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -52,7 +52,7 @@ static void pg_exit_restore_hw(void) * fixed amount of time to keep the console in use flag true after boot in * order to give a permanent window in which the low speed clock is not used. */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) +#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND) /* power management internal context data structure */ struct pm_context { @@ -172,20 +172,20 @@ static void init_aon_task(void) * limit: 0x67 * Present = 1, DPL = 0 */ - desc_lo = GEN_GDT_DESC_LO((uint32_t)&main_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); - desc_up = GEN_GDT_DESC_UP((uint32_t)&main_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); + desc_lo = GEN_GDT_DESC_LO((uint32_t)&main_tss, GDT_DESC_TSS_LIMIT, + GDT_DESC_TSS_FLAGS); + desc_up = GEN_GDT_DESC_UP((uint32_t)&main_tss, GDT_DESC_TSS_LIMIT, + GDT_DESC_TSS_FLAGS); add_gdt_entry(desc_lo, desc_up); /* set GDT entry 4 for TSS descriptor of aontask * limit: 0x67 * Present = 1, DPL = 0, Accessed = 1 */ - desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); - desc_up = GEN_GDT_DESC_UP((uint32_t)aon_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); + desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_tss, GDT_DESC_TSS_LIMIT, + GDT_DESC_TSS_FLAGS); + desc_up = GEN_GDT_DESC_UP((uint32_t)aon_tss, GDT_DESC_TSS_LIMIT, + GDT_DESC_TSS_FLAGS); pm_ctx.aon_tss_selector[1] = add_gdt_entry(desc_lo, desc_up); /* set GDT entry 5 for LDT descriptor of aontask @@ -205,12 +205,12 @@ static void init_aon_task(void) "pop %eax;"); aon_share->main_fw_ro_addr = (uint32_t)&__aon_ro_start; - aon_share->main_fw_ro_size = (uint32_t)&__aon_ro_end - - (uint32_t)&__aon_ro_start; + aon_share->main_fw_ro_size = + (uint32_t)&__aon_ro_end - (uint32_t)&__aon_ro_start; aon_share->main_fw_rw_addr = (uint32_t)&__aon_rw_start; - aon_share->main_fw_rw_size = (uint32_t)&__aon_rw_end - - (uint32_t)&__aon_rw_start; + aon_share->main_fw_rw_size = + (uint32_t)&__aon_rw_end - (uint32_t)&__aon_rw_start; aon_share->uma_msb = IPC_UMA_RANGE_LOWER_1; @@ -258,8 +258,7 @@ static void switch_to_aontask(void) interrupt_enable(); } -noreturn -static void handle_reset_in_aontask(enum ish_pm_state pm_state) +noreturn static void handle_reset_in_aontask(enum ish_pm_state pm_state) { pm_ctx.aon_share->pm_state = pm_state; @@ -318,10 +317,8 @@ static uint32_t convert_both_edge_gpio_to_single_edge(void) * interrupt trigger mode enabled pins. */ for (i = 0; i < 32; i++) { - if (ISH_GPIO_GIMR & BIT(i) && - ISH_GPIO_GRER & BIT(i) && + if (ISH_GPIO_GIMR & BIT(i) && ISH_GPIO_GRER & BIT(i) && ISH_GPIO_GFER & BIT(i)) { - /* Record the pin so we can restore it later */ both_edge_pins |= BIT(i); @@ -513,7 +510,6 @@ static int d0ix_decide(timestamp_t cur_time, uint32_t idle_us) int pm_state = ISH_PM_STATE_D0I0; if (DEEP_SLEEP_ALLOWED) { - /* check if the console use has expired. */ if (sleep_mask & SLEEP_MASK_CONSOLE) { if (cur_time.val > pm_ctx.console_expire_time.val) { @@ -525,8 +521,7 @@ static int d0ix_decide(timestamp_t cur_time, uint32_t idle_us) } if (IS_ENABLED(CONFIG_ISH_PM_D0I3) && - idle_us >= CONFIG_ISH_D0I3_MIN_USEC && - pm_ctx.aon_valid) + idle_us >= CONFIG_ISH_D0I3_MIN_USEC && pm_ctx.aon_valid) pm_state = ISH_PM_STATE_D0I3; else if (IS_ENABLED(CONFIG_ISH_PM_D0I2) && @@ -633,7 +628,8 @@ void ish_pm_init(void) PMU_MASK_EVENT = ~PMU_MASK_EVENT_BIT_ALL; if (IS_ENABLED(CONFIG_ISH_NEW_PM)) { - PMU_ISH_FABRIC_CNT = (PMU_ISH_FABRIC_CNT & 0xffff0000) | FABRIC_IDLE_COUNT; + PMU_ISH_FABRIC_CNT = (PMU_ISH_FABRIC_CNT & 0xffff0000) | + FABRIC_IDLE_COUNT; PMU_PGCB_CLKGATE_CTRL = TRUNK_CLKGATE_COUNT; } @@ -656,11 +652,9 @@ void ish_pm_init(void) } } -noreturn -void ish_pm_reset(enum ish_pm_state pm_state) +noreturn void ish_pm_reset(enum ish_pm_state pm_state) { - if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) && - pm_ctx.aon_valid) { + if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) && pm_ctx.aon_valid) { handle_reset_in_aontask(pm_state); } else { ish_mia_reset(); @@ -679,8 +673,8 @@ void __idle(void) * time in order to give a fixed window on boot */ disable_sleep(SLEEP_MASK_CONSOLE); - pm_ctx.console_expire_time.val = get_time().val + - CONSOLE_IN_USE_ON_BOOT_TIME; + pm_ctx.console_expire_time.val = + get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME; while (1) { t0 = get_time(); @@ -714,7 +708,7 @@ static void print_stats(const char *name, const struct pm_stat *stat) /** * Print low power idle statistics */ -static int command_idle_stats(int argc, char **argv) +static int command_idle_stats(int argc, const char **argv) { struct ish_aon_share *aon_share = pm_ctx.aon_share; @@ -742,13 +736,11 @@ static int command_idle_stats(int argc, char **argv) DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print power management statistics"); - /** * main FW only need handle PMU wakeup interrupt for D0i1 state, aontask will * handle PMU wakeup interrupt for other low power states */ -__maybe_unused -static void pmu_wakeup_isr(void) +__maybe_unused static void pmu_wakeup_isr(void) { /* at current nothing need to do */ } @@ -763,8 +755,7 @@ DECLARE_IRQ(ISH_PMU_WAKEUP_IRQ, pmu_wakeup_isr); * */ -__maybe_unused noreturn -static void reset_prep_isr(void) +__maybe_unused noreturn static void reset_prep_isr(void) { /* mask reset prep avail interrupt */ PMU_RST_PREP = PMU_RST_PREP_INT_MASK; @@ -784,8 +775,7 @@ static void reset_prep_isr(void) DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_isr); #endif -__maybe_unused -static void handle_d3(uint32_t irq_vec) +__maybe_unused static void handle_d3(uint32_t irq_vec) { PMU_D3_STATUS = PMU_D3_STATUS; @@ -839,5 +829,5 @@ void ish_pm_refresh_console_in_use(void) /* Set console in use expire time. */ pm_ctx.console_expire_time = get_time(); pm_ctx.console_expire_time.val += - pm_ctx.console_in_use_timeout_sec * SECOND; + pm_ctx.console_in_use_timeout_sec * SECOND; } diff --git a/chip/ish/power_mgt.h b/chip/ish/power_mgt.h index a1fd5aabb6..851529ffb1 100644 --- a/chip/ish/power_mgt.h +++ b/chip/ish/power_mgt.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,8 +17,8 @@ extern void clear_fabric_error(void); extern void i2c_port_restore(void); extern void lapic_restore(void); -#define FABRIC_IDLE_COUNT 50 -#define TRUNK_CLKGATE_COUNT 0xf +#define FABRIC_IDLE_COUNT 50 +#define TRUNK_CLKGATE_COUNT 0xf /* power states for ISH */ enum ish_pm_state { @@ -58,8 +58,7 @@ static inline void ish_mia_halt(void) } /* reset ISH mintue-ia cpu core */ -noreturn -static inline void ish_mia_reset(void) +noreturn static inline void ish_mia_reset(void) { /** * ISH HW looks at the rising edge of this bit to diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 08f1ce6ea3..bdd04a7cb2 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -19,99 +19,99 @@ * ISH3.0 has 3 controllers. Locking must occur by-controller (not by-port). */ enum ish_i2c_port { - ISH_I2C0 = 0, /* Controller 0 */ - ISH_I2C1 = 1, /* Controller 1 */ - ISH_I2C2 = 2, /* Controller 2 */ + ISH_I2C0 = 0, /* Controller 0 */ + ISH_I2C1 = 1, /* Controller 1 */ + ISH_I2C2 = 2, /* Controller 2 */ I2C_PORT_COUNT, }; #endif -#define ISH_I2C_PORT_COUNT I2C_PORT_COUNT +#define ISH_I2C_PORT_COUNT I2C_PORT_COUNT /* In ISH, the devices are mapped to pre-defined addresses in the 32-bit * linear address space. */ #ifdef CHIP_VARIANT_ISH5P4 -#define ISH_I2C0_BASE 0x00000000 -#define ISH_I2C1_BASE 0x00002000 -#define ISH_I2C2_BASE 0x00004000 -#define ISH_UART_BASE 0x08100000 -#define ISH_GPIO_BASE 0x00100000 -#define ISH_PMU_BASE 0x04200000 -#define ISH_OCP_BASE 0xFFFFFFFF -#define ISH_MISC_BASE 0x04400000 -#define ISH_DMA_BASE 0x10100000 -#define ISH_CCU_BASE 0x04300000 -#define ISH_IPC_BASE 0x04100000 -#define ISH_WDT_BASE 0x04900000 -#define ISH_IOAPIC_BASE 0xFEC00000 -#define ISH_HPET_BASE 0x04700000 -#define ISH_LAPIC_BASE 0xFEE00000 +#define ISH_I2C0_BASE 0x00000000 +#define ISH_I2C1_BASE 0x00002000 +#define ISH_I2C2_BASE 0x00004000 +#define ISH_UART_BASE 0x08100000 +#define ISH_GPIO_BASE 0x00100000 +#define ISH_PMU_BASE 0x04200000 +#define ISH_OCP_BASE 0xFFFFFFFF +#define ISH_MISC_BASE 0x04400000 +#define ISH_DMA_BASE 0x10100000 +#define ISH_CCU_BASE 0x04300000 +#define ISH_IPC_BASE 0x04100000 +#define ISH_WDT_BASE 0x04900000 +#define ISH_IOAPIC_BASE 0xFEC00000 +#define ISH_HPET_BASE 0x04700000 +#define ISH_LAPIC_BASE 0xFEE00000 #else -#define ISH_I2C0_BASE 0x00100000 -#define ISH_I2C1_BASE 0x00102000 -#define ISH_I2C2_BASE 0x00105000 -#define ISH_UART_BASE 0x00103000 -#define ISH_GPIO_BASE 0x001F0000 -#define ISH_PMU_BASE 0x00800000 -#define ISH_OCP_BASE 0x00700000 -#define ISH_MISC_BASE 0x00C00000 -#define ISH_DMA_BASE 0x00400000 -#define ISH_CCU_BASE 0x00900000 -#define ISH_IPC_BASE 0x00B00000 -#define ISH_WDT_BASE 0xFDE00000 -#define ISH_IOAPIC_BASE 0xFEC00000 -#define ISH_HPET_BASE 0xFED00000 -#define ISH_LAPIC_BASE 0xFEE00000 +#define ISH_I2C0_BASE 0x00100000 +#define ISH_I2C1_BASE 0x00102000 +#define ISH_I2C2_BASE 0x00105000 +#define ISH_UART_BASE 0x00103000 +#define ISH_GPIO_BASE 0x001F0000 +#define ISH_PMU_BASE 0x00800000 +#define ISH_OCP_BASE 0x00700000 +#define ISH_MISC_BASE 0x00C00000 +#define ISH_DMA_BASE 0x00400000 +#define ISH_CCU_BASE 0x00900000 +#define ISH_IPC_BASE 0x00B00000 +#define ISH_WDT_BASE 0xFDE00000 +#define ISH_IOAPIC_BASE 0xFEC00000 +#define ISH_HPET_BASE 0xFED00000 +#define ISH_LAPIC_BASE 0xFEE00000 #endif /* HW interrupt pins mapped to IOAPIC, from I/O sources */ #ifdef CHIP_VARIANT_ISH5P4 -#define ISH_I2C0_IRQ 15 -#define ISH_I2C1_IRQ 16 -#define ISH_FABRIC_IRQ 12 -#define ISH_I2C2_IRQ 17 -#define ISH_WDT_IRQ 26 -#define ISH_GPIO_IRQ 13 -#define ISH_HPET_TIMER1_IRQ 14 -#define ISH_IPC_HOST2ISH_IRQ 0 -#define ISH_PMU_WAKEUP_IRQ 10 -#define ISH_D3_RISE_IRQ 9 -#define ISH_D3_FALL_IRQ 9 -#define ISH_BME_RISE_IRQ 9 -#define ISH_BME_FALL_IRQ 9 -#define ISH_IPC_ISH2HOST_CLR_IRQ 0 -#define ISH_UART0_IRQ 23 -#define ISH_UART1_IRQ 24 -#define ISH_RESET_PREP_IRQ 6 +#define ISH_I2C0_IRQ 15 +#define ISH_I2C1_IRQ 16 +#define ISH_FABRIC_IRQ 12 +#define ISH_I2C2_IRQ 17 +#define ISH_WDT_IRQ 26 +#define ISH_GPIO_IRQ 13 +#define ISH_HPET_TIMER1_IRQ 14 +#define ISH_IPC_HOST2ISH_IRQ 0 +#define ISH_PMU_WAKEUP_IRQ 10 +#define ISH_D3_RISE_IRQ 9 +#define ISH_D3_FALL_IRQ 9 +#define ISH_BME_RISE_IRQ 9 +#define ISH_BME_FALL_IRQ 9 +#define ISH_IPC_ISH2HOST_CLR_IRQ 0 +#define ISH_UART0_IRQ 23 +#define ISH_UART1_IRQ 24 +#define ISH_RESET_PREP_IRQ 6 #else -#define ISH_I2C0_IRQ 0 -#define ISH_I2C1_IRQ 1 -#define ISH_FABRIC_IRQ 5 -#define ISH_I2C2_IRQ 40 -#define ISH_WDT_IRQ 6 -#define ISH_GPIO_IRQ 7 -#define ISH_HPET_TIMER1_IRQ 8 -#define ISH_IPC_HOST2ISH_IRQ 12 -#define ISH_PMU_WAKEUP_IRQ 18 -#define ISH_D3_RISE_IRQ 19 -#define ISH_D3_FALL_IRQ 29 -#define ISH_BME_RISE_IRQ 50 -#define ISH_BME_FALL_IRQ 51 -#define ISH_IPC_ISH2HOST_CLR_IRQ 24 -#define ISH_UART0_IRQ 34 -#define ISH_UART1_IRQ 35 -#define ISH_RESET_PREP_IRQ 62 +#define ISH_I2C0_IRQ 0 +#define ISH_I2C1_IRQ 1 +#define ISH_FABRIC_IRQ 5 +#define ISH_I2C2_IRQ 40 +#define ISH_WDT_IRQ 6 +#define ISH_GPIO_IRQ 7 +#define ISH_HPET_TIMER1_IRQ 8 +#define ISH_IPC_HOST2ISH_IRQ 12 +#define ISH_PMU_WAKEUP_IRQ 18 +#define ISH_D3_RISE_IRQ 19 +#define ISH_D3_FALL_IRQ 29 +#define ISH_BME_RISE_IRQ 50 +#define ISH_BME_FALL_IRQ 51 +#define ISH_IPC_ISH2HOST_CLR_IRQ 24 +#define ISH_UART0_IRQ 34 +#define ISH_UART1_IRQ 35 +#define ISH_RESET_PREP_IRQ 62 #endif /* Interrupt vectors 0-31 are architecture reserved. * Vectors 32-255 are user-defined. */ -#define USER_VEC_START 32 +#define USER_VEC_START 32 /* Map IRQs to vectors after offset 10 for certain APIC interrupts */ -#define IRQ_TO_VEC(irq) ((irq) + USER_VEC_START + 10) -#define VEC_TO_IRQ(vec) ((vec) - USER_VEC_START - 10) +#define IRQ_TO_VEC(irq) ((irq) + USER_VEC_START + 10) +#define VEC_TO_IRQ(vec) ((vec)-USER_VEC_START - 10) /* ISH GPIO Registers */ #define ISH_GPIO_GCCR REG32(ISH_GPIO_BASE + 0x000) /* Direction lock */ @@ -129,322 +129,322 @@ enum ish_i2c_port { #define ISH_GPIO_GSEC REG32(ISH_GPIO_BASE + 0x130) /* Secure Input */ /* APIC interrupt vectors */ -#define ISH_TS_VECTOR 0x20 /* Task switch vector */ -#define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */ -#define SOFTIRQ_VECTOR 0x22 /* Handles software generated IRQs */ -#define LAPIC_SPURIOUS_INT_VECTOR 0xff +#define ISH_TS_VECTOR 0x20 /* Task switch vector */ +#define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */ +#define SOFTIRQ_VECTOR 0x22 /* Handles software generated IRQs */ +#define LAPIC_SPURIOUS_INT_VECTOR 0xff /* Interrupt to vector mapping. To be programmed into IOAPIC */ -#define ISH_I2C0_VEC IRQ_TO_VEC(ISH_I2C0_IRQ) -#define ISH_I2C1_VEC IRQ_TO_VEC(ISH_I2C1_IRQ) -#define ISH_I2C2_VEC IRQ_TO_VEC(ISH_I2C2_IRQ) -#define ISH_WDT_VEC IRQ_TO_VEC(ISH_WDT_IRQ) -#define ISH_GPIO_VEC IRQ_TO_VEC(ISH_GPIO_IRQ) -#define ISH_HPET_TIMER1_VEC IRQ_TO_VEC(ISH_HPET_TIMER1_IRQ) -#define ISH_IPC_ISH2HOST_CLR_VEC IRQ_TO_VEC(ISH_IPC_ISH2HOST_CLR_IRQ) -#define ISH_UART0_VEC IRQ_TO_VEC(ISH_UART0_IRQ) -#define ISH_UART1_VEC IRQ_TO_VEC(ISH_UART1_IRQ) -#define ISH_IPC_VEC IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ) -#define ISH_RESET_PREP_VEC IRQ_TO_VEC(ISH_RESET_PREP_IRQ) -#define ISH_PMU_WAKEUP_VEC IRQ_TO_VEC(ISH_PMU_WAKEUP_IRQ) -#define ISH_D3_RISE_VEC IRQ_TO_VEC(ISH_D3_RISE_IRQ) -#define ISH_D3_FALL_VEC IRQ_TO_VEC(ISH_D3_FALL_IRQ) -#define ISH_BME_RISE_VEC IRQ_TO_VEC(ISH_BME_RISE_IRQ) -#define ISH_BME_FALL_VEC IRQ_TO_VEC(ISH_BME_FALL_IRQ) -#define ISH_FABRIC_VEC IRQ_TO_VEC(ISH_FABRIC_IRQ) - -#define ISH_DEBUG_UART UART_PORT_0 -#define ISH_DEBUG_UART_IRQ ISH_UART0_IRQ -#define ISH_DEBUG_UART_VEC ISH_UART0_VEC +#define ISH_I2C0_VEC IRQ_TO_VEC(ISH_I2C0_IRQ) +#define ISH_I2C1_VEC IRQ_TO_VEC(ISH_I2C1_IRQ) +#define ISH_I2C2_VEC IRQ_TO_VEC(ISH_I2C2_IRQ) +#define ISH_WDT_VEC IRQ_TO_VEC(ISH_WDT_IRQ) +#define ISH_GPIO_VEC IRQ_TO_VEC(ISH_GPIO_IRQ) +#define ISH_HPET_TIMER1_VEC IRQ_TO_VEC(ISH_HPET_TIMER1_IRQ) +#define ISH_IPC_ISH2HOST_CLR_VEC IRQ_TO_VEC(ISH_IPC_ISH2HOST_CLR_IRQ) +#define ISH_UART0_VEC IRQ_TO_VEC(ISH_UART0_IRQ) +#define ISH_UART1_VEC IRQ_TO_VEC(ISH_UART1_IRQ) +#define ISH_IPC_VEC IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ) +#define ISH_RESET_PREP_VEC IRQ_TO_VEC(ISH_RESET_PREP_IRQ) +#define ISH_PMU_WAKEUP_VEC IRQ_TO_VEC(ISH_PMU_WAKEUP_IRQ) +#define ISH_D3_RISE_VEC IRQ_TO_VEC(ISH_D3_RISE_IRQ) +#define ISH_D3_FALL_VEC IRQ_TO_VEC(ISH_D3_FALL_IRQ) +#define ISH_BME_RISE_VEC IRQ_TO_VEC(ISH_BME_RISE_IRQ) +#define ISH_BME_FALL_VEC IRQ_TO_VEC(ISH_BME_FALL_IRQ) +#define ISH_FABRIC_VEC IRQ_TO_VEC(ISH_FABRIC_IRQ) + +#define ISH_DEBUG_UART UART_PORT_0 +#define ISH_DEBUG_UART_IRQ ISH_UART0_IRQ +#define ISH_DEBUG_UART_VEC ISH_UART0_VEC /* IPC_Registers */ -#define IPC_PISR REG32(ISH_IPC_BASE + 0x0) -#define IPC_PISR_HOST2ISH_BIT BIT(0) - -#define IPC_PIMR REG32(ISH_IPC_BASE + 0x4) -#define IPC_PIMR_HOST2ISH_BIT BIT(0) -#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11) -#define IPC_PIMR_CSME_CSR_BIT BIT(23) -#define IPC_ISH2HOST_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0x60) -#define IPC_ISH_FWSTS REG32(ISH_IPC_BASE + 0x34) -#define IPC_HOST2ISH_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x48) -#define IPC_HOST2ISH_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0xE0) -#define IPC_ISH2HOST_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x54) -#define IPC_ISH2PMC_DOORBELL REG32(ISH_IPC_BASE + 0x58) -#define IPC_ISH2PMC_MSG_BASE (ISH_IPC_BASE + 0x260) -#define IPC_ISH_RMP0 REG32(ISH_IPC_BASE + 0x360) -#define IPC_ISH_RMP1 REG32(ISH_IPC_BASE + 0x364) -#define IPC_ISH_RMP2 REG32(ISH_IPC_BASE + 0x368) -#define DMA_ENABLED_MASK BIT(0) -#define IPC_BUSY_CLEAR REG32(ISH_IPC_BASE + 0x378) -#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0) - -#define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380) -#define IPC_UMA_RANGE_LOWER_1 REG32(ISH_IPC_BASE + 0x384) -#define IPC_UMA_RANGE_UPPER_0 REG32(ISH_IPC_BASE + 0x388) -#define IPC_UMA_RANGE_UPPER_1 REG32(ISH_IPC_BASE + 0x38C) +#define IPC_PISR REG32(ISH_IPC_BASE + 0x0) +#define IPC_PISR_HOST2ISH_BIT BIT(0) + +#define IPC_PIMR REG32(ISH_IPC_BASE + 0x4) +#define IPC_PIMR_HOST2ISH_BIT BIT(0) +#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11) +#define IPC_PIMR_CSME_CSR_BIT BIT(23) +#define IPC_ISH2HOST_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0x60) +#define IPC_ISH_FWSTS REG32(ISH_IPC_BASE + 0x34) +#define IPC_HOST2ISH_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x48) +#define IPC_HOST2ISH_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0xE0) +#define IPC_ISH2HOST_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x54) +#define IPC_ISH2PMC_DOORBELL REG32(ISH_IPC_BASE + 0x58) +#define IPC_ISH2PMC_MSG_BASE (ISH_IPC_BASE + 0x260) +#define IPC_ISH_RMP0 REG32(ISH_IPC_BASE + 0x360) +#define IPC_ISH_RMP1 REG32(ISH_IPC_BASE + 0x364) +#define IPC_ISH_RMP2 REG32(ISH_IPC_BASE + 0x368) +#define DMA_ENABLED_MASK BIT(0) +#define IPC_BUSY_CLEAR REG32(ISH_IPC_BASE + 0x378) +#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0) + +#define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380) +#define IPC_UMA_RANGE_LOWER_1 REG32(ISH_IPC_BASE + 0x384) +#define IPC_UMA_RANGE_UPPER_0 REG32(ISH_IPC_BASE + 0x388) +#define IPC_UMA_RANGE_UPPER_1 REG32(ISH_IPC_BASE + 0x38C) /* PMU Registers */ -#define PMU_SRAM_PG_EN REG32(ISH_PMU_BASE + 0x0) +#define PMU_SRAM_PG_EN REG32(ISH_PMU_BASE + 0x0) #ifndef CHIP_VARIANT_ISH5P4 -#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x4) -#define PMU_D3_BIT_SET BIT(0) -#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(1) -#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(2) -#define PMU_D3_BIT_RISING_EDGE_MASK BIT(3) -#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(4) -#define PMU_BME_BIT_SET BIT(5) -#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(6) +#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x4) +#define PMU_D3_BIT_SET BIT(0) +#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(1) +#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(2) +#define PMU_D3_BIT_RISING_EDGE_MASK BIT(3) +#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(4) +#define PMU_BME_BIT_SET BIT(5) +#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(6) #define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(7) -#define PMU_BME_BIT_RISING_EDGE_MASK BIT(8) -#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(9) +#define PMU_BME_BIT_RISING_EDGE_MASK BIT(8) +#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(9) #else -#define PMU_STATUS_REG_ADDR (ISH_PMU_BASE + 0xF00) -#define PMU_SCRATCHPAD0_REG_ADDR (ISH_PMU_BASE + 0xF04) -#define PMU_SCRATCHPAD1_REG_ADDR (ISH_PMU_BASE + 0xF08) -#define PMU_PG_EN_REG_ADDR (ISH_PMU_BASE + 0xF10) -#define PMU_PMC_HOST_RST_CTL REG32(ISH_PMU_BASE + 0xF20) -#define PMU_SW_PG_REQ REG32(ISH_PMU_BASE + 0xF14) -#define PMU_PMC_PG_WAKE REG32(ISH_PMU_BASE + 0xF18) -#define PMU_INTERNAL_PCE REG32(ISH_PMU_BASE + 0xF30) -#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x100) -#define PMU_HOST_RST_B BIT(0) -#define PMU_PCE_SHADOW_MASK 0x1F -#define PMU_PCE_PG_ALLOWED BIT(4) -#define PMU_PCE_CHANGE_MASK BIT(9) -#define PMU_PCE_CHANGE_DETECTED BIT(8) -#define PMU_PCE_PMCRE BIT(0) -#define PMU_SW_PG_REQ_B_VAL BIT(0) -#define PMU_SW_PG_REQ_B_RISE BIT(1) -#define PMU_SW_PG_REQ_B_FALL BIT(2) -#define PMU_PMC_PG_WAKE_VAL BIT(0) -#define PMU_PMC_PG_WAKE_RISE BIT(1) -#define PMU_PMC_PG_WAKE_FALL BIT(2) -#define PMU_PCE_PG_ALLOWED BIT(4) -#define PMU_D0I3_ENABLE_MASK BIT(23) -#define PMU_D3_BIT_SET BIT(16) -#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(17) -#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(18) -#define PMU_D3_BIT_RISING_EDGE_MASK BIT(19) -#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(20) -#define PMU_BME_BIT_SET BIT(24) -#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(25) -#define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(26) -#define PMU_BME_BIT_RISING_EDGE_MASK BIT(27) -#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(28) +#define PMU_STATUS_REG_ADDR (ISH_PMU_BASE + 0xF00) +#define PMU_SCRATCHPAD0_REG_ADDR (ISH_PMU_BASE + 0xF04) +#define PMU_SCRATCHPAD1_REG_ADDR (ISH_PMU_BASE + 0xF08) +#define PMU_PG_EN_REG_ADDR (ISH_PMU_BASE + 0xF10) +#define PMU_PMC_HOST_RST_CTL REG32(ISH_PMU_BASE + 0xF20) +#define PMU_SW_PG_REQ REG32(ISH_PMU_BASE + 0xF14) +#define PMU_PMC_PG_WAKE REG32(ISH_PMU_BASE + 0xF18) +#define PMU_INTERNAL_PCE REG32(ISH_PMU_BASE + 0xF30) +#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x100) +#define PMU_HOST_RST_B BIT(0) +#define PMU_PCE_SHADOW_MASK 0x1F +#define PMU_PCE_PG_ALLOWED BIT(4) +#define PMU_PCE_CHANGE_MASK BIT(9) +#define PMU_PCE_CHANGE_DETECTED BIT(8) +#define PMU_PCE_PMCRE BIT(0) +#define PMU_SW_PG_REQ_B_VAL BIT(0) +#define PMU_SW_PG_REQ_B_RISE BIT(1) +#define PMU_SW_PG_REQ_B_FALL BIT(2) +#define PMU_PMC_PG_WAKE_VAL BIT(0) +#define PMU_PMC_PG_WAKE_RISE BIT(1) +#define PMU_PMC_PG_WAKE_FALL BIT(2) +#define PMU_PCE_PG_ALLOWED BIT(4) +#define PMU_D0I3_ENABLE_MASK BIT(23) +#define PMU_D3_BIT_SET BIT(16) +#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(17) +#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(18) +#define PMU_D3_BIT_RISING_EDGE_MASK BIT(19) +#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(20) +#define PMU_BME_BIT_SET BIT(24) +#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(25) +#define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(26) +#define PMU_BME_BIT_RISING_EDGE_MASK BIT(27) +#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(28) #endif -#define PMU_GPIO_WAKE_MASK0 REG32(ISH_PMU_BASE + 0x250) -#define PMU_GPIO_WAKE_MASK1 REG32(ISH_PMU_BASE + 0x254) +#define PMU_GPIO_WAKE_MASK0 REG32(ISH_PMU_BASE + 0x250) +#define PMU_GPIO_WAKE_MASK1 REG32(ISH_PMU_BASE + 0x254) -#define PMU_ISH_FABRIC_CNT REG32(ISH_PMU_BASE + 0x18) +#define PMU_ISH_FABRIC_CNT REG32(ISH_PMU_BASE + 0x18) -#define PMU_PGCB_CLKGATE_CTRL REG32(ISH_PMU_BASE + 0x54) +#define PMU_PGCB_CLKGATE_CTRL REG32(ISH_PMU_BASE + 0x54) -#define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c) -#define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */ +#define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c) +#define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */ -#define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40) -#define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */ +#define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40) +#define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */ -#define PMU_VNNAON_RED REG32(ISH_PMU_BASE + 0x58) +#define PMU_VNNAON_RED REG32(ISH_PMU_BASE + 0x58) -#define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c) -#define PMU_RST_PREP_GET BIT(0) -#define PMU_RST_PREP_AVAIL BIT(1) -#define PMU_RST_PREP_INT_MASK BIT(31) +#define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c) +#define PMU_RST_PREP_GET BIT(0) +#define PMU_RST_PREP_AVAIL BIT(1) +#define PMU_RST_PREP_INT_MASK BIT(31) -#define VNN_ID_DMA0 4 -#define VNN_ID_DMA(chan) (VNN_ID_DMA0 + chan) +#define VNN_ID_DMA0 4 +#define VNN_ID_DMA(chan) (VNN_ID_DMA0 + chan) /* OCP registers */ -#define OCP_IOSF2OCP_BRIDGE (ISH_OCP_BASE + 0x9400) -#define OCP_AGENT_CONTROL REG32(OCP_IOSF2OCP_BRIDGE + 0x20) -#define OCP_RESPONSE_TO_DISABLE 0xFFFFF8FF +#define OCP_IOSF2OCP_BRIDGE (ISH_OCP_BASE + 0x9400) +#define OCP_AGENT_CONTROL REG32(OCP_IOSF2OCP_BRIDGE + 0x20) +#define OCP_RESPONSE_TO_DISABLE 0xFFFFF8FF /* MISC registers */ -#define MISC_REG_BASE ISH_MISC_BASE -#define DMA_REG_BASE ISH_DMA_BASE +#define MISC_REG_BASE ISH_MISC_BASE +#define DMA_REG_BASE ISH_DMA_BASE #ifndef CHIP_VARIANT_ISH5P4 -#define MISC_CHID_CFG_REG REG32(MISC_REG_BASE + 0x40) -#define MISC_DMA_CTL_REG(ch) REG32(MISC_REG_BASE + (4 * (ch))) -#define MISC_SRC_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x20 + (4 * (ch))) -#define MISC_DST_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x80 + (4 * (ch))) -#define MISC_ISH_ECC_ERR_SRESP REG32(MISC_REG_BASE + 0x94) +#define MISC_CHID_CFG_REG REG32(MISC_REG_BASE + 0x40) +#define MISC_DMA_CTL_REG(ch) REG32(MISC_REG_BASE + (4 * (ch))) +#define MISC_SRC_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x20 + (4 * (ch))) +#define MISC_DST_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x80 + (4 * (ch))) +#define MISC_ISH_ECC_ERR_SRESP REG32(MISC_REG_BASE + 0x94) #else -#define DMA_MISC_OFFSET 0x1000 -#define DMA_MISC_BASE (DMA_REG_BASE + DMA_MISC_OFFSET) -#define MISC_CHID_CFG_REG REG32(DMA_MISC_BASE + 0x400) -#define MISC_DMA_CTL_REG(ch) REG32(DMA_MISC_BASE + (4 * (ch))) -#define MISC_SRC_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x100 + (4 * (ch))) -#define MISC_DST_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x200 + (4 * (ch))) -#define MISC_ISH_ECC_ERR_SRESP REG32(DMA_MISC_BASE + 0x404) +#define DMA_MISC_OFFSET 0x1000 +#define DMA_MISC_BASE (DMA_REG_BASE + DMA_MISC_OFFSET) +#define MISC_CHID_CFG_REG REG32(DMA_MISC_BASE + 0x400) +#define MISC_DMA_CTL_REG(ch) REG32(DMA_MISC_BASE + (4 * (ch))) +#define MISC_SRC_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x100 + (4 * (ch))) +#define MISC_DST_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x200 + (4 * (ch))) +#define MISC_ISH_ECC_ERR_SRESP REG32(DMA_MISC_BASE + 0x404) #endif -#define MISC_ISH_RTC_COUNTER0 REG32(ISH_MISC_BASE + 0x70) -#define MISC_ISH_RTC_COUNTER1 REG32(ISH_MISC_BASE + 0x74) +#define MISC_ISH_RTC_COUNTER0 REG32(ISH_MISC_BASE + 0x70) +#define MISC_ISH_RTC_COUNTER1 REG32(ISH_MISC_BASE + 0x74) /* DMA registers */ -#define DMA_CH_REGS_SIZE 0x58 -#define DMA_CLR_BLOCK_REG REG32(DMA_REG_BASE + 0x340) -#define DMA_CLR_ERR_REG REG32(DMA_REG_BASE + 0x358) -#define DMA_EN_REG_ADDR (DMA_REG_BASE + 0x3A0) -#define DMA_EN_REG REG32(DMA_EN_REG_ADDR) -#define DMA_CFG_REG REG32(DMA_REG_BASE + 0x398) -#define DMA_PSIZE_01 REG32(DMA_REG_BASE + 0x400) -#define DMA_PSIZE_CHAN0_SIZE 512 -#define DMA_PSIZE_CHAN0_OFFSET 0 -#define DMA_PSIZE_CHAN1_SIZE 128 -#define DMA_PSIZE_CHAN1_OFFSET 13 -#define DMA_PSIZE_UPDATE BIT(26) -#define DMA_MAX_CHANNEL 4 -#define DMA_SAR(chan) REG32(chan + 0x000) -#define DMA_DAR(chan) REG32(chan + 0x008) -#define DMA_LLP(chan) REG32(chan + 0x010) -#define DMA_CTL_LOW(chan) REG32(chan + 0x018) -#define DMA_CTL_HIGH(chan) REG32(chan + 0x018 + 0x4) -#define DMA_CTL_INT_ENABLE BIT(0) -#define DMA_CTL_DST_TR_WIDTH_SHIFT 1 -#define DMA_CTL_SRC_TR_WIDTH_SHIFT 4 -#define DMA_CTL_DINC_SHIFT 7 -#define DMA_CTL_SINC_SHIFT 9 -#define DMA_CTL_ADDR_INC 0 -#define DMA_CTL_DEST_MSIZE_SHIFT 11 -#define DMA_CTL_SRC_MSIZE_SHIFT 14 -#define DMA_CTL_TT_FC_SHIFT 20 -#define DMA_CTL_TT_FC_M2M_DMAC 0 -#define DMA_ENABLE BIT(0) -#define DMA_CH_EN_BIT(n) BIT(n) -#define DMA_CH_EN_WE_BIT(n) BIT(8 + (n)) -#define DMA_MAX_BLOCK_SIZE (4096) -#define SRC_TR_WIDTH 2 -#define SRC_BURST_SIZE 3 -#define DEST_TR_WIDTH 2 -#define DEST_BURST_SIZE 3 - -#define PMU_MASK_EVENT REG32(ISH_PMU_BASE + 0x10) -#define PMU_MASK_EVENT_BIT_GPIO(pin) BIT(pin) -#define PMU_MASK_EVENT_BIT_HPET BIT(16) -#define PMU_MASK_EVENT_BIT_IPC BIT(17) -#define PMU_MASK_EVENT_BIT_D3 BIT(18) -#define PMU_MASK_EVENT_BIT_DMA BIT(19) -#define PMU_MASK_EVENT_BIT_I2C0 BIT(20) -#define PMU_MASK_EVENT_BIT_I2C1 BIT(21) -#define PMU_MASK_EVENT_BIT_SPI BIT(22) -#define PMU_MASK_EVENT_BIT_UART BIT(23) -#define PMU_MASK_EVENT_BIT_ALL (0xffffffff) - -#define PMU_RF_ROM_PWR_CTRL REG32(ISH_PMU_BASE + 0x30) - -#define PMU_LDO_CTRL REG32(ISH_PMU_BASE + 0x44) -#define PMU_LDO_ENABLE_BIT BIT(0) -#define PMU_LDO_RETENTION_BIT BIT(1) -#define PMU_LDO_CALIBRATION_BIT BIT(2) -#define PMU_LDO_READY_BIT BIT(3) +#define DMA_CH_REGS_SIZE 0x58 +#define DMA_CLR_BLOCK_REG REG32(DMA_REG_BASE + 0x340) +#define DMA_CLR_ERR_REG REG32(DMA_REG_BASE + 0x358) +#define DMA_EN_REG_ADDR (DMA_REG_BASE + 0x3A0) +#define DMA_EN_REG REG32(DMA_EN_REG_ADDR) +#define DMA_CFG_REG REG32(DMA_REG_BASE + 0x398) +#define DMA_PSIZE_01 REG32(DMA_REG_BASE + 0x400) +#define DMA_PSIZE_CHAN0_SIZE 512 +#define DMA_PSIZE_CHAN0_OFFSET 0 +#define DMA_PSIZE_CHAN1_SIZE 128 +#define DMA_PSIZE_CHAN1_OFFSET 13 +#define DMA_PSIZE_UPDATE BIT(26) +#define DMA_MAX_CHANNEL 4 +#define DMA_SAR(chan) REG32(chan + 0x000) +#define DMA_DAR(chan) REG32(chan + 0x008) +#define DMA_LLP(chan) REG32(chan + 0x010) +#define DMA_CTL_LOW(chan) REG32(chan + 0x018) +#define DMA_CTL_HIGH(chan) REG32(chan + 0x018 + 0x4) +#define DMA_CTL_INT_ENABLE BIT(0) +#define DMA_CTL_DST_TR_WIDTH_SHIFT 1 +#define DMA_CTL_SRC_TR_WIDTH_SHIFT 4 +#define DMA_CTL_DINC_SHIFT 7 +#define DMA_CTL_SINC_SHIFT 9 +#define DMA_CTL_ADDR_INC 0 +#define DMA_CTL_DEST_MSIZE_SHIFT 11 +#define DMA_CTL_SRC_MSIZE_SHIFT 14 +#define DMA_CTL_TT_FC_SHIFT 20 +#define DMA_CTL_TT_FC_M2M_DMAC 0 +#define DMA_ENABLE BIT(0) +#define DMA_CH_EN_BIT(n) BIT(n) +#define DMA_CH_EN_WE_BIT(n) BIT(8 + (n)) +#define DMA_MAX_BLOCK_SIZE (4096) +#define SRC_TR_WIDTH 2 +#define SRC_BURST_SIZE 3 +#define DEST_TR_WIDTH 2 +#define DEST_BURST_SIZE 3 + +#define PMU_MASK_EVENT REG32(ISH_PMU_BASE + 0x10) +#define PMU_MASK_EVENT_BIT_GPIO(pin) BIT(pin) +#define PMU_MASK_EVENT_BIT_HPET BIT(16) +#define PMU_MASK_EVENT_BIT_IPC BIT(17) +#define PMU_MASK_EVENT_BIT_D3 BIT(18) +#define PMU_MASK_EVENT_BIT_DMA BIT(19) +#define PMU_MASK_EVENT_BIT_I2C0 BIT(20) +#define PMU_MASK_EVENT_BIT_I2C1 BIT(21) +#define PMU_MASK_EVENT_BIT_SPI BIT(22) +#define PMU_MASK_EVENT_BIT_UART BIT(23) +#define PMU_MASK_EVENT_BIT_ALL (0xffffffff) + +#define PMU_RF_ROM_PWR_CTRL REG32(ISH_PMU_BASE + 0x30) + +#define PMU_LDO_CTRL REG32(ISH_PMU_BASE + 0x44) +#define PMU_LDO_ENABLE_BIT BIT(0) +#define PMU_LDO_RETENTION_BIT BIT(1) +#define PMU_LDO_CALIBRATION_BIT BIT(2) +#define PMU_LDO_READY_BIT BIT(3) /* CCU Registers */ -#define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0) -#define CCU_BCG_EN REG32(ISH_CCU_BASE + 0x4) +#define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0) +#define CCU_BCG_EN REG32(ISH_CCU_BASE + 0x4) #ifndef CHIP_VARIANT_ISH5P4 -#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x8) -#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x34) /* Reset history */ -#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x38) -#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x3c) +#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x8) +#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x34) /* Reset history */ +#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x38) +#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x3c) #else -#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x7c) -#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x3c) /* Reset history */ -#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x40) -#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x44) +#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x7c) +#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x3c) /* Reset history */ +#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x40) +#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x44) #endif -#define CCU_BCG_MIA REG32(ISH_CCU_BASE + 0x4) -#define CCU_BCG_UART REG32(ISH_CCU_BASE + 0x8) -#define CCU_BCG_I2C REG32(ISH_CCU_BASE + 0xc) -#define CCU_BCG_SPI REG32(ISH_CCU_BASE + 0x10) -#define CCU_BCG_GPIO REG32(ISH_CCU_BASE + 0x14) -#define CCU_BCG_DMA REG32(ISH_CCU_BASE + 0x28) -#define CCU_AONCG_EN REG32(ISH_CCU_BASE + 0xdc) -#define CCU_BCG_BIT_MIA BIT(0) -#define CCU_BCG_BIT_DMA BIT(1) -#define CCU_BCG_BIT_I2C0 BIT(2) -#define CCU_BCG_BIT_I2C1 BIT(3) -#define CCU_BCG_BIT_SPI BIT(4) -#define CCU_BCG_BIT_SRAM BIT(5) -#define CCU_BCG_BIT_HPET BIT(6) -#define CCU_BCG_BIT_UART BIT(7) -#define CCU_BCG_BIT_GPIO BIT(8) -#define CCU_BCG_BIT_I2C2 BIT(9) -#define CCU_BCG_BIT_SPI2 BIT(10) -#define CCU_BCG_BIT_ALL (0x7ff) +#define CCU_BCG_MIA REG32(ISH_CCU_BASE + 0x4) +#define CCU_BCG_UART REG32(ISH_CCU_BASE + 0x8) +#define CCU_BCG_I2C REG32(ISH_CCU_BASE + 0xc) +#define CCU_BCG_SPI REG32(ISH_CCU_BASE + 0x10) +#define CCU_BCG_GPIO REG32(ISH_CCU_BASE + 0x14) +#define CCU_BCG_DMA REG32(ISH_CCU_BASE + 0x28) +#define CCU_AONCG_EN REG32(ISH_CCU_BASE + 0xdc) +#define CCU_BCG_BIT_MIA BIT(0) +#define CCU_BCG_BIT_DMA BIT(1) +#define CCU_BCG_BIT_I2C0 BIT(2) +#define CCU_BCG_BIT_I2C1 BIT(3) +#define CCU_BCG_BIT_SPI BIT(4) +#define CCU_BCG_BIT_SRAM BIT(5) +#define CCU_BCG_BIT_HPET BIT(6) +#define CCU_BCG_BIT_UART BIT(7) +#define CCU_BCG_BIT_GPIO BIT(8) +#define CCU_BCG_BIT_I2C2 BIT(9) +#define CCU_BCG_BIT_SPI2 BIT(10) +#define CCU_BCG_BIT_ALL (0x7ff) /* Bitmasks for CCU_RST_HST */ -#define CCU_SW_RST BIT(0) /* Used to indicate SW reset */ -#define CCU_WDT_RST BIT(1) /* Used to indicate WDT reset */ -#define CCU_MIASS_RST BIT(2) /* Used to indicate UIA shutdown reset */ -#define CCU_SRECC_RST BIT(3) /* Used to indicate SRAM ECC reset */ +#define CCU_SW_RST BIT(0) /* Used to indicate SW reset */ +#define CCU_WDT_RST BIT(1) /* Used to indicate WDT reset */ +#define CCU_MIASS_RST BIT(2) /* Used to indicate UIA shutdown reset */ +#define CCU_SRECC_RST BIT(3) /* Used to indicate SRAM ECC reset */ /* Fabric Agent Status register */ -#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828) +#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828) #define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29) -#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28) -#define FABRIC_M_ERR_BIT BIT(24) -#define FABRIC_MIA_STATUS_BIT_ERR (FABRIC_INBAND_ERR_SECONDARY_BIT | \ - FABRIC_INBAND_ERR_PRIMARY_BIT | \ - FABRIC_M_ERR_BIT) +#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28) +#define FABRIC_M_ERR_BIT BIT(24) +#define FABRIC_MIA_STATUS_BIT_ERR \ + (FABRIC_INBAND_ERR_SECONDARY_BIT | FABRIC_INBAND_ERR_PRIMARY_BIT | \ + FABRIC_M_ERR_BIT) /* CSME Registers */ #ifdef CHIP_VARIANT_ISH5P4 -#define SEC_OFFSET 0x10000 +#define SEC_OFFSET 0x10000 #else -#define SEC_OFFSET 0x0 +#define SEC_OFFSET 0x0 #endif -#define ISH_RST_REG REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44) -#define IPC_PIMR_CIM_SEC (ISH_IPC_BASE + SEC_OFFSET + 0x10) +#define ISH_RST_REG REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44) +#define IPC_PIMR_CIM_SEC (ISH_IPC_BASE + SEC_OFFSET + 0x10) /* IOAPIC registers */ -#define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0) -#define IOAPIC_WDW REG32(ISH_IOAPIC_BASE + 0x10) +#define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0) +#define IOAPIC_WDW REG32(ISH_IOAPIC_BASE + 0x10) /* Bare address needed for assembler (ISH_IOAPIC_BASE + 0x40) */ -#define IOAPIC_EOI_REG_ADDR 0xFEC00040 -#define IOAPIC_EOI_REG REG32(IOAPIC_EOI_REG_ADDR) - -#define IOAPIC_VERSION (0x1) -#define IOAPIC_IOREDTBL (0x10) -#define IOAPIC_REDTBL_DELMOD_FIXED (0x00000000) -#define IOAPIC_REDTBL_DESTMOD_PHYS (0x00000000) -#define IOAPIC_REDTBL_INTPOL_HIGH (0x00000000) -#define IOAPIC_REDTBL_INTPOL_LOW (0x00002000) -#define IOAPIC_REDTBL_IRR (0x00004000) -#define IOAPIC_REDTBL_TRIGGER_EDGE (0x00000000) -#define IOAPIC_REDTBL_TRIGGER_LEVEL (0x00008000) -#define IOAPIC_REDTBL_MASK (0x00010000) +#define IOAPIC_EOI_REG_ADDR 0xFEC00040 +#define IOAPIC_EOI_REG REG32(IOAPIC_EOI_REG_ADDR) + +#define IOAPIC_VERSION (0x1) +#define IOAPIC_IOREDTBL (0x10) +#define IOAPIC_REDTBL_DELMOD_FIXED (0x00000000) +#define IOAPIC_REDTBL_DESTMOD_PHYS (0x00000000) +#define IOAPIC_REDTBL_INTPOL_HIGH (0x00000000) +#define IOAPIC_REDTBL_INTPOL_LOW (0x00002000) +#define IOAPIC_REDTBL_IRR (0x00004000) +#define IOAPIC_REDTBL_TRIGGER_EDGE (0x00000000) +#define IOAPIC_REDTBL_TRIGGER_LEVEL (0x00008000) +#define IOAPIC_REDTBL_MASK (0x00010000) /* WDT (Watchdog Timer) Registers */ -#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0) -#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4) -#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8) -#define WDT_CONTROL_ENABLE_BIT BIT(17) +#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0) +#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4) +#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8) +#define WDT_CONTROL_ENABLE_BIT BIT(17) /* LAPIC registers */ /* Bare address needed for assembler (ISH_LAPIC_BASE + 0xB0) */ -#define LAPIC_EOI_REG_ADDR 0xFEE000B0 -#define LAPIC_EOI_REG REG32(LAPIC_EOI_REG_ADDR) -#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x100) -#define LAPIC_ISR_LAST_REG REG32(ISH_LAPIC_BASE + 0x170) -#define LAPIC_IRR_REG REG32(ISH_LAPIC_BASE + 0x200) -#define LAPIC_ESR_REG REG32(ISH_LAPIC_BASE + 0x280) -#define LAPIC_ERR_RECV_ILLEGAL BIT(6) -#define LAPIC_ICR_REG REG32(ISH_LAPIC_BASE + 0x300) +#define LAPIC_EOI_REG_ADDR 0xFEE000B0 +#define LAPIC_EOI_REG REG32(LAPIC_EOI_REG_ADDR) +#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x100) +#define LAPIC_ISR_LAST_REG REG32(ISH_LAPIC_BASE + 0x170) +#define LAPIC_IRR_REG REG32(ISH_LAPIC_BASE + 0x200) +#define LAPIC_ESR_REG REG32(ISH_LAPIC_BASE + 0x280) +#define LAPIC_ERR_RECV_ILLEGAL BIT(6) +#define LAPIC_ICR_REG REG32(ISH_LAPIC_BASE + 0x300) /* SRAM control registers */ #ifndef CHIP_VARIANT_ISH5P4 -#define ISH_SRAM_CTRL_BASE 0x00500000 +#define ISH_SRAM_CTRL_BASE 0x00500000 #else -#define ISH_SRAM_CTRL_BASE 0x10500000 +#define ISH_SRAM_CTRL_BASE 0x10500000 #endif -#define ISH_SRAM_CTRL_CSFGR REG32(ISH_SRAM_CTRL_BASE + 0x00) -#define ISH_SRAM_CTRL_INTR REG32(ISH_SRAM_CTRL_BASE + 0x04) -#define ISH_SRAM_CTRL_INTR_MASK REG32(ISH_SRAM_CTRL_BASE + 0x08) -#define ISH_SRAM_CTRL_ERASE_CTRL REG32(ISH_SRAM_CTRL_BASE + 0x0c) -#define ISH_SRAM_CTRL_ERASE_ADDR REG32(ISH_SRAM_CTRL_BASE + 0x10) -#define ISH_SRAM_CTRL_BANK_STATUS REG32(ISH_SRAM_CTRL_BASE + 0x2c) +#define ISH_SRAM_CTRL_CSFGR REG32(ISH_SRAM_CTRL_BASE + 0x00) +#define ISH_SRAM_CTRL_INTR REG32(ISH_SRAM_CTRL_BASE + 0x04) +#define ISH_SRAM_CTRL_INTR_MASK REG32(ISH_SRAM_CTRL_BASE + 0x08) +#define ISH_SRAM_CTRL_ERASE_CTRL REG32(ISH_SRAM_CTRL_BASE + 0x0c) +#define ISH_SRAM_CTRL_ERASE_ADDR REG32(ISH_SRAM_CTRL_BASE + 0x10) +#define ISH_SRAM_CTRL_BANK_STATUS REG32(ISH_SRAM_CTRL_BASE + 0x2c) #endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/ish/system.c b/chip/ish/system.c index 30a2576e5e..22af124cd9 100644 --- a/chip/ish/system.c +++ b/chip/ish/system.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,8 +23,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) int system_is_reboot_warm(void) { @@ -57,8 +57,7 @@ uint32_t chip_read_reset_flags(void) * Used when the watchdog timer exceeds max retries and we want to * disable ISH completely. */ -noreturn -static void system_halt(void) +noreturn static void system_halt(void) { cflush(); @@ -66,9 +65,8 @@ static void system_halt(void) disable_all_interrupts(); WDT_CONTROL = 0; CCU_TCG_EN = 1; - __asm__ volatile ( - "cli\n" - "hlt\n"); + __asm__ volatile("cli\n" + "hlt\n"); } } @@ -90,8 +88,8 @@ void system_reset(int flags) if (flags & SYSTEM_RESET_AP_WATCHDOG) { save_flags |= EC_RESET_FLAG_WATCHDOG; ish_persistent_data.watchdog_counter += 1; - if (ish_persistent_data.watchdog_counter - >= CONFIG_WATCHDOG_MAX_RETRIES) { + if (ish_persistent_data.watchdog_counter >= + CONFIG_WATCHDOG_MAX_RETRIES) { CPRINTS("Halting ISH due to max watchdog resets"); system_halt(); } @@ -175,19 +173,13 @@ void system_set_image_copy(enum ec_image copy) { } -#define HBW_FABRIC_BASE 0x10000000 -#define PER0_FABRIC_BASE 0x04000000 -#define AGENT_STS 0x28 -#define ERROR_LOG 0x58 +#define HBW_FABRIC_BASE 0x10000000 +#define PER0_FABRIC_BASE 0x04000000 +#define AGENT_STS 0x28 +#define ERROR_LOG 0x58 -static uint16_t hbw_ia_offset[] = { - 0x1000, - 0x3400, - 0x3800, - 0x5000, - 0x5800, - 0x6000 -}; +static uint16_t hbw_ia_offset[] = { 0x1000, 0x3400, 0x3800, + 0x5000, 0x5800, 0x6000 }; static inline void clear_register(uint32_t reg) { diff --git a/chip/ish/system_state.h b/chip/ish/system_state.h index 20de1aaf4b..bcffcf49ee 100644 --- a/chip/ish/system_state.h +++ b/chip/ish/system_state.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,7 +6,7 @@ #ifndef __SYSTEM_STATE_H #define __SYSTEM_STATE_H -#define HECI_FIXED_SYSTEM_STATE_ADDR 13 +#define HECI_FIXED_SYSTEM_STATE_ADDR 13 struct ss_subsys_device; diff --git a/chip/ish/system_state_subsys.c b/chip/ish/system_state_subsys.c index 36b79c747a..bfc120ff9b 100644 --- a/chip/ish/system_state_subsys.c +++ b/chip/ish/system_state_subsys.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,24 +10,23 @@ #ifdef SS_SUBSYSTEM_DEBUG #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) #else #define CPUTS(outstr) #define CPRINTS(format, args...) #define CPRINTF(format, args...) #endif - /* the following "define"s and structures are from host driver * and they are slightly modified for look&feel purpose. */ -#define SYSTEM_STATE_SUBSCRIBE 0x1 -#define SYSTEM_STATE_STATUS 0x2 -#define SYSTEM_STATE_QUERY_SUBSCRIBERS 0x3 -#define SYSTEM_STATE_STATE_CHANGE_REQ 0x4 +#define SYSTEM_STATE_SUBSCRIBE 0x1 +#define SYSTEM_STATE_STATUS 0x2 +#define SYSTEM_STATE_QUERY_SUBSCRIBERS 0x3 +#define SYSTEM_STATE_STATE_CHANGE_REQ 0x4 -#define SUSPEND_STATE_BIT BIT(1) /* suspend/resume */ +#define SUSPEND_STATE_BIT BIT(1) /* suspend/resume */ /* Cached state of ISH's requested power rails when AP suspends */ static uint32_t cached_vnn_request; @@ -67,7 +66,7 @@ struct ss_state_change_req { * "struct ss_subsys_device" in it and calls ss_subsys_register_client() like * HECI client. */ -#define MAX_SS_CLIENTS HECI_MAX_NUM_OF_CLIENTS +#define MAX_SS_CLIENTS HECI_MAX_NUM_OF_CLIENTS struct ss_subsystem_context { uint32_t registered_state; @@ -103,7 +102,7 @@ static int ss_subsys_suspend(void) for (i = ss_subsys_ctx.num_of_ss_client - 1; i >= 0; i--) { if (ss_subsys_ctx.clients[i]->cbs->suspend) ss_subsys_ctx.clients[i]->cbs->suspend( - ss_subsys_ctx.clients[i]); + ss_subsys_ctx.clients[i]); } /* @@ -126,8 +125,7 @@ static int ss_subsys_resume(void) /* * Restore VNN power request from before suspend. */ - if (IS_ENABLED(CHIP_FAMILY_ISH5) && - cached_vnn_request) { + if (IS_ENABLED(CHIP_FAMILY_ISH5) && cached_vnn_request) { /* Request all cached power rails that are not already on. */ PMU_VNN_REQ = cached_vnn_request & ~PMU_VNN_REQ; /* Wait for power request to get acknowledged */ @@ -138,7 +136,7 @@ static int ss_subsys_resume(void) for (i = 0; i < ss_subsys_ctx.num_of_ss_client; i++) { if (ss_subsys_ctx.clients[i]->cbs->resume) ss_subsys_ctx.clients[i]->cbs->resume( - ss_subsys_ctx.clients[i]); + ss_subsys_ctx.clients[i]); } return EC_SUCCESS; diff --git a/chip/ish/uart.c b/chip/ish/uart.c index 71d8a41397..b1c9493869 100644 --- a/chip/ish/uart.c +++ b/chip/ish/uart.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,20 +17,14 @@ #include "system.h" #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) static const uint32_t baud_conf[][BAUD_TABLE_MAX] = { - {B9600, 9600}, - {B57600, 57600}, - {B115200, 115200}, - {B921600, 921600}, - {B2000000, 2000000}, - {B3000000, 3000000}, - {B3250000, 3250000}, - {B3500000, 3500000}, - {B4000000, 4000000}, - {B19200, 19200}, + { B9600, 9600 }, { B57600, 57600 }, { B115200, 115200 }, + { B921600, 921600 }, { B2000000, 2000000 }, { B3000000, 3000000 }, + { B3250000, 3250000 }, { B3500000, 3500000 }, { B4000000, 4000000 }, + { B19200, 19200 }, }; static struct uart_ctx uart_ctx[UART_DEVICES] = { @@ -146,7 +140,7 @@ static int uart_return_baud_rate_by_id(int baud_rate_id) static void uart_hw_init(enum UART_PORT id) { - uint32_t divisor; /* baud rate divisor */ + uint32_t divisor; /* baud rate divisor */ uint8_t mcr = 0; uint8_t fcr = 0; struct uart_ctx *ctx = &uart_ctx[id]; @@ -156,7 +150,8 @@ static void uart_hw_init(enum UART_PORT id) divisor = (ctx->input_freq / ctx->baud_rate) >> 4; if (IS_ENABLED(CONFIG_ISH_DW_UART)) { /* calculate the fractional part */ - fraction = ceil_for(ctx->input_freq, ctx->baud_rate) - (divisor << 4); + fraction = ceil_for(ctx->input_freq, ctx->baud_rate) - + (divisor << 4); } else { MUL(ctx->id) = (divisor * ctx->baud_rate); DIV(ctx->id) = (ctx->input_freq / 16); @@ -189,8 +184,7 @@ static void uart_hw_init(enum UART_PORT id) fcr = FCR_FIFO_SIZE_64 | FCR_ITL_FIFO_64_BYTES_1; /* configure FIFOs */ - FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE - | FCR_RESET_RX | FCR_RESET_TX); + FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE | FCR_RESET_RX | FCR_RESET_TX); if (!IS_ENABLED(CONFIG_ISH_DW_UART)) /* enable UART unit */ @@ -229,8 +223,8 @@ static void uart_stop_hw(enum UART_PORT id) if (!IS_ENABLED(CONFIG_ISH_DW_UART)) { /* Manually clearing the fifo from possible noise. - * Entering D0i3 when fifo is not cleared may result in a hang. - */ + * Entering D0i3 when fifo is not cleared may result in a hang. + */ fifo_len = (FOR(id) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS; for (i = 0; i < fifo_len; i++) @@ -280,10 +274,10 @@ static void uart_drv_init(void) if (!IS_ENABLED(CONFIG_ISH_DW_UART)) /* Enable HSU global interrupts (DMA/U0/U1) and set PMEN bit - * to allow PMU to clock gate ISH - */ - HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN - | GIEN_UART1_EN | GIEN_PWR_MGMT); + * to allow PMU to clock gate ISH + */ + HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN | GIEN_UART1_EN | + GIEN_PWR_MGMT); task_enable_irq(ISH_DEBUG_UART_IRQ); } diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h index 5bfc7b9a6b..1fc36b7adc 100644 --- a/chip/ish/uart_defs.h +++ b/chip/ish/uart_defs.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,344 +12,331 @@ #include <stddef.h> #include "atomic.h" -#define UART_ERROR -1 -#define UART_BUSY -2 +#define UART_ERROR -1 +#define UART_BUSY -2 #ifdef CHIP_VARIANT_ISH5P4 -#define UART0_OFFS (0x00) -#define UART1_OFFS (0x2000) -#define UART2_OFFS (0x4000) +#define UART0_OFFS (0x00) +#define UART1_OFFS (0x2000) +#define UART2_OFFS (0x4000) #else -#define UART0_OFFS (0x80) -#define UART1_OFFS (0x100) -#define UART2_OFFS (0x180) +#define UART0_OFFS (0x80) +#define UART1_OFFS (0x100) +#define UART2_OFFS (0x180) #endif -#define HSU_BASE ISH_UART_BASE -#define UART0_BASE (ISH_UART_BASE + UART0_OFFS) -#define UART1_BASE (ISH_UART_BASE + UART1_OFFS) -#define UART2_BASE (ISH_UART_BASE + UART2_OFFS) +#define HSU_BASE ISH_UART_BASE +#define UART0_BASE (ISH_UART_BASE + UART0_OFFS) +#define UART1_BASE (ISH_UART_BASE + UART1_OFFS) +#define UART2_BASE (ISH_UART_BASE + UART2_OFFS) -#define UART_REG(size, name, n) \ - REG##size(uart_ctx[n].base + \ +#define UART_REG(size, name, n) \ + REG##size(uart_ctx[n].base + \ UART_OFFSET_##name * uart_ctx[n].addr_interval) /* Register accesses */ -#define LSR(n) UART_REG(8, LSR, n) -#define THR(n) UART_REG(8, THR, n) -#define RBR(n) UART_REG(8, RBR, n) -#define DLL(n) UART_REG(8, DLL, n) -#define DLH(n) UART_REG(8, DLH, n) -#define IER(n) UART_REG(8, IER, n) -#define IIR(n) UART_REG(8, IIR, n) -#define FCR(n) UART_REG(8, FCR, n) -#define LCR(n) UART_REG(8, LCR, n) -#define MCR(n) UART_REG(8, MCR, n) -#define MSR(n) UART_REG(8, MSR, n) -#define DLF(n) UART_REG(8, DLF, n) -#define FOR(n) UART_REG(32, FOR, n) -#define ABR(n) UART_REG(32, ABR, n) -#define PS(n) UART_REG(32, PS, n) -#define MUL(n) UART_REG(32, MUL, n) -#define DIV(n) UART_REG(32, DIV, n) +#define LSR(n) UART_REG(8, LSR, n) +#define THR(n) UART_REG(8, THR, n) +#define RBR(n) UART_REG(8, RBR, n) +#define DLL(n) UART_REG(8, DLL, n) +#define DLH(n) UART_REG(8, DLH, n) +#define IER(n) UART_REG(8, IER, n) +#define IIR(n) UART_REG(8, IIR, n) +#define FCR(n) UART_REG(8, FCR, n) +#define LCR(n) UART_REG(8, LCR, n) +#define MCR(n) UART_REG(8, MCR, n) +#define MSR(n) UART_REG(8, MSR, n) +#define DLF(n) UART_REG(8, DLF, n) +#define FOR(n) UART_REG(32, FOR, n) +#define ABR(n) UART_REG(32, ABR, n) +#define PS(n) UART_REG(32, PS, n) +#define MUL(n) UART_REG(32, MUL, n) +#define DIV(n) UART_REG(32, DIV, n) #ifdef CONFIG_ISH_DW_UART /* * RBR: Receive Buffer register (BLAB bit = 0) */ -#define UART_OFFSET_RBR (0x00) +#define UART_OFFSET_RBR (0x00) /* * THR: Transmit Holding register (BLAB bit = 0) */ -#define UART_OFFSET_THR (0x00) +#define UART_OFFSET_THR (0x00) /* * DLL: Divisor Latch Reg. low byte (BLAB bit = 1) * baud rate = (serial clock freq) / (16 * divisor) */ -#define UART_OFFSET_DLL (0x00) +#define UART_OFFSET_DLL (0x00) /* * DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */ -#define UART_OFFSET_DLH (0x04) +#define UART_OFFSET_DLH (0x04) /* * IER: Interrupt Enable register (BLAB bit = 0) */ -#define UART_OFFSET_IER (0x04) +#define UART_OFFSET_IER (0x04) -#define IER_RECV (0x01) /* Receive Data Available */ -#define IER_TDRQ (0x02) /* Transmit Holding Register Empty */ -#define IER_LINE_STAT (0x04) /* Receiver Line Status */ -#define IER_MODEM (0x08) /* Modem Status */ -#define IER_PTIME (0x80) /* Programmable THRE Interrupt Mode Enable */ +#define IER_RECV (0x01) /* Receive Data Available */ +#define IER_TDRQ (0x02) /* Transmit Holding Register Empty */ +#define IER_LINE_STAT (0x04) /* Receiver Line Status */ +#define IER_MODEM (0x08) /* Modem Status */ +#define IER_PTIME (0x80) /* Programmable THRE Interrupt Mode Enable */ /* * IIR: Interrupt ID register */ -#define UART_OFFSET_IIR (0x08) - -#define IIR_MODEM (0x00) /* Prio: 4 */ -#define IIR_NO_INTR (0x01) -#define IIR_THRE (0x02) /* Prio: 3 */ -#define IIR_RECV_DATA (0x04) /* Prio: 2 */ -#define IIR_LINE_STAT (0x06) /* Prio: 1 */ -#define IIR_BUSY (0x07) /* Prio: 5 */ -#define IIR_TIME_OUT (0x0C) /* Prio: 2 */ -#define IIR_SOURCE (0x0F) +#define UART_OFFSET_IIR (0x08) +#define IIR_MODEM (0x00) /* Prio: 4 */ +#define IIR_NO_INTR (0x01) +#define IIR_THRE (0x02) /* Prio: 3 */ +#define IIR_RECV_DATA (0x04) /* Prio: 2 */ +#define IIR_LINE_STAT (0x06) /* Prio: 1 */ +#define IIR_BUSY (0x07) /* Prio: 5 */ +#define IIR_TIME_OUT (0x0C) /* Prio: 2 */ +#define IIR_SOURCE (0x0F) /* * FCR: FIFO Control register (FIFO_MODE != NONE) */ -#define UART_OFFSET_FCR (0x08) +#define UART_OFFSET_FCR (0x08) -#define FIFO_SIZE 64 -#define FCR_FIFO_ENABLE (0x01) -#define FCR_RESET_RX (0x02) -#define FCR_RESET_TX (0x04) -#define FCR_DMA_MODE (0x08) +#define FIFO_SIZE 64 +#define FCR_FIFO_ENABLE (0x01) +#define FCR_RESET_RX (0x02) +#define FCR_RESET_TX (0x04) +#define FCR_DMA_MODE (0x08) /* * LCR: Line Control register */ -#define UART_OFFSET_LCR (0x0c) +#define UART_OFFSET_LCR (0x0c) -#define LCR_5BIT_CHR (0x00) -#define LCR_6BIT_CHR (0x01) -#define LCR_7BIT_CHR (0x02) -#define LCR_8BIT_CHR (0x03) -#define LCR_BIT_CHR_MASK (0x03) +#define LCR_5BIT_CHR (0x00) +#define LCR_6BIT_CHR (0x01) +#define LCR_7BIT_CHR (0x02) +#define LCR_8BIT_CHR (0x03) +#define LCR_BIT_CHR_MASK (0x03) -#define LCR_STOP BIT(2) /* 0: 1 stop bit, 1: 1.5/2 */ -#define LCR_PEN BIT(3) /* Parity Enable */ -#define LCR_EPS BIT(4) /* Even Parity Select */ -#define LCR_SP BIT(5) /* Stick Parity */ -#define LCR_BC BIT(6) /* Break Control */ -#define LCR_DLAB BIT(7) /* Divisor Latch Access */ +#define LCR_STOP BIT(2) /* 0: 1 stop bit, 1: 1.5/2 */ +#define LCR_PEN BIT(3) /* Parity Enable */ +#define LCR_EPS BIT(4) /* Even Parity Select */ +#define LCR_SP BIT(5) /* Stick Parity */ +#define LCR_BC BIT(6) /* Break Control */ +#define LCR_DLAB BIT(7) /* Divisor Latch Access */ /* * MCR: Modem Control register */ -#define UART_OFFSET_MCR (0x10) -#define MCR_DTR (0x1) /* Data terminal ready */ -#define MCR_RTS (0x2) /* Request to send */ -#define MCR_LOOP (0x10) /* LoopBack bit*/ +#define UART_OFFSET_MCR (0x10) +#define MCR_DTR (0x1) /* Data terminal ready */ +#define MCR_RTS (0x2) /* Request to send */ +#define MCR_LOOP (0x10) /* LoopBack bit*/ -#define MCR_INTR_ENABLE (0x08) /* User-designated OUT2 */ -#define MCR_AUTO_FLOW_EN (0x20) +#define MCR_INTR_ENABLE (0x08) /* User-designated OUT2 */ +#define MCR_AUTO_FLOW_EN (0x20) /* * LSR: Line Status register */ -#define UART_OFFSET_LSR (0x14) +#define UART_OFFSET_LSR (0x14) -#define LSR_DR (0x01) /* Data Ready */ -#define LSR_OE (0x02) /* Overrun error */ -#define LSR_PE (0x04) /* Parity error */ -#define LSR_FE (0x08) /* Framing error */ -#define LSR_BI (0x10) /* Breaking interrupt */ -#define LSR_TDRQ (0x20) /* Transmit Holding Register Empty */ -#define LSR_TEMT (0x40) /* Transmitter empty */ +#define LSR_DR (0x01) /* Data Ready */ +#define LSR_OE (0x02) /* Overrun error */ +#define LSR_PE (0x04) /* Parity error */ +#define LSR_FE (0x08) /* Framing error */ +#define LSR_BI (0x10) /* Breaking interrupt */ +#define LSR_TDRQ (0x20) /* Transmit Holding Register Empty */ +#define LSR_TEMT (0x40) /* Transmitter empty */ /* * MSR: Modem Status register */ -#define UART_OFFSET_MSR (0x18) +#define UART_OFFSET_MSR (0x18) -#define MSR_CTS BIT(4) /* Clear To Send signal */ +#define MSR_CTS BIT(4) /* Clear To Send signal */ /* * TFL: Transmit FIFO Level */ -#define UART_OFFSET_TFL (0x80) +#define UART_OFFSET_TFL (0x80) /* * RFL: Receive FIFO Level */ -#define UART_OFFSET_RFL (0x84) +#define UART_OFFSET_RFL (0x84) #else /* RBR: Receive Buffer register (BLAB bit = 0) */ -#define UART_OFFSET_RBR (0) +#define UART_OFFSET_RBR (0) /* THR: Transmit Holding register (BLAB bit = 0) */ -#define UART_OFFSET_THR (0) +#define UART_OFFSET_THR (0) /* IER: Interrupt Enable register (BLAB bit = 0) */ -#define UART_OFFSET_IER (1) +#define UART_OFFSET_IER (1) /* FCR: FIFO Control register */ -#define UART_OFFSET_FCR (2) -#define FCR_FIFO_ENABLE BIT(0) -#define FCR_RESET_RX BIT(1) -#define FCR_RESET_TX BIT(2) +#define UART_OFFSET_FCR (2) +#define FCR_FIFO_ENABLE BIT(0) +#define FCR_RESET_RX BIT(1) +#define FCR_RESET_TX BIT(2) /* LCR: Line Control register */ -#define UART_OFFSET_LCR (3) -#define LCR_DLAB (0x80) -#define LCR_5BIT_CHR (0x00) -#define LCR_6BIT_CHR (0x01) -#define LCR_7BIT_CHR (0x02) -#define LCR_8BIT_CHR (0x03) -#define LCR_BIT_CHR_MASK (0x03) -#define LCR_SB (0x40) /* Set Break */ +#define UART_OFFSET_LCR (3) +#define LCR_DLAB (0x80) +#define LCR_5BIT_CHR (0x00) +#define LCR_6BIT_CHR (0x01) +#define LCR_7BIT_CHR (0x02) +#define LCR_8BIT_CHR (0x03) +#define LCR_BIT_CHR_MASK (0x03) +#define LCR_SB (0x40) /* Set Break */ /* MCR: Modem Control register */ -#define UART_OFFSET_MCR (4) -#define MCR_DTR BIT(0) -#define MCR_RTS BIT(1) -#define MCR_LOO BIT(4) -#define MCR_INTR_ENABLE BIT(3) -#define MCR_AUTO_FLOW_EN BIT(5) +#define UART_OFFSET_MCR (4) +#define MCR_DTR BIT(0) +#define MCR_RTS BIT(1) +#define MCR_LOO BIT(4) +#define MCR_INTR_ENABLE BIT(3) +#define MCR_AUTO_FLOW_EN BIT(5) /* LSR: Line Status register */ -#define UART_OFFSET_LSR (5) -#define LSR_DR BIT(0) /* Data Ready */ -#define LSR_OE BIT(1) /* Overrun error */ -#define LSR_PE BIT(2) /* Parity error */ -#define LSR_FE BIT(3) /* Framing error */ -#define LSR_BI BIT(4) /* Breaking interrupt */ -#define LSR_THR_EMPTY BIT(5) /* Non FIFO mode: Transmit holding - * register empty - */ -#define LSR_TDRQ BIT(5) /* FIFO mode: Transmit Data request */ -#define LSR_TEMT BIT(6) /* Transmitter empty */ +#define UART_OFFSET_LSR (5) +#define LSR_DR BIT(0) /* Data Ready */ +#define LSR_OE BIT(1) /* Overrun error */ +#define LSR_PE BIT(2) /* Parity error */ +#define LSR_FE BIT(3) /* Framing error */ +#define LSR_BI BIT(4) /* Breaking interrupt */ +#define LSR_THR_EMPTY \ + BIT(5) /* Non FIFO mode: Transmit holding \ + * register empty \ + */ +#define LSR_TDRQ BIT(5) /* FIFO mode: Transmit Data request */ +#define LSR_TEMT BIT(6) /* Transmitter empty */ #define FCR_ITL_FIFO_64_BYTES_56 (BIT(6) | BIT(7)) -#define IER_RECV BIT(0) -#define IER_TDRQ BIT(1) -#define IER_LINE_STAT BIT(2) +#define IER_RECV BIT(0) +#define IER_TDRQ BIT(1) +#define IER_LINE_STAT BIT(2) -#define UART_OFFSET_IIR (2) +#define UART_OFFSET_IIR (2) /* MSR: Modem Status register */ -#define UART_OFFSET_MSR (6) +#define UART_OFFSET_MSR (6) /* DLL: Divisor Latch Reg. low byte (BLAB bit = 1) */ -#define UART_OFFSET_DLL (0) +#define UART_OFFSET_DLL (0) /* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */ -#define UART_OFFSET_DLH (1) +#define UART_OFFSET_DLH (1) #endif /* * DLF: Divisor Latch Fraction Register */ -#define UART_OFFSET_DLF (0xC0) +#define UART_OFFSET_DLF (0xC0) /* FOR: Fifo O Register (ISH only) */ -#define UART_OFFSET_FOR (0x20) -#define FOR_OCCUPANCY_OFFS 0 -#define FOR_OCCUPANCY_MASK 0x7F +#define UART_OFFSET_FOR (0x20) +#define FOR_OCCUPANCY_OFFS 0 +#define FOR_OCCUPANCY_MASK 0x7F /* ABR: Auto-Baud Control Register (ISH only) */ -#define UART_OFFSET_ABR (0x24) -#define ABR_UUE BIT(4) +#define UART_OFFSET_ABR (0x24) +#define ABR_UUE BIT(4) /* Pre-Scalar Register (ISH only) */ -#define UART_OFFSET_PS (0x30) +#define UART_OFFSET_PS (0x30) /* DDS registers (ISH only) */ -#define UART_OFFSET_MUL (0x34) -#define UART_OFFSET_DIV (0x38) +#define UART_OFFSET_MUL (0x34) +#define UART_OFFSET_DIV (0x38) -#define FCR_FIFO_SIZE_16 (0x00) -#define FCR_FIFO_SIZE_64 (0x20) -#define FCR_ITL_FIFO_64_BYTES_1 (0x00) +#define FCR_FIFO_SIZE_16 (0x00) +#define FCR_FIFO_SIZE_64 (0x20) +#define FCR_ITL_FIFO_64_BYTES_1 (0x00) /* tx empty trigger(TET) */ -#define FCR_TET_EMPTY (0x00) -#define FCR_TET_2CHAR (0x10) -#define FCR_TET_QTR_FULL (0x20) -#define FCR_TET_HALF_FULL (0x30) +#define FCR_TET_EMPTY (0x00) +#define FCR_TET_2CHAR (0x10) +#define FCR_TET_QTR_FULL (0x20) +#define FCR_TET_HALF_FULL (0x30) /* receive trigger(RT) */ -#define FCR_RT_1CHAR (0x00) -#define FCR_RT_QTR_FULL (0x40) -#define FCR_RT_HALF_FULL (0x80) -#define FCR_RT_2LESS_FULL (0xc0) +#define FCR_RT_1CHAR (0x00) +#define FCR_RT_QTR_FULL (0x40) +#define FCR_RT_HALF_FULL (0x80) +#define FCR_RT_2LESS_FULL (0xc0) /* G_IEN: Global Interrupt Enable (ISH only) */ -#define HSU_REG_GIEN REG32(HSU_BASE + 0x0) -#define HSU_REG_GIST REG32(HSU_BASE + 0x4) - -#define GIEN_PWR_MGMT BIT(24) -#define GIEN_DMA_EN BIT(5) -#define GIEN_UART2_EN BIT(2) -#define GIEN_UART1_EN BIT(1) -#define GIEN_UART0_EN BIT(0) -#define GIST_DMA_EN BIT(5) -#define GIST_UART2_EN BIT(2) -#define GIST_UART1_EN BIT(1) -#define GIST_UART0_EN BIT(0) -#define GIST_UARTx_EN (GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN) +#define HSU_REG_GIEN REG32(HSU_BASE + 0x0) +#define HSU_REG_GIST REG32(HSU_BASE + 0x4) + +#define GIEN_PWR_MGMT BIT(24) +#define GIEN_DMA_EN BIT(5) +#define GIEN_UART2_EN BIT(2) +#define GIEN_UART1_EN BIT(1) +#define GIEN_UART0_EN BIT(0) +#define GIST_DMA_EN BIT(5) +#define GIST_UART2_EN BIT(2) +#define GIST_UART1_EN BIT(1) +#define GIST_UART0_EN BIT(0) +#define GIST_UARTx_EN (GIST_UART0_EN | GIST_UART1_EN | GIST_UART2_EN) /* UART config flag, send to sc_io_control if the current UART line has HW * flow control lines connected. */ -#define UART_CONFIG_HW_FLOW_CONTROL BIT(0) +#define UART_CONFIG_HW_FLOW_CONTROL BIT(0) /* UART config flag for sc_io_control. If defined a sc_io_event_rx_msg is * raised only when the rx buffer is completely full. Otherwise, the event * is raised after a timeout is received on the UART line, * and all data received until now is provided. */ -#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1) +#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1) /* UART config flag for sc_io_control. If defined a sc_io_event_rx_buf_depleted * is raised when all rx buffers that were added are full. Otherwise, no * event is raised. */ -#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2) - -#define UART_INT_DEVICES 3 -#define UART_EXT_DEVICES 8 -#define UART_DEVICES UART_INT_DEVICES -#define UART_ISH_ADDR_INTERVAL 1 - -#define B9600 0x0000d -#define B57600 0x00000018 -#define B115200 0x00000011 -#define B921600 0x00000012 -#define B2000000 0x00000013 -#define B3000000 0x00000014 -#define B3250000 0x00000015 -#define B3500000 0x00000016 -#define B4000000 0x00000017 -#define B19200 0x0000e -#define B38400 0x0000f +#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2) + +#define UART_INT_DEVICES 3 +#define UART_EXT_DEVICES 8 +#define UART_DEVICES UART_INT_DEVICES +#define UART_ISH_ADDR_INTERVAL 1 + +#define B9600 0x0000d +#define B57600 0x00000018 +#define B115200 0x00000011 +#define B921600 0x00000012 +#define B2000000 0x00000013 +#define B3000000 0x00000014 +#define B3250000 0x00000015 +#define B3500000 0x00000016 +#define B4000000 0x00000017 +#define B19200 0x0000e +#define B38400 0x0000f /* KHZ, MHZ */ -#define KHZ(x) ((x) * 1000) -#define MHZ(x) (KHZ(x) * 1000) +#define KHZ(x) ((x)*1000) +#define MHZ(x) (KHZ(x) * 1000) #if defined(CHIP_VARIANT_ISH5P4) /* Change to 100MHZ in real silicon platform */ -#define UART_ISH_INPUT_FREQ MHZ(100) +#define UART_ISH_INPUT_FREQ MHZ(100) #elif defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5) -#define UART_ISH_INPUT_FREQ MHZ(120) +#define UART_ISH_INPUT_FREQ MHZ(120) #elif defined(CHIP_FAMILY_ISH4) -#define UART_ISH_INPUT_FREQ MHZ(100) +#define UART_ISH_INPUT_FREQ MHZ(100) #endif -#define UART_DEFAULT_BAUD_RATE 115200 -#define UART_STATE_CG BIT(UART_OP_CG) +#define UART_DEFAULT_BAUD_RATE 115200 +#define UART_STATE_CG BIT(UART_OP_CG) -enum UART_PORT { - UART_PORT_0, - UART_PORT_1, - UART_PORT_MAX -}; +enum UART_PORT { UART_PORT_0, UART_PORT_1, UART_PORT_MAX }; -enum UART_OP { - UART_OP_READ, - UART_OP_WRITE, - UART_OP_CG, - UART_OP_MAX -}; +enum UART_OP { UART_OP_READ, UART_OP_WRITE, UART_OP_CG, UART_OP_MAX }; -enum { - BAUD_IDX, - BAUD_SPEED, - BAUD_TABLE_MAX -}; +enum { BAUD_IDX, BAUD_SPEED, BAUD_TABLE_MAX }; struct uart_ctx { uint32_t id; diff --git a/chip/ish/util/pack_ec.py b/chip/ish/util/pack_ec.py index bd9b823cab..7f381005f0 100755 --- a/chip/ish/util/pack_ec.py +++ b/chip/ish/util/pack_ec.py @@ -1,13 +1,9 @@ #!/usr/bin/env python3 # -*- coding: utf-8 -*-" -# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Copyright 2019 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # A script to pack EC binary with manifest header according to # Based on 607297_Host_ISH_Firmware_Load_Chrome_OS_SAS_Rev0p5.pdf, @@ -28,85 +24,104 @@ MANIFEST_ENTRY_SIZE = 0x80 HEADER_SIZE = 0x1000 PAGE_SIZE = 0x1000 + def parseargs(): - parser = argparse.ArgumentParser() - parser.add_argument("-k", "--kernel", - help="EC kernel binary to pack, \ - usually ec.RW.bin or ec.RW.flat.", - required=True) - parser.add_argument("--kernel-size", type=int, - help="Size of EC kernel image", - required=True) - parser.add_argument("-a", "--aon", - help="EC aontask binary to pack, \ - usually ish_aontask.bin.", - required=False) - parser.add_argument("--aon-size", type=int, - help="Size of EC aontask image", - required=False) - parser.add_argument("-o", "--output", - help="Output flash binary file") - - return parser.parse_args() + parser = argparse.ArgumentParser() + parser.add_argument( + "-k", + "--kernel", + help="EC kernel binary to pack, usually ec.RW.bin or ec.RW.flat.", + required=True, + ) + parser.add_argument( + "--kernel-size", type=int, help="Size of EC kernel image", required=True + ) + parser.add_argument( + "-a", + "--aon", + help="EC aontask binary to pack, usually ish_aontask.bin.", + required=False, + ) + parser.add_argument( + "--aon-size", type=int, help="Size of EC aontask image", required=False + ) + parser.add_argument("-o", "--output", help="Output flash binary file") + + return parser.parse_args() + def gen_manifest(ext_id, comp_app_name, code_offset, module_size): - """Returns a binary blob that represents a manifest entry""" - m = bytearray(MANIFEST_ENTRY_SIZE) + """Returns a binary blob that represents a manifest entry""" + m = bytearray(MANIFEST_ENTRY_SIZE) - # 4 bytes of ASCII encode ID (little endian) - struct.pack_into('<4s', m, 0, ext_id) - # 8 bytes of ASCII encode ID (little endian) - struct.pack_into('<8s', m, 32, comp_app_name) - # 4 bytes of code offset (little endian) - struct.pack_into('<I', m, 96, code_offset) - # 2 bytes of module in page size increments (little endian) - struct.pack_into('<H', m, 100, module_size) + # 4 bytes of ASCII encode ID (little endian) + struct.pack_into("<4s", m, 0, ext_id) + # 8 bytes of ASCII encode ID (little endian) + struct.pack_into("<8s", m, 32, comp_app_name) + # 4 bytes of code offset (little endian) + struct.pack_into("<I", m, 96, code_offset) + # 2 bytes of module in page size increments (little endian) + struct.pack_into("<H", m, 100, module_size) + + return m - return m def roundup_page(size): - """Returns roundup-ed page size from size of bytes""" - return int(size / PAGE_SIZE) + (size % PAGE_SIZE > 0) + """Returns roundup-ed page size from size of bytes""" + return int(size / PAGE_SIZE) + (size % PAGE_SIZE > 0) + def main(): - args = parseargs() - print(" Packing EC image file for ISH") - - with open(args.output, 'wb') as f: - print(" kernel binary size:", args.kernel_size) - kern_rdup_pg_size = roundup_page(args.kernel_size) - # Add manifest for main ISH binary - f.write(gen_manifest(b'ISHM', b'ISH_KERN', HEADER_SIZE, kern_rdup_pg_size)) - - if args.aon is not None: - print(" AON binary size: ", args.aon_size) - aon_rdup_pg_size = roundup_page(args.aon_size) - # Add manifest for aontask binary - f.write(gen_manifest(b'ISHM', b'AON_TASK', - (HEADER_SIZE + kern_rdup_pg_size * PAGE_SIZE - - MANIFEST_ENTRY_SIZE), aon_rdup_pg_size)) - - # Add manifest that signals end of manifests - f.write(gen_manifest(b'ISHE', b'', 0, 0)) - - # Pad the remaining HEADER with 0s - if args.aon is not None: - f.write(b'\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3))) - else: - f.write(b'\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2))) - - # Append original kernel image - with open(args.kernel, 'rb') as in_file: - f.write(in_file.read()) - # Filling padings due to size round up as pages - f.write(b'\x00' * (kern_rdup_pg_size * PAGE_SIZE - args.kernel_size)) - - if args.aon is not None: - # Append original aon image - with open(args.aon, 'rb') as in_file: - f.write(in_file.read()) - # Filling padings due to size round up as pages - f.write(b'\x00' * (aon_rdup_pg_size * PAGE_SIZE - args.aon_size)) - -if __name__ == '__main__': - main() + args = parseargs() + print(" Packing EC image file for ISH") + + with open(args.output, "wb") as f: + print(" kernel binary size:", args.kernel_size) + kern_rdup_pg_size = roundup_page(args.kernel_size) + # Add manifest for main ISH binary + f.write( + gen_manifest(b"ISHM", b"ISH_KERN", HEADER_SIZE, kern_rdup_pg_size) + ) + + if args.aon is not None: + print(" AON binary size: ", args.aon_size) + aon_rdup_pg_size = roundup_page(args.aon_size) + # Add manifest for aontask binary + f.write( + gen_manifest( + b"ISHM", + b"AON_TASK", + ( + HEADER_SIZE + + kern_rdup_pg_size * PAGE_SIZE + - MANIFEST_ENTRY_SIZE + ), + aon_rdup_pg_size, + ) + ) + + # Add manifest that signals end of manifests + f.write(gen_manifest(b"ISHE", b"", 0, 0)) + + # Pad the remaining HEADER with 0s + if args.aon is not None: + f.write(b"\x00" * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3))) + else: + f.write(b"\x00" * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2))) + + # Append original kernel image + with open(args.kernel, "rb") as in_file: + f.write(in_file.read()) + # Filling padings due to size round up as pages + f.write(b"\x00" * (kern_rdup_pg_size * PAGE_SIZE - args.kernel_size)) + + if args.aon is not None: + # Append original aon image + with open(args.aon, "rb") as in_file: + f.write(in_file.read()) + # Filling padings due to size round up as pages + f.write(b"\x00" * (aon_rdup_pg_size * PAGE_SIZE - args.aon_size)) + + +if __name__ == "__main__": + main() diff --git a/chip/ish/watchdog.c b/chip/ish/watchdog.c index bf78f49312..7b32133619 100644 --- a/chip/ish/watchdog.c +++ b/chip/ish/watchdog.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -29,8 +29,8 @@ #include "watchdog.h" /* Units are hundreds of milliseconds */ -#define WDT_T1_PERIOD (100) /* 10 seconds */ -#define WDT_T2_PERIOD (10) /* 1 second */ +#define WDT_T1_PERIOD (100) /* 10 seconds */ +#define WDT_T2_PERIOD (10) /* 1 second */ int watchdog_init(void) { @@ -45,9 +45,8 @@ int watchdog_init(void) CCU_WDT_CD = WDT_CLOCK_HZ / 10; /* 10 Hz => 100 ms period */ /* Enable the watchdog timer and set initial T1/T2 values */ - WDT_CONTROL = WDT_CONTROL_ENABLE_BIT - | (WDT_T2_PERIOD << 8) - | WDT_T1_PERIOD; + WDT_CONTROL = WDT_CONTROL_ENABLE_BIT | (WDT_T2_PERIOD << 8) | + WDT_T1_PERIOD; task_enable_irq(ISH_WDT_IRQ); |