diff options
author | Denis Brockus <dbrockus@chromium.org> | 2019-06-14 09:35:34 -0600 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2019-06-17 03:21:12 +0000 |
commit | 470a9586fd8d897a847e52a65debc00001c1d565 (patch) | |
tree | baf15ed7dc48d0cb993b60946e5f758c00aa01e3 /chip/ish | |
parent | 70e9e80590d05bad7dbd44fc4d2613633e7b98eb (diff) | |
download | chrome-ec-470a9586fd8d897a847e52a65debc00001c1d565.tar.gz |
ish: remove conditional compilation where possible
Removed many of the #if conditions and replaced them with IS_ENABLED
BUG=b:132178013
BRANCH=none
TEST=make buildall -j
TEST=verify basic ish ec functionality
Change-Id: I39c1d2dfdb39baa06e53746789d0b6a648275ed9
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660021
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Diffstat (limited to 'chip/ish')
-rw-r--r-- | chip/ish/aontaskfw/ish_aontask.c | 5 | ||||
-rw-r--r-- | chip/ish/clock.c | 4 | ||||
-rw-r--r-- | chip/ish/gpio.c | 5 | ||||
-rw-r--r-- | chip/ish/i2c.c | 16 | ||||
-rw-r--r-- | chip/ish/ipc_heci.c | 26 | ||||
-rw-r--r-- | chip/ish/power_mgt.c | 4 | ||||
-rw-r--r-- | chip/ish/system_state_subsys.c | 15 |
7 files changed, 31 insertions, 44 deletions
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c index d25f2a5f4d..996827e8c9 100644 --- a/chip/ish/aontaskfw/ish_aontask.c +++ b/chip/ish/aontaskfw/ish_aontask.c @@ -93,8 +93,6 @@ static void pmu_wakeup_isr(void) __builtin_unreachable(); } -#ifdef CONFIG_ISH_PM_RESET_PREP - /* ISR for reset prep interrupt */ static void reset_prep_isr(void) { @@ -113,9 +111,6 @@ static void reset_prep_isr(void) __builtin_unreachable(); } -#endif - - /** * Use a static data array for aon IDT, and setting IDT header for IDTR * register diff --git a/chip/ish/clock.c b/chip/ish/clock.c index 7e0879cc0a..ac818f5733 100644 --- a/chip/ish/clock.c +++ b/chip/ish/clock.c @@ -20,8 +20,6 @@ void clock_init(void) /* No initialization for clock on ISH */ } -#ifdef CONFIG_LOW_POWER_IDLE - void clock_refresh_console_in_use(void) { /** @@ -32,5 +30,3 @@ void clock_refresh_console_in_use(void) */ ish_pm_refresh_console_in_use(); } - -#endif diff --git a/chip/ish/gpio.c b/chip/ish/gpio.c index 18890c111d..3d374f3cb8 100644 --- a/chip/ish/gpio.c +++ b/chip/ish/gpio.c @@ -55,13 +55,12 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) } /* ISH 3 can't support both rising and falling edge */ -#ifdef CHIP_FAMILY_ISH3 - if ((flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) { + if (IS_ENABLED(CHIP_FAMILY_ISH3) && + (flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) { ccprintf("\n\nISH 2/3 does not support both rising & falling " "edge for %d 0x%02x\n\n", port, mask); } -#endif /* GPSR/GPCR Output high/low */ if (flags & GPIO_HIGH) /* Output high */ diff --git a/chip/ish/i2c.c b/chip/ish/i2c.c index cecb81f40f..0cb445cea0 100644 --- a/chip/ish/i2c.c +++ b/chip/ish/i2c.c @@ -427,17 +427,21 @@ int chip_i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_size, static void i2c_interrupt_handler(struct i2c_context *ctx) { -#ifdef INTR_DEBUG uint32_t raw_intr; - raw_intr = 0x0000FFFF & i2c_mmio_read(ctx->base, IC_RAW_INTR_STAT); -#endif + + if (IS_ENABLED(INTR_DEBUG)) + raw_intr = 0x0000FFFF & i2c_mmio_read(ctx->base, + IC_RAW_INTR_STAT); + /* check interrupts */ ctx->interrupts = i2c_mmio_read(ctx->base, IC_INTR_STAT); ctx->reason = (uint16_t) i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE); -#ifdef INTR_DEBUG - CPRINTS("INTR_STAT = 0x%04x, TX_ABORT_SRC = 0x%04x, RAW_INTR_STAT = 0x%04x\n", + + if (IS_ENABLED(INTR_DEBUG)) + CPRINTS("INTR_STAT = 0x%04x, TX_ABORT_SRC = 0x%04x, " + "RAW_INTR_STAT = 0x%04x\n", ctx->interrupts, ctx->reason, raw_intr); -#endif + /* disable interrupts */ i2c_intr_switch(ctx->base, DISABLE_INT); task_set_event(ctx->wait_task_id, TASK_EVENT_I2C_IDLE, 0); diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c index 394c768e28..1eb3e7da4d 100644 --- a/chip/ish/ipc_heci.c +++ b/chip/ish/ipc_heci.c @@ -323,10 +323,11 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx, CPRINTS("buffer is smaller than payload\n"); return -IPC_ERR_TOO_SMALL_BUFFER; } -#ifdef IPC_HECI_DEBUG - CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n", protocol, drbl_val, - IPC_DB_MSG_LENGTH(drbl_val)); -#endif + + if (IS_ENABLED(IPC_HECI_DEBUG)) + CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n", + protocol, drbl_val, + IPC_DB_MSG_LENGTH(drbl_val)); switch (protocol) { case IPC_PROTOCOL_HECI: @@ -446,7 +447,6 @@ static void ipc_host2ish_isr(void) uint32_t pisr = IPC_PISR; uint32_t pimr = IPC_PIMR; -#ifdef CHIP_FAMILY_ISH5 /* * TODO(b/122364080): Remove this code once proper power management is * in place for ISH. @@ -456,9 +456,8 @@ static void ipc_host2ish_isr(void) * host ipc communication). Resume is where we would like to restore all * power settings, but that is too late for this power request. */ - - PMU_VNN_REQ = VNN_REQ_IPC_HOST_WRITE & ~PMU_VNN_REQ; -#endif + if (IS_ENABLED(CHIP_FAMILY_ISH5)) + PMU_VNN_REQ = VNN_REQ_IPC_HOST_WRITE & ~PMU_VNN_REQ; if ((pisr & IPC_PISR_HOST2ISH_BIT) && (pimr & IPC_PIMR_HOST2ISH_BIT)) handle_msg_recv_interrupt(IPC_PEER_ID_HOST); @@ -687,17 +686,18 @@ void ipc_mng_task(void) struct ipc_msg msg; ipc_handle_t handle; -#ifdef CHIP_FAMILY_ISH5 /* * TODO(b/122364080): Remove this code once proper power management is * in place for ISH. * * Ensure that power for host IPCs is requested and ack'ed */ - PMU_VNN_REQ = VNN_REQ_IPC_HOST_WRITE & ~PMU_VNN_REQ; - while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS)) - continue; -#endif + if (IS_ENABLED(CHIP_FAMILY_ISH5)) { + PMU_VNN_REQ = VNN_REQ_IPC_HOST_WRITE & ~PMU_VNN_REQ; + while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS)) + continue; + } + handle = ipc_open(IPC_PEER_ID_HOST, IPC_PROTOCOL_MNG, EVENT_FLAG_BIT_MNG_MSG); diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c index 7d4e901a13..dea5b4cf1c 100644 --- a/chip/ish/power_mgt.c +++ b/chip/ish/power_mgt.c @@ -711,25 +711,21 @@ static void handle_d3(uint32_t irq_vec) } } -__maybe_unused static void d3_rise_isr(void) { handle_d3(ISH_D3_RISE_VEC); } -__maybe_unused static void d3_fall_isr(void) { handle_d3(ISH_D3_FALL_VEC); } -__maybe_unused static void bme_rise_isr(void) { handle_d3(ISH_BME_RISE_VEC); } -__maybe_unused static void bme_fall_isr(void) { handle_d3(ISH_BME_FALL_VEC); diff --git a/chip/ish/system_state_subsys.c b/chip/ish/system_state_subsys.c index 5a0fe582b5..93539d2ddf 100644 --- a/chip/ish/system_state_subsys.c +++ b/chip/ish/system_state_subsys.c @@ -30,9 +30,7 @@ #define SUSPEND_STATE_BIT BIT(1) /* suspend/resume */ /* Cached state of ISH's requested power rails when AP suspends */ -#ifdef CHIP_FAMILY_ISH5 static uint32_t cached_vnn_request; -#endif struct ss_header { uint32_t cmd; @@ -108,7 +106,6 @@ static int ss_subsys_suspend(void) ss_subsys_ctx.clients[i]); } -#ifdef CHIP_FAMILY_ISH5 /* * TODO(b/122364080): Remove this code once proper power management is * in place for ISH. @@ -118,9 +115,10 @@ static int ss_subsys_suspend(void) * rails. Setting a bit to 1 both sets and clears a requested value. * Cache the value of request power so we can restore it on resume. */ - cached_vnn_request = PMU_VNN_REQ; - PMU_VNN_REQ = cached_vnn_request; -#endif + if (IS_ENABLED(CHIP_FAMILY_ISH5)) { + cached_vnn_request = PMU_VNN_REQ; + PMU_VNN_REQ = cached_vnn_request; + } return EC_SUCCESS; } @@ -128,21 +126,20 @@ static int ss_subsys_resume(void) { int i; -#ifdef CHIP_FAMILY_ISH5 /* * TODO(b/122364080): Remove this code once proper power management is * in place for ISH. * * Restore VNN power request from before suspend. */ - if (cached_vnn_request) { + if (IS_ENABLED(CHIP_FAMILY_ISH5) && + cached_vnn_request) { /* Request all cached power rails that are not already on. */ PMU_VNN_REQ = cached_vnn_request & ~PMU_VNN_REQ; /* Wait for power request to get acknowledged */ while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS)) continue; } -#endif for (i = 0; i < ss_subsys_ctx.num_of_ss_client; i++) { if (ss_subsys_ctx.clients[i]->cbs->resume) |