drop unnecessary boards, chips and cts tests

The only board which would be built from this branch is Cr50. bds,
fizz and host boards are necessary for proper make infrastructure
operation and tests.

lm4 and npcx are chips used by the bds and fizz boards, so they are
also kept around.

BRANCH=cr50, cr50-mp
BUG=b:145912698
TEST='make buildall -j' succeeds

Change-Id: I937b2b8642c1fe91578fc9615438ae22c165b20f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986942
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>

37 files changed, 0 insertions, 8319 deletions

diff --git a/chip/ish/aontaskfw/ish_aon_share.h b/chip/ish/aontaskfw/ish_aon_share.h
deleted file mode 100644
index e804bd72e8..0000000000
--- a/chip/ish/aontaskfw/ish_aon_share.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ISH_AON_SHARE_H
-#define __CROS_EC_ISH_AON_SHARE_H
-
-#include "common.h"
-#include "ia_structs.h"
-#include "power_mgt.h"
-
-/* magic ID for valid aontask image sanity check */
-#define AON_MAGIC_ID			        0x544E4F41  /*"AONT"*/
-
-/* aontask error code  */
-#define AON_SUCCESS				0
-#define AON_ERROR_NOT_SUPPORT_POWER_MODE	1
-#define AON_ERROR_DMA_FAILED			2
-
-
-/* shared data structure between main FW and aontask */
-struct ish_aon_share {
-	/* magic ID */
-	uint32_t magic_id;
-	/* error counter */
-	uint32_t error_count;
-	/* last error */
-	int last_error;
-	/* aontask's TSS segment entry */
-	struct tss_entry *aon_tss;
-	/* aontask's LDT start address */
-	ldt_entry *aon_ldt;
-	/* aontask's LDT's limit size */
-	uint32_t aon_ldt_size;
-	/* current power state, see chip/ish/power_mgt.h */
-	enum ish_pm_state pm_state;
-	/* for store/restore main FW's IDT */
-	struct idt_header main_fw_idt_hdr;
-
-	/**
-	 * main FW's read only code and data region in main SRAM,
-	 * address need 64 bytes align due to DMA requirement
-	 */
-	uint32_t main_fw_ro_addr;
-	uint32_t main_fw_ro_size;
-
-	/**
-	 * main FW's read and write data region in main SRAM,
-	 * address need 64 bytes align due to DMA requirement
-	 */
-	uint32_t main_fw_rw_addr;
-	uint32_t main_fw_rw_size;
-} __packed;
-
-#endif /* __CROS_EC_ISH_AON_SHARE_H */
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c
deleted file mode 100644
index 183c61f97a..0000000000
--- a/chip/ish/aontaskfw/ish_aontask.c
+++ /dev/null
@@ -1,708 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * ISH aontask is a seprated very small program from main FW, not like main FW
- * resides in main SRAM, aontask resides in a small AON memory (ISH3 has no
- * seprated AON memory, reserved last 4KB of main SRAM for AON use, from ISH4,
- * there is seprated AON memory, 4KB for ISH4, and 8KB for ISH5).
- *
- * When ISH entered into low power states, aontask may get switched and run,
- * aontask managments the main SRAM and is responsible for store and restore
- * main FW's running context, for example, when entering D0i2 state, put main
- * SRAM into retention mode, when exit D0i2 state and before switch back to
- * main FW, put main SRAM into normal access mode, when entering D0i3 state,
- * at first stores main FW's writeable data into IMR DDR (read only code and
- * data already have copies in IMR), then power off the main SRAM completely,
- * when exit D0i3 state, at first power on the main SRAM, and restore main FW's
- * code and data from IMR to main SRAM, then switch back to main FW.
- *
- * On ISH, except the hpet timer, also have other wakeup sources, peripheral
- * events, such as gpio interrupt, uart interrupt, ipc interrupt, I2C and SPI
- * access are also can wakeup ISH. ISH's PMU (power management unit HW) will
- * manage these wakeup sources and transfer to a PMU wakeup interrupt which
- * can wakeup aontask, and aontask will handle it, when aontask got up, and
- * swiched back to main FW, main FW will receive the original wakeup source
- * interrupt which triggered the PMU wakeup interrupt in aontask, then main FW
- * handle the original interrupt normally.
- *
- * In most of the time, aontask is in halt state, and waiting for PMU wakeup
- * interrupt to wakeup (reset prep interrupt also can wakeup aontask
- * if CONFIG_ISH_PM_RESET_PREP defined), after wakeup, aontask will handle the
- * low power states exit process and finaly switch back to main FW.
- *
- * aontask is running in the 32bit protection mode with flat memory segment
- * settings, paging and cache are disabled (cache will be power gated).
- *
- * We use x86's hardware context switching mechanism for the switching of
- * main FW and aontask.
- * see	https://wiki.osdev.org/Context_Switching
- *      https://en.wikipedia.org/wiki/Task_state_segment
- *
- */
-
-#include "common.h"
-#include "ia_structs.h"
-#include "ish_aon_share.h"
-#include "ish_dma.h"
-#include "power_mgt.h"
-
-/**
- * ISH aontask only need handle PMU wakeup interrupt and reset prep interrupt
- * (if CONFIG_ISH_PM_RESET_PREP defined), before switch to aontask, all other
- * interrupts should be masked. Since aontask is a seprated program from
- * main FW, and the main SRAM will be power offed or will be put in in
- * retention mode, aontask need its own IDT to handle PMU wakeup interrupt and
- * reset prep interrupt (if CONFIG_ISH_PM_RESET_PREP defined)
- *
- * Due to very limit AON memory size (typically total 4KB), we don't want to
- * define and allocate whole 256 entries for aontask'IDT, that almost need 2KB
- * (256 * 8), so we just defined the only needed IDT entries:
- * AON_IDT_ENTRY_VEC_FIRST ~  AON_IDT_ENTRY_VEC_LAST
- */
-#define AON_IDT_ENTRY_VEC_FIRST        ISH_PMU_WAKEUP_VEC
-
-#ifdef CONFIG_ISH_PM_RESET_PREP
-/**
- * assume reset prep interrupt vector is greater than PMU wakeup interrupt
- * vector, and also need handle reset prep interrupt
- * (if CONFIG_ISH_PM_RESET_PREP defined)
- */
-#define AON_IDT_ENTRY_VEC_LAST         ISH_RESET_PREP_VEC
-#else
-/* only need handle single PMU wakeup interrupt */
-#define AON_IDT_ENTRY_VEC_LAST         ISH_PMU_WAKEUP_VEC
-#endif
-
-static void handle_reset(enum ish_pm_state pm_state);
-
-/* ISR for PMU wakeup interrupt */
-static void pmu_wakeup_isr(void)
-{
-	/**
-	 * Indicate completion of servicing the interrupt to IOAPIC first
-	 * then indicate completion of servicing the interrupt to LAPIC
-	 */
-	IOAPIC_EOI_REG = ISH_PMU_WAKEUP_VEC;
-	LAPIC_EOI_REG = 0x0;
-
-	__asm__ volatile ("iret;");
-
-	__builtin_unreachable();
-}
-
-/* ISR for reset prep interrupt */
-static void reset_prep_isr(void)
-{
-	/* mask reset prep avail interrupt */
-	PMU_RST_PREP = PMU_RST_PREP_INT_MASK;
-
-	/**
-	 * Indicate completion of servicing the interrupt to IOAPIC first
-	 * then indicate completion of servicing the interrupt to LAPIC
-	 */
-	IOAPIC_EOI_REG = ISH_RESET_PREP_VEC;
-	LAPIC_EOI_REG = 0x0;
-
-	handle_reset(ISH_PM_STATE_RESET_PREP);
-
-	__builtin_unreachable();
-}
-
-/**
- * Use a static data array for aon IDT, and setting IDT header for IDTR
- * register
- *
- * Due to very limit AON memory size (typically total 4KB), we don't want to
- * define and allocate whole 256 entries for aontask'IDT, that almost need 2KB
- * (256 * 8), so we just defined the only needed IDT entries:
- * AON_IDT_ENTRY_VEC_FIRST ~  AON_IDT_ENTRY_VEC_LAST
- *
- * Since on x86, the IDT entry index (count from 0) is also the interrupt
- * vector number, for IDT header, the 'start' filed still need to point to
- * the entry 0, and 'size' must count from entry 0.
- *
- * We only allocated memory for entry AON_IDT_ENTRY_VEC_FIRST to
- * AON_IDT_ENTRY_VEC_LAST, a little trick, but works well on ISH
- *
- *              ------>---------------------------<----- aon_idt_hdr.start
- *                |    |          entry 0        |
- *                |    +-------------------------+
- *                |    |           ...           |
- *                |    +-------------------------+<-----
- *  aon_idt_hdr.size   | AON_IDT_ENTRY_VEC_FIRST |    |
- *                |    +-------------------------+    |
- *                |    |            ...          | allocated memory in aon_idt
- *                |    +-------------------------+    |
- *                |    | AON_IDT_ENTRY_VEC_LAST  |    |
- *              ------>+-------------------------+<-----
- *                     |            ...          |
- *                     +-------------------------+
- *                     |          entry 255      |
- *                     ---------------------------
- */
-
-static struct idt_entry aon_idt[AON_IDT_ENTRY_VEC_LAST -
-				AON_IDT_ENTRY_VEC_FIRST + 1];
-
-static struct idt_header aon_idt_hdr = {
-
-	.limit = (sizeof(struct idt_entry) * (AON_IDT_ENTRY_VEC_LAST + 1)) - 1,
-	.entries = (struct idt_entry *)((uint32_t)&aon_idt -
-			(sizeof(struct idt_entry) * AON_IDT_ENTRY_VEC_FIRST))
-};
-
-/* aontask entry point function */
-void ish_aon_main(void);
-
-/**
- * 8 bytes reserved on stack, just for GDB to show the correct stack
- * information when doing source code level debuging
- */
-#define AON_SP_RESERVED (8)
-
-/* TSS segment for aon task */
-static struct tss_entry aon_tss = {
-	.prev_task_link = 0,
-	.reserved1 = 0,
-	.esp0 = (uint8_t *)(CONFIG_AON_PERSISTENT_BASE - AON_SP_RESERVED),
-	/* entry 1 in LDT for data segment */
-	.ss0 = 0xc,
-	.reserved2 = 0,
-	.esp1 = 0,
-	.ss1 = 0,
-	.reserved3 = 0,
-	.esp2 = 0,
-	.ss2 = 0,
-	.reserved4 = 0,
-	.cr3 = 0,
-	/* task excute entry point */
-	.eip = (uint32_t)&ish_aon_main,
-	.eflags = 0,
-	.eax = 0,
-	.ecx = 0,
-	.edx = 0,
-	.ebx = 0,
-	/* set stack top pointer at the end of usable aon memory */
-	.esp = CONFIG_AON_PERSISTENT_BASE - AON_SP_RESERVED,
-	.ebp = CONFIG_AON_PERSISTENT_BASE - AON_SP_RESERVED,
-	.esi = 0,
-	.edi = 0,
-	/* entry 1 in LDT for data segment */
-	.es = 0xc,
-	.reserved5 = 0,
-	/* entry 0 in LDT for code segment */
-	.cs = 0x4,
-	.reserved6 = 0,
-	/* entry 1 in LDT for data segment */
-	.ss = 0xc,
-	.reserved7 = 0,
-	/* entry 1 in LDT for data segment */
-	.ds = 0xc,
-	.reserved8 = 0,
-	/* entry 1 in LDT for data segment */
-	.fs = 0xc,
-	.reserved9 = 0,
-	/* entry 1 in LDT for data segment */
-	.gs = 0xc,
-	.reserved10 = 0,
-	.ldt_seg_selector = 0,
-	.reserved11 = 0,
-	.trap_debug = 0,
-
-	/**
-	 * TSS's limit specified as 0x67, to allow the task has permission to
-	 * access I/O port using IN/OUT instructions,'iomap_base_addr' field
-	 * must be greater than or equal to TSS' limit
-	 * see 'I/O port permissions' on
-	 *	https://en.wikipedia.org/wiki/Task_state_segment
-	 */
-	.iomap_base_addr = GDT_DESC_TSS_LIMIT
-};
-
-/**
- * define code and data LDT segements for aontask
- * code : base = 0x0, limit = 0xFFFFFFFF, Present = 1, DPL = 0
- * data : base = 0x0, limit = 0xFFFFFFFF, Present = 1, DPL = 0
- */
-static ldt_entry aon_ldt[2] = {
-
-	/**
-	 * entry 0 for code segment
-	 * base: 0x0
-	 * limit: 0xFFFFFFFF
-	 * flag: 0x9B, Present = 1, DPL = 0, code segment
-	 */
-	{
-		.dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF,
-				GDT_DESC_CODE_FLAGS),
-
-		.dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF,
-				GDT_DESC_CODE_FLAGS)
-	},
-
-	/**
-	 * entry 1 for data segment
-	 * base: 0x0
-	 * limit: 0xFFFFFFFF
-	 * flag: 0x93, Present = 1, DPL = 0, data segment
-	 */
-	{
-		.dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF,
-				GDT_DESC_DATA_FLAGS),
-
-		.dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF,
-				GDT_DESC_DATA_FLAGS)
-	}
-};
-
-
-/* shared data structure between main FW and aon task */
-struct ish_aon_share aon_share = {
-	.magic_id = AON_MAGIC_ID,
-	.error_count = 0,
-	.last_error = AON_SUCCESS,
-	.aon_tss = &aon_tss,
-	.aon_ldt = &aon_ldt[0],
-	.aon_ldt_size = sizeof(aon_ldt),
-};
-
-/* snowball structure */
-#if defined(CHIP_FAMILY_ISH3)
-/* on ISH3, reused ISH2PMC IPC message registers */
-#define SNOWBALL_BASE	IPC_ISH2PMC_MSG_BASE
-#else
-/* from ISH4, used reserved rom part of AON memory */
-#define SNOWBALL_BASE	(CONFIG_AON_PERSISTENT_BASE + 256)
-#endif
-
-struct snowball_struct *snowball = (void *)SNOWBALL_BASE;
-
-
-/* In IMR DDR, ISH FW image has a manifest header */
-#define ISH_FW_IMAGE_MANIFEST_HEADER_SIZE (0x1000)
-
-/* simple count based delay */
-static inline void delay(uint32_t count)
-{
-	while (count)
-		count--;
-}
-
-static int store_main_fw(void)
-{
-	int ret;
-	uint64_t imr_fw_addr;
-	uint64_t imr_fw_rw_addr;
-
-	imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) +
-		       snowball->uma_base_lo +
-		       snowball->fw_offset +
-		       ISH_FW_IMAGE_MANIFEST_HEADER_SIZE);
-
-	imr_fw_rw_addr = (imr_fw_addr
-			  + aon_share.main_fw_rw_addr
-			  - CONFIG_RAM_BASE);
-
-	/* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */
-	CCU_BCG_EN = CCU_BCG_EN & ~CCU_BCG_BIT_DMA;
-
-	/* store main FW's read and write data region to IMR/UMA DDR */
-	ret = ish_dma_copy(
-		PAGING_CHAN,
-		imr_fw_rw_addr,
-		aon_share.main_fw_rw_addr,
-		aon_share.main_fw_rw_size,
-		SRAM_TO_UMA);
-
-	/* enable BCG for DMA, DMA can't be accessed now */
-	CCU_BCG_EN = CCU_BCG_EN | CCU_BCG_BIT_DMA;
-
-	if (ret != DMA_RC_OK) {
-
-		aon_share.last_error = AON_ERROR_DMA_FAILED;
-		aon_share.error_count++;
-
-		return AON_ERROR_DMA_FAILED;
-	}
-
-	return AON_SUCCESS;
-}
-
-static int restore_main_fw(void)
-{
-	int ret;
-	uint64_t imr_fw_addr;
-	uint64_t imr_fw_ro_addr;
-	uint64_t imr_fw_rw_addr;
-
-	imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) +
-		       snowball->uma_base_lo +
-		       snowball->fw_offset +
-		       ISH_FW_IMAGE_MANIFEST_HEADER_SIZE);
-
-	imr_fw_ro_addr = (imr_fw_addr
-			  + aon_share.main_fw_ro_addr
-			  - CONFIG_RAM_BASE);
-
-	imr_fw_rw_addr = (imr_fw_addr
-			  + aon_share.main_fw_rw_addr
-			  - CONFIG_RAM_BASE);
-
-	/* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */
-	CCU_BCG_EN = CCU_BCG_EN & ~CCU_BCG_BIT_DMA;
-
-	/* restore main FW's read only code and data region from IMR/UMA DDR */
-	ret = ish_dma_copy(
-		PAGING_CHAN,
-		aon_share.main_fw_ro_addr,
-		imr_fw_ro_addr,
-		aon_share.main_fw_ro_size,
-		UMA_TO_SRAM);
-
-	if (ret != DMA_RC_OK) {
-
-		aon_share.last_error = AON_ERROR_DMA_FAILED;
-		aon_share.error_count++;
-
-		/* enable BCG for DMA, DMA can't be accessed now */
-		CCU_BCG_EN = CCU_BCG_EN | CCU_BCG_BIT_DMA;
-
-		return AON_ERROR_DMA_FAILED;
-	}
-
-	/* restore main FW's read and write data region from IMR/UMA DDR */
-	ret = ish_dma_copy(
-			PAGING_CHAN,
-			aon_share.main_fw_rw_addr,
-			imr_fw_rw_addr,
-			aon_share.main_fw_rw_size,
-			UMA_TO_SRAM
-			);
-
-	/* enable BCG for DMA, DMA can't be accessed now */
-	CCU_BCG_EN = CCU_BCG_EN | CCU_BCG_BIT_DMA;
-
-	if (ret != DMA_RC_OK) {
-
-		aon_share.last_error = AON_ERROR_DMA_FAILED;
-		aon_share.error_count++;
-
-		return AON_ERROR_DMA_FAILED;
-	}
-
-	return AON_SUCCESS;
-}
-
-#if defined(CHIP_FAMILY_ISH3)
-/* on ISH3, the last SRAM bank is reserved for AON use */
-#define SRAM_POWER_OFF_BANKS	(CONFIG_RAM_BANKS - 1)
-#elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
-/* ISH4 and ISH5 have separate AON memory, can power off entire main SRAM */
-#define SRAM_POWER_OFF_BANKS	CONFIG_RAM_BANKS
-#else
-#error "CHIP_FAMILY_ISH(3|4|5) must be defined"
-#endif
-
-/**
- * check SRAM bank i power gated status in PMU_SRAM_PG_EN register
- * 1: power gated 0: not power gated
- */
-#define BANK_PG_STATUS(i)	(PMU_SRAM_PG_EN & (0x1 << (i)))
-
-/* enable power gate of a SRAM bank */
-#define BANK_PG_ENABLE(i)	(PMU_SRAM_PG_EN |= (0x1 << (i)))
-
-/* disable power gate of a SRAM bank */
-#define BANK_PG_DISABLE(i)	(PMU_SRAM_PG_EN &= ~(0x1 << (i)))
-
-/**
- * check SRAM bank i disabled status in ISH_SRAM_CTRL_CSFGR register
- * 1: disabled 0: enabled
- */
-#define BANK_DISABLE_STATUS(i)	(ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4)))
-
-/* enable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */
-#define BANK_ENABLE(i)		(ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4)))
-
-/* disable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */
-#define BANK_DISABLE(i)		(ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4)))
-
-/* SRAM needs time to warm up after power on */
-#define SRAM_WARM_UP_DELAY_CNT		10
-
-/* SRAM needs time to enter retention mode */
-#define CYCLES_PER_US                  100
-#define SRAM_RETENTION_US_DELAY	       5
-#define SRAM_RETENTION_CYCLES_DELAY    (SRAM_RETENTION_US_DELAY * CYCLES_PER_US)
-
-static void sram_power(int on)
-{
-	int i;
-	uint32_t bank_size;
-	uint32_t sram_addr;
-	uint32_t erase_cfg;
-
-	bank_size = CONFIG_RAM_BANK_SIZE;
-	sram_addr = CONFIG_RAM_BASE;
-
-	/**
-	 * set erase size as one bank, erase control register using DWORD as
-	 * size unit, and using 0 based length, i.e if set 0, will erase one
-	 * DWORD
-	 */
-	erase_cfg = (((bank_size - 4) >> 2) << 2) | 0x1;
-
-	for (i = 0; i < SRAM_POWER_OFF_BANKS; i++) {
-
-		if (on && (BANK_PG_STATUS(i) || BANK_DISABLE_STATUS(i))) {
-
-			/* power on and enable a bank */
-			BANK_PG_DISABLE(i);
-
-			delay(SRAM_WARM_UP_DELAY_CNT);
-
-			BANK_ENABLE(i);
-
-			/* erase a bank */
-			ISH_SRAM_CTRL_ERASE_ADDR = sram_addr + (i * bank_size);
-			ISH_SRAM_CTRL_ERASE_CTRL = erase_cfg;
-
-			/* wait erase complete */
-			while (ISH_SRAM_CTRL_ERASE_CTRL & 0x1)
-				continue;
-
-		} else {
-			/* disable and power off a bank */
-			BANK_DISABLE(i);
-			BANK_PG_ENABLE(i);
-		}
-
-		/**
-		 * clear interrupt status register, not allow generate SRAM
-		 * interrupts. Bringup already masked all SRAM interrupts when
-		 * booting ISH
-		 */
-		ISH_SRAM_CTRL_INTR = 0xFFFFFFFF;
-
-	}
-}
-
-static void handle_d0i2(void)
-{
-	/* set main SRAM into retention mode*/
-	PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT
-		| PMU_LDO_RETENTION_BIT;
-
-	/* delay some cycles before halt */
-	delay(SRAM_RETENTION_CYCLES_DELAY);
-
-	ish_mia_halt();
-	/* wakeup from PMU interrupt */
-
-	/* set main SRAM intto normal mode */
-	PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT;
-
-	/**
-	 * poll LDO_READY status to make sure SRAM LDO is on
-	 * (exited retention mode)
-	 */
-	while (!(PMU_LDO_CTRL & PMU_LDO_READY_BIT))
-		continue;
-}
-
-static void handle_d0i3(void)
-{
-	int ret;
-
-	/* store main FW 's context to IMR DDR from main SRAM */
-	ret = store_main_fw();
-
-	/* if store main FW failed, then switch back to main FW */
-	if (ret != AON_SUCCESS)
-		return;
-
-	/* power off main SRAM */
-	sram_power(0);
-
-	ish_mia_halt();
-	/* wakeup from PMU interrupt */
-
-	/* power on main SRAM */
-	sram_power(1);
-
-	/* restore main FW 's context to main SRAM from IMR DDR */
-	ret = restore_main_fw();
-
-	if (ret != AON_SUCCESS) {
-		/* we can't switch back to main FW now, reset ISH */
-		handle_reset(ISH_PM_STATE_RESET);
-	}
-}
-
-static void handle_d3(void)
-{
-	/* handle D3 */
-	handle_reset(ISH_PM_STATE_RESET);
-}
-
-static void handle_reset(enum ish_pm_state pm_state)
-{
-	/* disable watch dog */
-	WDT_CONTROL &= ~WDT_CONTROL_ENABLE_BIT;
-
-	/* disable all gpio interrupts */
-	ISH_GPIO_GRER = 0;
-	ISH_GPIO_GFER = 0;
-	ISH_GPIO_GIMR = 0;
-
-	/* disable CSME CSR irq */
-	IPC_PIMR &= ~IPC_PIMR_CSME_CSR_BIT;
-
-	/* power off main SRAM */
-	sram_power(0);
-
-	while (1) {
-		/**
-		 * check if host ish driver already set the DMA enable flag
-		 *
-		 * ISH FW and ISH ipc host driver using IPC_ISH_RMP2 register
-		 * for synchronization during ISH boot.
-		 * ISH ipc host driver will set DMA_ENABLED_MASK bit when it
-		 * is loaded and starts, and clear this bit when it is removed.
-		 *
-		 * see: https://github.com/torvalds/linux/blob/master/drivers/
-		 *      hid/intel-ish-hid/ipc/ipc.c
-		 *
-		 * we have two kinds of reset situations need to handle here:
-		 * 1: reset ISH via uart console cmd or ectool host cmd
-		 * 2: S0 -> Sx (reset_prep interrupt)
-		 *
-		 * for #1, ISH ipc host driver no changed states,
-		 * DMA_ENABLED_MASK bit always set, so, will reset ISH directly
-		 *
-		 * for #2, ISH ipc host driver changed states, and cleared
-		 * DMA_ENABLED_MASK bit, then ISH FW received reset_prep
-		 * interrupt, ISH will stay in this while loop (most time in
-		 * halt state), waiting for DMA_ENABLED_MASK bit was set and
-		 * reset ISH then. Since ISH ROM have no power managment, stay
-		 * in aontask can save more power especially if system stay in
-		 * Sx for long time.
-		 *
-		 */
-		if (IPC_ISH_RMP2 & DMA_ENABLED_MASK) {
-
-			/* clear ISH2HOST doorbell register */
-			*IPC_ISH2HOST_DOORBELL_ADDR = 0;
-
-			/* clear error register in MISC space */
-			MISC_ISH_ECC_ERR_SRESP = 1;
-
-			/*
-			 * Disable power gating of RF(Cache) and ROMs.
-			 *
-			 * Before switch to aon task, RF and ROMs are already
-			 * power gated, so we need disable the power gating
-			 * before reset to ROM, to make sure ROM code runs
-			 * correctly.
-			 */
-			PMU_RF_ROM_PWR_CTRL = 0;
-
-			/* reset ISH minute-ia cpu core, will goto ISH ROM */
-			ish_mia_reset();
-
-			__builtin_unreachable();
-		}
-
-		ish_mia_halt();
-	}
-
-}
-
-static void handle_unknown_state(void)
-{
-	aon_share.last_error = AON_ERROR_NOT_SUPPORT_POWER_MODE;
-	aon_share.error_count++;
-
-	/* switch back to main FW */
-}
-
-void ish_aon_main(void)
-{
-
-	/* set PMU wakeup interrupt gate using LDT code segment selector(0x4) */
-	aon_idt[0].dword_lo = GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4,
-					IDT_DESC_FLAGS);
-
-	aon_idt[0].dword_up = GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4,
-					IDT_DESC_FLAGS);
-
-	if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) {
-		/*
-		 * set reset prep interrupt gate using LDT code segment
-		 * selector(0x4)
-		 */
-		aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST]
-			.dword_lo =
-			GEN_IDT_DESC_LO(&reset_prep_isr, 0x4, IDT_DESC_FLAGS);
-
-		aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST]
-			.dword_up =
-			GEN_IDT_DESC_UP(&reset_prep_isr, 0x4, IDT_DESC_FLAGS);
-	}
-
-	while (1) {
-
-		/**
-		 *  will start to run from here when switched to aontask from
-		 *  the second time
-		 */
-
-		/* save main FW's IDT and load aontask's IDT */
-		__asm__ volatile (
-				"sidtl %0;\n"
-				"lidtl %1;\n"
-				:
-				: "m" (aon_share.main_fw_idt_hdr),
-				  "m" (aon_idt_hdr)
-				);
-
-		aon_share.last_error = AON_SUCCESS;
-
-		switch (aon_share.pm_state) {
-		case ISH_PM_STATE_D0I2:
-			handle_d0i2();
-			break;
-		case ISH_PM_STATE_D0I3:
-			handle_d0i3();
-			break;
-		case ISH_PM_STATE_D3:
-			handle_d3();
-			break;
-		case ISH_PM_STATE_RESET:
-		case ISH_PM_STATE_RESET_PREP:
-			handle_reset(aon_share.pm_state);
-			break;
-		default:
-			handle_unknown_state();
-			break;
-		}
-
-		/* check if D3 rising status */
-		if (PMU_D3_STATUS &
-		    (PMU_D3_BIT_RISING_EDGE_STATUS | PMU_D3_BIT_SET)) {
-			aon_share.pm_state = ISH_PM_STATE_D3;
-			handle_d3();
-		}
-
-		/* restore main FW's IDT and switch back to main FW */
-		__asm__ volatile(
-				"lidtl %0;\n"
-				"iret;"
-				:
-				: "m" (aon_share.main_fw_idt_hdr)
-				);
-	}
-}
diff --git a/chip/ish/aontaskfw/ish_aontask.lds.S b/chip/ish/aontaskfw/ish_aontask.lds.S
deleted file mode 100644
index ca5f54f705..0000000000
--- a/chip/ish/aontaskfw/ish_aontask.lds.S
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <config_chip.h>
-
-ENTRY(ish_aon_main);
-
-#define SRAM_START	CONFIG_AON_RAM_BASE
-#define SRAM_RW_LEN	(CONFIG_AON_RAM_SIZE - CONFIG_AON_PERSISTENT_SIZE)
-
-/* reserved stack size */
-#define STACK_SIZE  (256)
-
-/**
- * resered 8 bytes for GDB showing correct stack
- * information during source code level debuging
- */
-#define RESERVED_GDB_SIZE  (8)
-
-#define RAM_LEN (SRAM_RW_LEN - STACK_SIZE - RESERVED_GDB_SIZE)
-
-/**
- *  AON memory layout
- * +---------+------------+-----------------+-----------------+
- * | RAM_LEN | STACK_SIZE | 8 Bytes for GDB | ROM (384 Bytes) |
- * +---------+------------+-----------------+-----------------+
- *
- * The first 256 bytes of the AON ROM is reserved for ECOS use.
- * The remaining 128 bytes of the AON ROM may be used by the shim
- * loader.
- */
-
-MEMORY
-{
-    /* leave STACK_SIZE bytes in the end of memory for stack */
-    RAM : ORIGIN = SRAM_START, LENGTH = RAM_LEN
-}
-
-SECTIONS
-{
-    /* AON parts visible to FW are linked to the beginning of the AON area */
-    .data.aon_share : AT(SRAM_START)
-    {
-	KEEP(*(.data.aon_share))
-    } > RAM
-
-    .data :
-    {
-	*(.data)
-	    *(.data*)
-    } > RAM
-
-    .text :
-    {
-	*(.text)
-	    *(.text*)
-    } > RAM
-
-    .bss :
-    {
-	*(.bss)
-	    *(.bss*)
-    } > RAM
-
-    .stack_tag :
-    {
-	KEEP(*(.stack_tag))
-    } > RAM
-
-}
diff --git a/chip/ish/build.mk b/chip/ish/build.mk
deleted file mode 100644
index bce9322184..0000000000
--- a/chip/ish/build.mk
+++ /dev/null
@@ -1,92 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# ISH chip specific files build
-#
-
-# ISH SoC has a Minute-IA core
-CORE:=minute-ia
-# Allow the i486 instruction set
-CFLAGS_CPU+=-march=pentium -mtune=i486 -m32
-
-ifeq ($(CONFIG_LTO),y)
-# Re-include the core's build.mk file so we can remove the lto flag.
-include core/$(CORE)/build.mk
-endif
-
-# Required chip modules
-chip-y+=clock.o gpio.o system.o hwtimer.o uart.o flash.o ish_persistent_data.o
-chip-$(CHIP_VARIANT_ISH5P4)+=reset_prep_wr.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-chip-$(CONFIG_HOSTCMD_HECI)+=host_command_heci.o
-chip-$(CONFIG_HOSTCMD_HECI)+=heci.o system_state_subsys.o ipc_heci.o
-chip-$(CONFIG_HID_HECI)+=hid_subsys.o
-chip-$(CONFIG_HID_HECI)+=heci.o system_state_subsys.o ipc_heci.o
-chip-$(CONFIG_DMA_PAGING)+=dma.o
-chip-$(CONFIG_LOW_POWER_IDLE)+=power_mgt.o
-
-# There is no framework for on-board tests in ISH. Do not specify any.
-test-list-y=
-
-# Build ish aon task fw
-ish-aon-name=ish_aontask
-ish-aon-$(CONFIG_ISH_PM_AONTASK)=aontaskfw/ish_aontask.o dma.o
-
-# Rules for building ish aon task fw
-ish-aon-out=$(out)/aontaskfw
-ish-aon-bin-$(CONFIG_ISH_PM_AONTASK)=$(ish-aon-out)/$(ish-aon-name).bin
-ish-aon-elf-$(CONFIG_ISH_PM_AONTASK)=$(ish-aon-out)/$(ish-aon-name).elf
-ish-aon-lds-$(CONFIG_ISH_PM_AONTASK)=$(ish-aon-out)/$(ish-aon-name).lds
-
-ish-aon-objs=$(call objs_from_dir,$(ish-aon-out)/chip/$(CHIP),ish-aon)
-ish-aon-deps+=$(addsuffix .d, $(ish-aon-objs)) $(ish-aon-lds-y).d
-
-cmd_ish_aon_elf = $(CC) $(ish-aon-objs) $(LDFLAGS) \
-	-o $@ -Wl,-T,$< -Wl,-Map,$(patsubst %.elf,%.map,$@)
-
-PROJECT_EXTRA+=$(ish-aon-bin-y)
-deps-$(CONFIG_ISH_PM_AONTASK)+=$(ish-aon-deps)
-
-$(out)/$(PROJECT).bin: $(ish-aon-bin-y) $(out)/RW/$(PROJECT).RW.flat
-
-$(ish-aon-bin-y): $(ish-aon-elf-y)
-	$(call quiet,elf_to_bin,EXTBIN )
-
-$(ish-aon-elf-y): $(ish-aon-lds-y) $(ish-aon-objs)
-	$(call quiet,ish_aon_elf,LD     )
-
-$(ish-aon-lds-y): chip/$(CHIP)/aontaskfw/ish_aontask.lds.S
-	-@ mkdir -p $(@D)
-	$(call quiet,lds,LDS    )
-
-$(ish-aon-out)/%.o: %.c
-	-@ mkdir -p $(@D)
-	$(call quiet,c_to_o,CC     )
-
-# Location of the scripts used to pack image
-SCRIPTDIR:=./chip/${CHIP}/util
-
-# Calculate aon binary file size and kernel binary file size
-_aon_size_str=$(shell stat -L -c %s $(ish-aon-bin-y))
-_aon_size=$(shell echo "$$(($(_aon_size_str)))")
-
-_kernel_size_str=$(shell stat -L -c %s $(out)/RW/$(PROJECT).RW.flat)
-_kernel_size=$(shell echo "$$(($(_kernel_size_str)))")
-
-# Commands to convert ec.RW.flat to $@.tmp - This will add the manifest header
-# needed to load the FW onto the ISH HW.
-
-ifeq ($(CONFIG_ISH_PM_AONTASK),y)
-cmd_obj_to_bin = ${SCRIPTDIR}/pack_ec.py -o $@.tmp \
-		 -k $(out)/RW/$(PROJECT).RW.flat \
-		 --kernel-size $(_kernel_size) \
-		 -a $(ish-aon-bin-y)  \
-		 --aon-size $(_aon_size);
-else
-cmd_obj_to_bin = ${SCRIPTDIR}/pack_ec.py -o $@.tmp \
-		 -k $(out)/RW/$(PROJECT).RW.flat \
-		 --kernel-size $(_kernel_size);
-endif
diff --git a/chip/ish/clock.c b/chip/ish/clock.c
deleted file mode 100644
index ac818f5733..0000000000
--- a/chip/ish/clock.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "common.h"
-#include "util.h"
-#include "power_mgt.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-
-void clock_init(void)
-{
-	/* No initialization for clock on ISH */
-}
-
-void clock_refresh_console_in_use(void)
-{
-	/**
-	 * on ISH, uart interrupt can only wakeup ISH from low power state via
-	 * CTS pin, but most ISH platforms only have Rx and Tx pins, no CTS pin
-	 * exposed, so, we need block ISH enter low power state for a while
-	 * when console is in use
-	 */
-	ish_pm_refresh_console_in_use();
-}
diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h
deleted file mode 100644
index b4dea95767..0000000000
--- a/chip/ish/config_chip.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/minute-ia/config_core.h"
-
-#ifndef __ASSEMBLER__
-/* Needed for PANIC_DATA_BASE */
-#include "ish_persistent_data.h"
-#endif
-
-/* Number of IRQ vectors on the ISH */
-#define CONFIG_IRQ_COUNT	(VEC_TO_IRQ(255) + 1)
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	2048
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Maximum number of deferrable functions */
-#define DEFERRABLE_MAX_COUNT	8
-
-/* this macro causes 'pause' and reduces loop counts inside loop. */
-#define CPU_RELAX() asm volatile("rep; nop" ::: "memory")
-
-/*****************************************************************************/
-/*                               Memory Layout                               */
-/*****************************************************************************/
-
-#ifdef CHIP_VARIANT_ISH5P4
-#define CONFIG_RAM_BASE		0xFF200000
-#else
-#define CONFIG_RAM_BASE		0xFF000000
-#endif
-#define CONFIG_RAM_SIZE		0x000A0000
-#define CONFIG_RAM_BANK_SIZE		0x00008000
-
-#if defined(CHIP_FAMILY_ISH3)
-/* On ISH3, there is no separate AON memory; use last 4KB of SRAM */
-#define CONFIG_AON_RAM_BASE		0xFF09F000
-#define CONFIG_AON_RAM_SIZE		0x00001000
-#elif defined(CHIP_FAMILY_ISH4)
-#define CONFIG_AON_RAM_BASE		0xFF800000
-#define CONFIG_AON_RAM_SIZE		0x00001000
-#elif defined(CHIP_FAMILY_ISH5)
-#define CONFIG_AON_RAM_BASE		0xFF800000
-#define CONFIG_AON_RAM_SIZE		0x00002000
-#else
-#error "CHIP_FAMILY_ISH(3|4|5) must be defined"
-#endif
-
-/* The end of the AON memory is reserved for read-only use */
-#define CONFIG_AON_PERSISTENT_SIZE	0x180
-#define CONFIG_AON_PERSISTENT_BASE	(CONFIG_AON_RAM_BASE	\
-					 + CONFIG_AON_RAM_SIZE	\
-					 - CONFIG_AON_PERSISTENT_SIZE)
-
-/* Store persistent panic data in AON memory. */
-#define CONFIG_PANIC_DATA_BASE		(&(ish_persistent_data.panic_data))
-
-/* System stack size */
-#define CONFIG_STACK_SIZE		1024
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		640
-#define LARGER_TASK_STACK_SIZE		1024
-#define HUGE_TASK_STACK_SIZE		2048
-/* Default task stack size */
-#define TASK_STACK_SIZE			640
-
-/****************************************************************************/
-/* Define our flash layout. */
-/* Note: The 4 macros below are unnecesasry for the ISH chip. However they are
- * referenced in common files and hence retained to avoid build errors.
- */
-
-/* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
-/* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00000000
-/* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000000
-/* Program memory base address */
-#define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
-
-#include "config_flash_layout.h"
-
-/*****************************************************************************/
-/*                        Watchdog Timer Configuration                       */
-/*****************************************************************************/
-#if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
-#define WDT_CLOCK_HZ		(120000000) /* 120 MHz */
-#elif defined(CHIP_FAMILY_ISH4)
-#define WDT_CLOCK_HZ		(100000000) /* 100 MHz */
-#else
-#error "CHIP_FAMILY_ISH(3|4|5) must be defined"
-#endif
-
-/* Provide WDT vec number to Minute-IA core implementation */
-#undef CONFIG_MIA_WDT_VEC
-#define CONFIG_MIA_WDT_VEC	ISH_WDT_VEC
-
-/****************************************************************************/
-/* Customize the build */
-/* Optional features present on this chip */
-
-/* ISH uses 64-bit hardware timer */
-#define CONFIG_HWTIMER_64BIT
-
-/* Macro used with gpio.inc, ISH only has port 0 */
-#define GPIO_PIN(index) 0, (1 << (index))
-#define GPIO_PIN_MASK(m) .port = 0, .mask = (m)
-
-#ifdef CHIP_VARIANT_ISH5P4
-/* Use combined ISR for ipc communication between host and ISH */
-#define CONFIG_ISH_HOST2ISH_COMBINED_ISR
-/* Use Synopsys Designware uart */
-#define CONFIG_ISH_DW_UART
-#else
-/* Need to clear ISH fabric error */
-#define CONFIG_ISH_CLEAR_FABRIC_ERRORS
-#endif
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/ish/config_flash_layout.h b/chip/ish/config_flash_layout.h
deleted file mode 100644
index 0430baf3eb..0000000000
--- a/chip/ish/config_flash_layout.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
-#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
-
-/* Mem-mapped, No external SPI for ISH */
-#undef CONFIG_EXTERNAL_STORAGE
-#define  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
-#undef CONFIG_SPI_FLASH
-
-#ifdef CHIP_VARIANT_ISH5P4
-#define CONFIG_ISH_BOOT_START		0xFF200000
-#else
-#define CONFIG_ISH_BOOT_START		0xFF000000
-#endif
-
-/*****************************************************************************/
-/* The following macros are not applicable for ISH, however the build fails if
- * they are not defined. Ideally, there should be an option in EC build to
- * turn off SPI and flash, making these unnecessary.
- */
-
-#define CONFIG_MAPPED_STORAGE_BASE	0x0
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  (CONFIG_FLASH_SIZE - 0x20000)
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   (CONFIG_FLASH_SIZE - 0x40000)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
-
-/* Unused for ISH - loader is external to ISH FW */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0xC00
-
-
-/* RO/RW images - not relevant for ISH
- */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
-#define CONFIG_RO_SIZE			(97 * 1024)
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-
-/*****************************************************************************/
-
-/* Not relevant for ISH */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF	0
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE	0x240
-
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
-
-/* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
-
-/* RW image starts at the beginning of SPI */
-#define CONFIG_RW_STORAGE_OFF		0
-
-#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/ish/dma.c b/chip/ish/dma.c
deleted file mode 100644
index a409dc6ad3..0000000000
--- a/chip/ish/dma.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* DMA module for ISH */
-
-#include "common.h"
-#include "console.h"
-#include "registers.h"
-#include "ish_dma.h"
-#include "util.h"
-
-static int dma_init_called; /* If ish_dma_init is called */
-
-static int dma_poll(uint32_t addr, uint32_t expected, uint32_t mask)
-{
-	int retval = -1;
-	uint32_t counter = 0;
-
-	/*
-	 * The timeout is approximately 2.2 seconds according to
-	 * value of UINT32_MAX, 120MHZ ISH clock frequency and
-	 * instruction count which is around 4.
-	 */
-	while (counter < (UINT32_MAX / 64)) {
-		/* test condition */
-		if ((REG32(addr) & mask) == expected) {
-			retval = DMA_RC_OK;
-			break;
-		}
-		counter++;
-	}
-
-	return retval;
-}
-
-void ish_dma_ocp_timeout_disable(void)
-{
-	uint32_t ctrl = OCP_AGENT_CONTROL;
-
-	OCP_AGENT_CONTROL = ctrl & OCP_RESPONSE_TO_DISABLE;
-}
-
-static inline uint32_t interrupt_lock(void)
-{
-	uint32_t eflags = 0;
-	__asm__ volatile("pushfl;" /* save eflag value */
-			 "popl  %0;"
-			 "cli;"
-			 : "=r"(eflags)); /* shut off interrupts */
-	return eflags;
-}
-
-static inline void interrupt_unlock(uint32_t eflags)
-{
-	__asm__ volatile("pushl  %0;" /* restore elfag values */
-			 "popfl;"
-			 :
-			 : "r"(eflags));
-}
-
-void dma_configure_psize(void)
-{
-	/* Give chan0 512 bytes for high performance, and chan1 128 bytes. */
-	DMA_PSIZE_01 = DMA_PSIZE_UPDATE |
-		       (DMA_PSIZE_CHAN1_SIZE << DMA_PSIZE_CHAN1_OFFSET) |
-		       (DMA_PSIZE_CHAN0_SIZE << DMA_PSIZE_CHAN0_OFFSET);
-}
-
-void ish_dma_init(void)
-{
-	uint32_t uma_msb;
-
-	ish_dma_ocp_timeout_disable();
-
-	/* configure DMA partition size */
-	dma_configure_psize();
-
-	/* set DRAM address 32 MSB for DMA transactions on UMA */
-	uma_msb = IPC_UMA_RANGE_LOWER_1;
-	ish_dma_set_msb(PAGING_CHAN, uma_msb, uma_msb);
-
-	dma_init_called = 1;
-}
-
-int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length,
-		 enum dma_mode mode)
-{
-	uint32_t chan_reg = DMA_REG_BASE + (DMA_CH_REGS_SIZE * chan);
-	int rc = DMA_RC_OK;
-	uint32_t eflags;
-	uint32_t chunk;
-
-	__asm__ volatile("\twbinvd\n"); /* Flush cache before dma start */
-
-	/* Bringup VNN power rail for accessing SoC fabric */
-	PMU_VNN_REQ = (1 << VNN_ID_DMA(chan));
-	while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS))
-		continue;
-
-	/*
-	 * shut off interrupts to assure no simultanious
-	 * access to DMA registers
-	 */
-	eflags = interrupt_lock();
-
-	MISC_CHID_CFG_REG = chan; /* Set channel to configure */
-
-	mode |= NON_SNOOP;
-	MISC_DMA_CTL_REG(chan) = mode; /* Set transfer direction */
-
-	DMA_CFG_REG = DMA_ENABLE;  /* Enable DMA module */
-	DMA_LLP(chan_reg) = 0;     /* Linked lists are not used */
-	DMA_CTL_LOW(chan_reg) =
-		0 /* Set transfer parameters */ |
-		(DMA_CTL_TT_FC_M2M_DMAC << DMA_CTL_TT_FC_SHIFT) |
-		(DMA_CTL_ADDR_INC << DMA_CTL_SINC_SHIFT) |
-		(DMA_CTL_ADDR_INC << DMA_CTL_DINC_SHIFT) |
-		(SRC_TR_WIDTH << DMA_CTL_SRC_TR_WIDTH_SHIFT) |
-		(DEST_TR_WIDTH << DMA_CTL_DST_TR_WIDTH_SHIFT) |
-		(SRC_BURST_SIZE << DMA_CTL_SRC_MSIZE_SHIFT) |
-		(DEST_BURST_SIZE << DMA_CTL_DEST_MSIZE_SHIFT);
-
-	interrupt_unlock(eflags);
-	while (length) {
-		chunk = (length > DMA_MAX_BLOCK_SIZE) ? DMA_MAX_BLOCK_SIZE
-						      : length;
-
-		if (rc != DMA_RC_OK)
-			break;
-
-		eflags = interrupt_lock();
-		MISC_CHID_CFG_REG = chan; /* Set channel to configure */
-		DMA_CTL_HIGH(chan_reg) =
-			chunk;		 /* Set number of bytes to transfer */
-		DMA_DAR(chan_reg) = dst; /* Destination address */
-		DMA_SAR(chan_reg) = src; /* Source address */
-		DMA_EN_REG = DMA_CH_EN_BIT(chan) |
-			     DMA_CH_EN_WE_BIT(chan); /* Enable the channel */
-		interrupt_unlock(eflags);
-
-		rc = ish_wait_for_dma_done(
-			chan); /* Wait for trans completion */
-
-		dst += chunk;
-		src += chunk;
-		length -= chunk;
-	}
-
-	/* Mark the DMA VNN power rail as no longer needed */
-	PMU_VNN_REQ = (1 << VNN_ID_DMA(chan));
-	return rc;
-}
-
-void ish_dma_disable(void)
-{
-	uint32_t channel;
-	uint32_t counter;
-
-	/* Disable DMA on per-channel basis. */
-	for (channel = 0; channel <= DMA_MAX_CHANNEL; channel++) {
-		MISC_CHID_CFG_REG = channel;
-		if (DMA_EN_REG & DMA_CH_EN_BIT(channel)) {
-			/* Write 0 to channel enable bit ... */
-			DMA_EN_REG = DMA_CH_EN_WE_BIT(channel);
-
-			/* Wait till it shuts up. */
-			counter = 0;
-			while ((DMA_EN_REG & DMA_CH_EN_BIT(channel)) &&
-			       counter < (UINT32_MAX / 64))
-				counter++;
-		}
-	}
-	DMA_CLR_ERR_REG = 0xFFFFFFFF;
-	DMA_CLR_BLOCK_REG = 0xFFFFFFFF;
-
-	DMA_CFG_REG = 0; /* Disable DMA module */
-}
-
-int ish_wait_for_dma_done(uint32_t ch)
-{
-	return dma_poll(DMA_EN_REG_ADDR, 0, DMA_CH_EN_BIT(ch));
-}
-
-void ish_dma_set_msb(uint32_t chan, uint32_t dst_msb, uint32_t src_msb)
-{
-	uint32_t eflags = interrupt_lock();
-	MISC_CHID_CFG_REG = chan; /* Set channel to configure */
-	MISC_SRC_FILLIN_DMA(chan) = src_msb;
-	MISC_DST_FILLIN_DMA(chan) = dst_msb;
-	interrupt_unlock(eflags);
-}
diff --git a/chip/ish/flash.c b/chip/ish/flash.c
deleted file mode 100644
index 8ef4d1a73c..0000000000
--- a/chip/ish/flash.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "flash.h"
-
-
-/**
- * Initialize the module.
- *
- * Applies at-boot protection settings if necessary.
- */
-int flash_pre_init(void)
-{
-	return EC_SUCCESS;
-}
diff --git a/chip/ish/gpio.c b/chip/ish/gpio.c
deleted file mode 100644
index 3d374f3cb8..0000000000
--- a/chip/ish/gpio.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for ISH */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define ISH_TOTAL_GPIO_PINS 8
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Unimplemented GPIOs shouldn't do anything */
-	if (g->port == DUMMY_GPIO_BANK)
-		return 0;
-
-	return  !!(ISH_GPIO_GPLR & g->mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Unimplemented GPIOs shouldn't do anything */
-	if (g->port == DUMMY_GPIO_BANK)
-		return;
-
-	if (value)
-		ISH_GPIO_GPSR |= g->mask;
-	else
-		ISH_GPIO_GPCR |= g->mask;
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/* Unimplemented GPIOs shouldn't do anything */
-	if (port == DUMMY_GPIO_BANK)
-		return;
-
-	/* ISH does not support level-trigger interrupts; only edge. */
-	if (flags & (GPIO_INT_F_HIGH | GPIO_INT_F_LOW)) {
-		ccprintf("\n\nISH does not support level trigger GPIO for %d "
-			 "0x%02x!\n\n",
-			 port, mask);
-	}
-
-	/* ISH 3 can't support both rising and falling edge */
-	if (IS_ENABLED(CHIP_FAMILY_ISH3) &&
-	    (flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) {
-		ccprintf("\n\nISH 2/3 does not support both rising & falling "
-			 "edge for %d 0x%02x\n\n",
-			 port, mask);
-	}
-
-	/* GPSR/GPCR Output high/low */
-	if (flags & GPIO_HIGH) /* Output high */
-		ISH_GPIO_GPSR |= mask;
-	else if (flags & GPIO_LOW)  /* output low */
-		ISH_GPIO_GPCR |= mask;
-
-	/* GPDR pin direction 1 = output, 0 = input*/
-	if (flags & GPIO_OUTPUT)
-		ISH_GPIO_GPDR |= mask;
-	else /* GPIO_INPUT or un-configured */
-		ISH_GPIO_GPDR &= ~mask;
-
-	/* Interrupt is asserted on rising edge */
-	if (flags & GPIO_INT_F_RISING)
-		ISH_GPIO_GRER |= mask;
-	else
-		ISH_GPIO_GRER &= ~mask;
-
-	/* Interrupt is asserted on falling edge */
-	if (flags & GPIO_INT_F_FALLING)
-		ISH_GPIO_GFER |= mask;
-	else
-		ISH_GPIO_GFER &= ~mask;
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Unimplemented GPIOs shouldn't do anything */
-	if (g->port == DUMMY_GPIO_BANK)
-		return EC_SUCCESS;
-
-	ISH_GPIO_GIMR |= g->mask;
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	ISH_GPIO_GIMR &= ~g->mask;
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	ISH_GPIO_GISR = g->mask;
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	int i;
-	int flags;
-	int is_warm = system_is_reboot_warm();
-	const struct gpio_info *g = gpio_list;
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-
-		flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels
-		 * or we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-
-	/* disable GPIO interrupts */
-	ISH_GPIO_GIMR = 0;
-	/* clear pending GPIO interrupts */
-	ISH_GPIO_GISR = 0xFFFFFFFF;
-}
-
-static void gpio_init(void)
-{
-	task_enable_irq(ISH_GPIO_IRQ);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-static void gpio_interrupt(void)
-{
-	int i;
-	const struct gpio_info *g = gpio_list;
-	uint32_t gisr = ISH_GPIO_GISR;
-	uint32_t gimr = ISH_GPIO_GIMR;
-
-	/* mask off any not enabled pins */
-	gisr &= gimr;
-
-	for (i = 0; i < GPIO_IH_COUNT; i++, g++) {
-		if (gisr & g->mask) {
-			/* write 1 to clear interrupt status bit */
-			ISH_GPIO_GISR = g->mask;
-			gpio_irq_handlers[i](i);
-		}
-	}
-}
-DECLARE_IRQ(ISH_GPIO_IRQ, gpio_interrupt);
diff --git a/chip/ish/hbm.h b/chip/ish/hbm.h
deleted file mode 100644
index edfb587d21..0000000000
--- a/chip/ish/hbm.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __HBM_H
-#define __HBM_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#include "heci_client.h"
-
-#define HBM_MAJOR_VERSION			1
-#ifdef HECI_ENABLE_DMA
-#define HBM_MINOR_VERSION			2
-#else
-#define HBM_MINOR_VERSION			0
-#endif
-
-#define __packed __attribute__((packed))
-
-#define HECI_MSG_REPONSE_FLAG			0x80
-
-enum HECI_BUS_MSG {
-	/* requests */
-	HECI_BUS_MSG_VERSION_REQ		= 1,
-	HECI_BUS_MSG_HOST_STOP_REQ		= 2,
-	HECI_BUS_MSG_ME_STOP_REQ		= 3,
-	HECI_BUS_MSG_HOST_ENUM_REQ		= 4,
-	HECI_BUS_MSG_HOST_CLIENT_PROP_REQ	= 5,
-	HECI_BUS_MSG_CLIENT_CONNECT_REQ		= 6,
-	HECI_BUS_MSG_CLIENT_DISCONNECT_REQ	= 7,
-	HECI_BUS_MSG_FLOW_CONTROL		= 8,
-	HECI_BUS_MSG_RESET_REQ			= 9,
-	HECI_BUS_MSG_ADD_CLIENT_REQ		= 0x0A,
-	HECI_BUS_MSG_DMA_REQ			= 0x10,
-	HECI_BUS_MSG_DMA_ALLOC_NOTIFY		= 0x11,
-	HECI_BUS_MSG_DMA_XFER_REQ		= 0x12,
-
-	/* responses */
-	HECI_BUS_MSG_VERSION_RESP		=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_VERSION_REQ),
-	HECI_BUS_MSG_HOST_STOP_RESP		=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_STOP_REQ),
-	HECI_BUS_MSG_HOST_ENUM_RESP		=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_ENUM_REQ),
-	HECI_BUS_MSG_HOST_CLIENT_PROP_RESP	=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_CLIENT_PROP_REQ),
-	HECI_BUS_MSG_CLIENT_CONNECT_RESP	=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_CONNECT_REQ),
-	HECI_BUS_MSG_CLIENT_DISCONNECT_RESP	= 
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_DISCONNECT_REQ),
-	HECI_BUS_MSG_RESET_RESP			=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_RESET_REQ),
-	HECI_BUS_MSG_ADD_CLIENT_RESP		=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_ADD_CLIENT_REQ),
-	HECI_BUS_MSG_DMA_RESP			=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_REQ),
-	HECI_BUS_MSG_DMA_ALLOC_RESP		=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_ALLOC_NOTIFY),
-	HECI_BUS_MSG_DMA_XFER_RESP		=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_XFER_REQ)
-};
-
-enum {
-	HECI_CONNECT_STATUS_SUCCESS           = 0,
-	HECI_CONNECT_STATUS_CLIENT_NOT_FOUND  = 1,
-	HECI_CONNECT_STATUS_ALREADY_EXISTS    = 2,
-	HECI_CONNECT_STATUS_REJECTED          = 3,
-	HECI_CONNECT_STATUS_INVALID_PARAMETER = 4,
-	HECI_CONNECT_STATUS_INACTIVE_CLIENT   = 5,
-};
-
-struct hbm_version {
-	uint8_t minor;
-	uint8_t major;
-} __packed;
-
-struct hbm_version_req {
-	uint8_t reserved;
-	struct hbm_version version;
-} __packed;
-
-struct hbm_version_res {
-	uint8_t supported;
-	struct hbm_version version;
-} __packed;
-
-struct hbm_enum_req {
-	uint8_t reserved[3];
-} __packed;
-
-struct hbm_enum_res {
-	uint8_t reserved[3];
-	uint8_t valid_addresses[32];
-} __packed;
-
-struct hbm_client_prop_req {
-	uint8_t address;
-	uint8_t reserved[2];
-} __packed;
-
-#define CLIENT_DMA_ENABLE	0x80
-
-struct hbm_client_properties {
-	struct heci_guid protocol_name; /* heci client protocol ID */
-	uint8_t protocol_version;	/* protocol version */
-	/* max connection from host to client. currently only 1 is allowed */
-	uint8_t max_number_of_connections;
-	uint8_t fixed_address;	/* not yet supported */
-	uint8_t single_recv_buf; /* not yet supported */
-	uint32_t max_msg_length; /* max payload size */
-	/* not yet supported. [7] enable/disable, [6:0] dma length */
-	uint8_t dma_hdr_len;
-	uint8_t reserved4;
-	uint8_t reserved5;
-	uint8_t reserved6;
-} __packed;
-
-struct hbm_client_prop_res {
-	uint8_t address;
-	uint8_t status;
-	uint8_t reserved[1];
-	struct hbm_client_properties client_prop;
-} __packed;
-
-struct hbm_client_connect_req {
-	uint8_t fw_addr;
-	uint8_t host_addr;
-	uint8_t reserved;
-} __packed;
-
-struct hbm_client_connect_res {
-	uint8_t fw_addr;
-	uint8_t host_addr;
-	uint8_t status;
-} __packed;
-
-struct hbm_flow_control {
-	uint8_t fw_addr;
-	uint8_t host_addr;
-	uint8_t reserved[5];
-} __packed;
-
-struct hbm_client_disconnect_req {
-	uint8_t fw_addr;
-	uint8_t host_addr;
-	uint8_t reserved;
-} __packed;
-
-struct hbm_client_disconnect_res {
-	uint8_t fw_addr;
-	uint8_t host_addr;
-	uint8_t status;
-} __packed;
-
-struct hbm_host_stop_req {
-	uint8_t reason;
-	uint8_t reserved[2];
-};
-
-struct hbm_host_stop_res {
-	uint8_t reserved[3];
-};
-
-/* host bus message : host -> ish */
-struct hbm_h2i {
-	uint8_t cmd;
-	union {
-		struct hbm_version_req			ver_req;
-		struct hbm_enum_req			enum_req;
-		struct hbm_client_prop_req		client_prop_req;
-		struct hbm_client_connect_req		client_connect_req;
-		struct hbm_flow_control			flow_ctrl;
-		struct hbm_client_disconnect_req	client_disconnect_req;
-		struct hbm_host_stop_req		host_stop_req;
-	} data;
-} __packed;
-
-/* host bus message : i2h -> host */
-struct hbm_i2h {
-	uint8_t cmd;
-	union {
-		struct hbm_version_res			ver_res;
-		struct hbm_enum_res			enum_res;
-		struct hbm_client_prop_res		client_prop_res;
-		struct hbm_client_connect_res		client_connect_res;
-		struct hbm_flow_control			flow_ctrl;
-		struct hbm_client_disconnect_res	client_disconnect_res;
-		struct hbm_host_stop_res		host_stop_res;
-	} data;
-} __packed;
-
-#endif /* __HBM_H */
diff --git a/chip/ish/heci.c b/chip/ish/heci.c
deleted file mode 100644
index 309a17c0a1..0000000000
--- a/chip/ish/heci.c
+++ /dev/null
@@ -1,1026 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "hbm.h"
-#include "heci_client.h"
-#include "ipc_heci.h"
-#include "system_state.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-
-struct heci_header {
-	uint8_t fw_addr;
-	uint8_t host_addr;
-	uint16_t length; /* [8:0] length, [14:9] reserved, [15] msg_complete */
-} __packed;
-#define HECI_MSG_CMPL_SHIFT		15
-#define HECI_MSG_LENGTH_MASK		0x01FF
-#define HECI_MSG_LENGTH(length)		((length) & HECI_MSG_LENGTH_MASK)
-#define HECI_MSG_IS_COMPLETED(length) \
-				(!!((length) & (0x01 << HECI_MSG_CMPL_SHIFT)))
-
-BUILD_ASSERT(HECI_IPC_PAYLOAD_SIZE ==
-	     (IPC_MAX_PAYLOAD_SIZE - sizeof(struct heci_header)));
-
-struct heci_msg {
-	struct heci_header hdr;
-	uint8_t payload[HECI_IPC_PAYLOAD_SIZE];
-} __packed;
-
-/* HECI addresses */
-#define HECI_HBM_ADDRESS		0	/* HECI Bus Message */
-#define HECI_DYN_CLIENT_ADDR_START	0x20	/* Dynamic client start addr */
-
-/* A fw client has the same value for both handle and fw address */
-#define TO_FW_ADDR(handle)		((uintptr_t)(handle))
-#define TO_HECI_HANDLE(fw_addr)		((heci_handle_t)(uintptr_t)(fw_addr))
-/* convert client fw address to client context index */
-#define TO_CLIENT_CTX_IDX(fw_addr)	((fw_addr) - HECI_DYN_CLIENT_ADDR_START)
-
-/* should be less than HECI_INVALID_HANDLE - 1 */
-BUILD_ASSERT(HECI_MAX_NUM_OF_CLIENTS < 0x0FE);
-
-struct heci_client_connect {
-	uint8_t is_connected;	/* client is connected to host */
-	uint8_t host_addr;	/* connected host address */
-
-	/* receiving message */
-	uint8_t ignore_rx_msg;
-	uint8_t	rx_msg[HECI_MAX_MSG_SIZE];
-	size_t  rx_msg_length;
-
-	uint32_t flow_ctrl_creds; /* flow control */
-	struct mutex lock; /* protects against 2 writers */
-	struct mutex cred_lock; /* protects flow ctrl */
-	int waiting_task;
-};
-
-struct heci_client_context {
-	const struct heci_client *client;
-	void *data;	/* client specific data */
-
-	struct heci_client_connect connect; /* connection context */
-	struct ss_subsys_device ss_device; /* system state receiver device */
-};
-
-struct heci_bus_context {
-	ipc_handle_t ipc_handle; /* ipc handle for heci protocol */
-
-	int num_of_clients;
-	struct heci_client_context client_ctxs[HECI_MAX_NUM_OF_CLIENTS];
-};
-
-/* declare heci bus */
-struct heci_bus_context heci_bus_ctx = {
-		.ipc_handle = IPC_INVALID_HANDLE,
-};
-
-static inline struct heci_client_context *
-heci_get_client_context(const uint8_t fw_addr)
-{
-	return &heci_bus_ctx.client_ctxs[TO_CLIENT_CTX_IDX(fw_addr)];
-}
-
-static inline struct heci_client_connect *
-heci_get_client_connect(const uint8_t fw_addr)
-{
-	struct heci_client_context *cli_ctx = heci_get_client_context(fw_addr);
-	return &cli_ctx->connect;
-}
-
-static inline int heci_is_client_connected(const uint8_t fw_addr)
-{
-	struct heci_client_context *cli_ctx = heci_get_client_context(fw_addr);
-	return cli_ctx->connect.is_connected;
-}
-
-static inline int heci_is_valid_client_addr(const uint8_t fw_addr)
-{
-	uint8_t cli_idx = TO_CLIENT_CTX_IDX(fw_addr);
-
-	return cli_idx < heci_bus_ctx.num_of_clients;
-}
-
-static inline int heci_is_valid_handle(const heci_handle_t handle)
-{
-	return heci_is_valid_client_addr((uintptr_t)(handle));
-}
-
-/* find heci device that contains this system state device in it */
-#define ss_device_to_heci_client_context(ss_dev) \
-	((struct heci_client_context *)((void *)(ss_dev) - \
-	(void *)(&(((struct heci_client_context *)0)->ss_device))))
-#define client_context_to_handle(cli_ctx) \
-	((heci_handle_t)((uint32_t)((cli_ctx) - &heci_bus_ctx.client_ctxs[0]) \
-	/ sizeof(heci_bus_ctx.client_ctxs[0]) + 1))
-
-/*
- * each heci device registered as system state device which gets
- * system state(e.g. suspend/resume, portrait/landscape) events
- * through system state subsystem from host
- */
-static int heci_client_suspend(struct ss_subsys_device *ss_device)
-{
-	struct heci_client_context *cli_ctx =
-			ss_device_to_heci_client_context(ss_device);
-	heci_handle_t handle = client_context_to_handle(cli_ctx);
-
-	if (cli_ctx->client->cbs->suspend)
-		cli_ctx->client->cbs->suspend(handle);
-
-	return EC_SUCCESS;
-}
-
-static int heci_client_resume(struct ss_subsys_device *ss_device)
-{
-	struct heci_client_context *cli_ctx =
-			ss_device_to_heci_client_context(ss_device);
-	heci_handle_t handle = client_context_to_handle(cli_ctx);
-
-	if (cli_ctx->client->cbs->resume)
-		cli_ctx->client->cbs->resume(handle);
-
-	return EC_SUCCESS;
-}
-
-struct system_state_callbacks heci_ss_cbs = {
-	.suspend = heci_client_suspend,
-	.resume = heci_client_resume,
-};
-
-/*
- * This function should be called only by HECI_CLIENT_ENTRY()
- */
-heci_handle_t heci_register_client(const struct heci_client *client)
-{
-	int ret;
-	heci_handle_t handle;
-	struct heci_client_context *cli_ctx;
-
-	if (client == NULL || client->cbs == NULL)
-		return HECI_INVALID_HANDLE;
-
-	/*
-	 * we don't need mutex here since this function is called by
-	 * entry function which is serialized among heci clients.
-	 */
-	if (heci_bus_ctx.num_of_clients >= HECI_MAX_NUM_OF_CLIENTS)
-		return HECI_INVALID_HANDLE;
-
-	/* we only support 1 connection */
-	if (client->max_n_of_connections > 1)
-		return HECI_INVALID_HANDLE;
-
-	if (client->max_msg_size > HECI_MAX_MSG_SIZE)
-		return HECI_INVALID_HANDLE;
-
-	/* create handle with the same value of fw address */
-	handle = (heci_handle_t)(heci_bus_ctx.num_of_clients +
-				 HECI_DYN_CLIENT_ADDR_START);
-	cli_ctx = &heci_bus_ctx.client_ctxs[heci_bus_ctx.num_of_clients++];
-	cli_ctx->client = client;
-
-	if (client->cbs->initialize) {
-		ret = client->cbs->initialize(handle);
-		if (ret) {
-			heci_bus_ctx.num_of_clients--;
-			return HECI_INVALID_HANDLE;
-		}
-	}
-
-	if (client->cbs->suspend || client->cbs->resume) {
-		cli_ctx->ss_device.cbs = &heci_ss_cbs;
-		ss_subsys_register_client(&cli_ctx->ss_device);
-	}
-
-	return handle;
-}
-
-static void heci_build_hbm_header(struct heci_header *hdr, uint32_t length)
-{
-	hdr->fw_addr = HECI_HBM_ADDRESS;
-	hdr->host_addr = HECI_HBM_ADDRESS;
-	hdr->length = length;
-	/* payload of hbm is less than IPC payload */
-	hdr->length |= (uint16_t)1 << HECI_MSG_CMPL_SHIFT;
-}
-
-static void heci_build_fixed_client_header(struct heci_header *hdr,
-					   const uint8_t fw_addr,
-					   const uint32_t length)
-{
-	hdr->fw_addr = fw_addr;
-	hdr->host_addr = 0;
-	hdr->length = length;
-	/* Fixed client payload < IPC payload */
-	hdr->length |= (uint16_t)1 << HECI_MSG_CMPL_SHIFT;
-}
-
-static int heci_send_heci_msg_timestamp(struct heci_msg *msg,
-					uint32_t *timestamp)
-{
-	int length, written;
-
-	if (heci_bus_ctx.ipc_handle == IPC_INVALID_HANDLE)
-		return -1;
-
-	length = sizeof(msg->hdr) + HECI_MSG_LENGTH(msg->hdr.length);
-	written = ipc_write_timestamp(heci_bus_ctx.ipc_handle, msg, length,
-				      timestamp);
-
-	if (written != length) {
-		CPRINTF("%s error : len = %d err = %d\n", __func__,
-			(int)length, written);
-		return -EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int heci_send_heci_msg(struct heci_msg *msg)
-{
-	return heci_send_heci_msg_timestamp(msg, NULL);
-}
-
-int heci_set_client_data(const heci_handle_t handle, void *data)
-{
-	struct heci_client_context *cli_ctx;
-	const uint8_t fw_addr = TO_FW_ADDR(handle);
-
-	if (!heci_is_valid_handle(handle))
-		return -EC_ERROR_INVAL;
-
-	cli_ctx = heci_get_client_context(fw_addr);
-	cli_ctx->data = data;
-
-	return EC_SUCCESS;
-}
-
-void *heci_get_client_data(const heci_handle_t handle)
-{
-	struct heci_client_context *cli_ctx;
-	const uint8_t fw_addr = TO_FW_ADDR(handle);
-
-	if (!heci_is_valid_handle(handle))
-		return NULL;
-
-	cli_ctx = heci_get_client_context(fw_addr);
-	return cli_ctx->data;
-}
-
-/*
- * Waits for flow control credit that allows TX transactions
- *
- * Returns true if credit was acquired, otherwise false
- */
-static int wait_for_flow_ctrl_cred(struct heci_client_connect *connect)
-{
-	int need_to_wait;
-
-	do {
-		mutex_lock(&connect->cred_lock);
-		need_to_wait = !connect->flow_ctrl_creds;
-		if (need_to_wait) {
-			connect->waiting_task = task_get_current();
-		} else {
-			connect->flow_ctrl_creds = 0;
-			connect->waiting_task = 0;
-		}
-		mutex_unlock(&connect->cred_lock);
-		if (need_to_wait) {
-			/*
-			 * A second is more than enough, otherwise if will
-			 * probably never happen.
-			 */
-			int ev = task_wait_event_mask(TASK_EVENT_IPC_READY,
-						      SECOND);
-			if (ev & TASK_EVENT_TIMER) {
-				/* Return false, not able to get credit */
-				return 0;
-			}
-		}
-	} while (need_to_wait);
-
-	/* We successfully got flow control credit */
-	return 1;
-}
-
-int heci_send_msg_timestamp(const heci_handle_t handle, uint8_t *buf,
-			    const size_t buf_size, uint32_t *timestamp)
-{
-	int buf_offset = 0, ret = 0, remain, payload_size;
-	struct heci_client_connect *connect;
-	struct heci_msg msg;
-	const uint8_t fw_addr = TO_FW_ADDR(handle);
-
-	if (!heci_is_valid_handle(handle))
-		return -EC_ERROR_INVAL;
-
-	if (buf_size > HECI_MAX_MSG_SIZE)
-		return -EC_ERROR_OVERFLOW;
-
-	connect = heci_get_client_connect(fw_addr);
-	mutex_lock(&connect->lock);
-
-	if (!heci_is_client_connected(fw_addr)) {
-		ret = -HECI_ERR_CLIENT_IS_NOT_CONNECTED;
-		goto err_locked;
-	}
-
-	if (!wait_for_flow_ctrl_cred(connect)) {
-		CPRINTF("no cred\n");
-		ret = -HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST;
-		goto err_locked;
-	}
-
-	msg.hdr.fw_addr = fw_addr;
-	msg.hdr.host_addr = connect->host_addr;
-
-	remain = buf_size;
-	while (remain) {
-		if (remain > HECI_IPC_PAYLOAD_SIZE) {
-			msg.hdr.length = HECI_IPC_PAYLOAD_SIZE;
-			payload_size = HECI_IPC_PAYLOAD_SIZE;
-		} else {
-			msg.hdr.length = remain;
-			/* set as last heci msg */
-			msg.hdr.length |= (uint16_t)1 << HECI_MSG_CMPL_SHIFT;
-			payload_size = remain;
-		}
-
-		memcpy(msg.payload, buf + buf_offset, payload_size);
-
-		heci_send_heci_msg_timestamp(&msg, timestamp);
-
-		remain -= payload_size;
-		buf_offset += payload_size;
-	}
-	mutex_unlock(&connect->lock);
-
-	return buf_size;
-
-err_locked:
-	mutex_unlock(&connect->lock);
-
-	return ret;
-}
-
-int heci_send_msg(const heci_handle_t handle, uint8_t *buf,
-		  const size_t buf_size)
-{
-	return heci_send_msg_timestamp(handle, buf, buf_size, NULL);
-}
-
-
-int heci_send_msgs(const heci_handle_t handle,
-		   const struct heci_msg_list *msg_list)
-{
-	struct heci_msg_item *cur_item;
-	int total_size = 0;
-	int i, msg_cur_pos, buf_size, copy_size, msg_sent;
-	struct heci_client_connect *connect;
-	struct heci_msg msg;
-	const uint8_t fw_addr = TO_FW_ADDR(handle);
-
-	if (!heci_is_valid_handle(handle))
-		return -EC_ERROR_INVAL;
-
-	for (i = 0; i < msg_list->num_of_items; i++) {
-		if (!msg_list->items[i]->size || !msg_list->items[i]->buf)
-			return -EC_ERROR_INVAL;
-
-		total_size += msg_list->items[i]->size;
-	}
-
-	if (total_size > HECI_MAX_MSG_SIZE)
-		return -EC_ERROR_OVERFLOW;
-
-	if (msg_list->num_of_items > HECI_MAX_MSGS)
-		return -HECI_ERR_TOO_MANY_MSG_ITEMS;
-
-	connect = heci_get_client_connect(fw_addr);
-	mutex_lock(&connect->lock);
-
-	if (!heci_is_client_connected(fw_addr)) {
-		total_size = -HECI_ERR_CLIENT_IS_NOT_CONNECTED;
-		goto err_locked;
-	}
-
-	if (!wait_for_flow_ctrl_cred(connect)) {
-		CPRINTF("no cred\n");
-		total_size = -HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST;
-		goto err_locked;
-	}
-
-	msg.hdr.fw_addr = fw_addr;
-	msg.hdr.host_addr = connect->host_addr;
-
-	i = 1;
-	msg_cur_pos = 0;
-	buf_size = 0;
-	cur_item = msg_list->items[0];
-	msg_sent = 0;
-	while (1) {
-		/* get next item if current item is consumed */
-		if (msg_cur_pos == cur_item->size) {
-			/*
-			 * break if no more item.
-			 * if "msg" contains data to be sent
-			 * it will be sent after break.
-			 */
-			if (i == msg_list->num_of_items)
-				break;
-
-			/* get next item and reset msg_cur_pos */
-			cur_item = msg_list->items[i++];
-			msg_cur_pos = 0;
-		}
-
-		/* send data in ipc buf if it's completely filled */
-		if (buf_size == HECI_IPC_PAYLOAD_SIZE) {
-			msg.hdr.length = buf_size;
-			msg_sent += buf_size;
-
-			/* no leftovers, send the last msg here */
-			if (msg_sent == total_size) {
-				msg.hdr.length |=
-					(uint16_t)1 << HECI_MSG_CMPL_SHIFT;
-			}
-
-			heci_send_heci_msg(&msg);
-			buf_size = 0;
-		}
-
-		/* fill ipc msg buffer */
-		if (cur_item->size - msg_cur_pos >
-		    HECI_IPC_PAYLOAD_SIZE - buf_size) {
-			copy_size = HECI_IPC_PAYLOAD_SIZE - buf_size;
-		} else {
-			copy_size = cur_item->size - msg_cur_pos;
-		}
-
-		memcpy(msg.payload + buf_size, cur_item->buf + msg_cur_pos,
-		       copy_size);
-
-		msg_cur_pos += copy_size;
-		buf_size += copy_size;
-	}
-
-	/* leftovers ? send last msg */
-	if (buf_size != 0) {
-		msg.hdr.length = buf_size;
-		msg.hdr.length |= (uint16_t)1 << HECI_MSG_CMPL_SHIFT;
-
-		heci_send_heci_msg(&msg);
-	}
-
-err_locked:
-	mutex_unlock(&connect->lock);
-
-	return total_size;
-
-}
-
-/* For now, we only support fixed client payload size < IPC payload size */
-int heci_send_fixed_client_msg(const uint8_t fw_addr, uint8_t *buf,
-			       const size_t buf_size)
-{
-	struct heci_msg msg;
-
-	heci_build_fixed_client_header(&msg.hdr, fw_addr, buf_size);
-
-	memcpy(msg.payload, buf, buf_size);
-
-	heci_send_heci_msg(&msg);
-
-	return EC_SUCCESS;
-}
-
-static int handle_version_req(struct hbm_version_req *ver_req)
-{
-	struct hbm_version_res *ver_res;
-	struct heci_msg heci_msg;
-	struct hbm_i2h *i2h;
-
-	heci_build_hbm_header(&heci_msg.hdr,
-			      sizeof(i2h->cmd) + sizeof(*ver_res));
-
-	i2h = (struct hbm_i2h *)heci_msg.payload;
-	i2h->cmd = HECI_BUS_MSG_VERSION_RESP;
-	ver_res = (struct hbm_version_res *)&i2h->data;
-
-	memset(ver_res, 0, sizeof(*ver_res));
-
-	ver_res->version.major = HBM_MAJOR_VERSION;
-	ver_res->version.minor = HBM_MINOR_VERSION;
-	if (ver_req->version.major == HBM_MAJOR_VERSION &&
-	    ver_req->version.minor == HBM_MINOR_VERSION) {
-		ver_res->supported = 1;
-	} else {
-		ver_res->supported = 0;
-	}
-
-	heci_send_heci_msg(&heci_msg);
-
-	return EC_SUCCESS;
-}
-
-#define BITS_PER_BYTE			8
-/* get number of bits for one element of "valid_addresses" array */
-#define	BITS_PER_ELEMENT \
-	(sizeof(((struct hbm_enum_res *)0)->valid_addresses[0]) * BITS_PER_BYTE)
-
-static int handle_enum_req(struct hbm_enum_req *enum_req)
-{
-	struct hbm_enum_res *enum_res;
-	struct heci_msg heci_msg;
-	struct hbm_i2h *i2h;
-	int i;
-
-	heci_build_hbm_header(&heci_msg.hdr,
-			      sizeof(i2h->cmd) + sizeof(*enum_res));
-
-	i2h = (struct hbm_i2h *)heci_msg.payload;
-	i2h->cmd = HECI_BUS_MSG_HOST_ENUM_RESP;
-	enum_res = (struct hbm_enum_res *)&i2h->data;
-
-	memset(enum_res, 0, sizeof(*enum_res));
-
-	/*
-	 * fw address 0 is reserved for HECI Bus Message
-	 * fw address 1 ~ 0x1f are reserved for fixed clients
-	 * fw address 0x20 ~ 0xFF is for dynamic clients
-	 * bit-0 set -> fw address "0", bit-1 set -> fw address "1"
-	 */
-	for (i = HECI_DYN_CLIENT_ADDR_START;
-	     i < heci_bus_ctx.num_of_clients + HECI_DYN_CLIENT_ADDR_START;
-	     i++) {
-		enum_res->valid_addresses[i / BITS_PER_ELEMENT] |=
-			1 << (i & (BITS_PER_ELEMENT - 1));
-	}
-
-	heci_send_heci_msg(&heci_msg);
-
-	return EC_SUCCESS;
-}
-
-static int handle_client_prop_req(struct hbm_client_prop_req *client_prop_req)
-{
-	struct hbm_client_prop_res *client_prop_res;
-	struct heci_msg heci_msg;
-	struct hbm_i2h *i2h;
-	struct heci_client_context *client_ctx;
-	const struct heci_client *client;
-
-	heci_build_hbm_header(&heci_msg.hdr,
-			      sizeof(i2h->cmd) + sizeof(*client_prop_res));
-
-	i2h = (struct hbm_i2h *)heci_msg.payload;
-	i2h->cmd = HECI_BUS_MSG_HOST_CLIENT_PROP_RESP;
-	client_prop_res = (struct hbm_client_prop_res *)&i2h->data;
-
-	memset(client_prop_res, 0, sizeof(*client_prop_res));
-
-	client_prop_res->address = client_prop_req->address;
-	if (!heci_is_valid_client_addr(client_prop_req->address)) {
-		client_prop_res->status = HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
-	} else {
-		struct hbm_client_properties *client_prop;
-
-		client_ctx = heci_get_client_context(client_prop_req->address);
-		client = client_ctx->client;
-		client_prop = &client_prop_res->client_prop;
-
-		client_prop->protocol_name = client->protocol_id;
-		client_prop->protocol_version = client->protocol_ver;
-		client_prop->max_number_of_connections =
-						client->max_n_of_connections;
-		client_prop->max_msg_length = client->max_msg_size;
-		client_prop->dma_hdr_len = client->dma_header_length;
-		client_prop->dma_hdr_len |= client->dma_enabled ?
-					    CLIENT_DMA_ENABLE : 0;
-	}
-
-	heci_send_heci_msg(&heci_msg);
-
-	return EC_SUCCESS;
-}
-
-static int heci_send_flow_control(uint8_t fw_addr)
-{
-	struct heci_client_connect *connect;
-	struct hbm_i2h *i2h;
-	struct hbm_flow_control *flow_ctrl;
-	struct heci_msg heci_msg;
-
-	connect = heci_get_client_connect(fw_addr);
-
-	heci_build_hbm_header(&heci_msg.hdr,
-			      sizeof(i2h->cmd) + sizeof(*flow_ctrl));
-
-	i2h = (struct hbm_i2h *)heci_msg.payload;
-	i2h->cmd = HECI_BUS_MSG_FLOW_CONTROL;
-	flow_ctrl = (struct hbm_flow_control *)&i2h->data;
-
-	memset(flow_ctrl, 0, sizeof(*flow_ctrl));
-
-	flow_ctrl->fw_addr = fw_addr;
-	flow_ctrl->host_addr = connect->host_addr;
-
-	heci_send_heci_msg(&heci_msg);
-
-	return EC_SUCCESS;
-}
-
-static int handle_client_connect_req(
-			struct hbm_client_connect_req *client_connect_req)
-{
-	struct hbm_client_connect_res *client_connect_res;
-	struct heci_msg heci_msg;
-	struct hbm_i2h *i2h;
-	struct heci_client_connect *connect;
-
-	heci_build_hbm_header(&heci_msg.hdr,
-			      sizeof(i2h->cmd) + sizeof(*client_connect_res));
-
-	i2h = (struct hbm_i2h *)heci_msg.payload;
-	i2h->cmd = HECI_BUS_MSG_CLIENT_CONNECT_RESP;
-	client_connect_res = (struct hbm_client_connect_res *)&i2h->data;
-
-	memset(client_connect_res, 0, sizeof(*client_connect_res));
-
-	client_connect_res->fw_addr = client_connect_req->fw_addr;
-	client_connect_res->host_addr = client_connect_req->host_addr;
-	if (!heci_is_valid_client_addr(client_connect_req->fw_addr)) {
-		client_connect_res->status =
-					HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
-	} else if (!client_connect_req->host_addr) {
-		client_connect_res->status =
-			HECI_CONNECT_STATUS_INVALID_PARAMETER;
-	} else {
-		connect = heci_get_client_connect(client_connect_req->fw_addr);
-		if (connect->is_connected) {
-			client_connect_res->status =
-					HECI_CONNECT_STATUS_ALREADY_EXISTS;
-		} else {
-			connect->is_connected = 1;
-			connect->host_addr = client_connect_req->host_addr;
-		}
-	}
-
-	heci_send_heci_msg(&heci_msg);
-
-	/* no error, send flow control */
-	if (!client_connect_res->status)
-		heci_send_flow_control(client_connect_req->fw_addr);
-
-	return EC_SUCCESS;
-}
-
-static int handle_flow_control_cmd(struct hbm_flow_control *flow_ctrl)
-{
-	struct heci_client_connect *connect;
-	int waiting_task;
-
-	if (!heci_is_valid_client_addr(flow_ctrl->fw_addr))
-		return -1;
-
-	if (!heci_is_client_connected(flow_ctrl->fw_addr))
-		return -1;
-
-	connect = heci_get_client_connect(flow_ctrl->fw_addr);
-
-	mutex_lock(&connect->cred_lock);
-	connect->flow_ctrl_creds = 1;
-	waiting_task = connect->waiting_task;
-	mutex_unlock(&connect->cred_lock);
-
-	if (waiting_task)
-		task_set_event(waiting_task, TASK_EVENT_IPC_READY, 0);
-
-	return EC_SUCCESS;
-}
-
-static void heci_handle_client_msg(struct heci_msg *msg, size_t length)
-{
-	struct heci_client_context *cli_ctx;
-	struct heci_client_connect *connect;
-	const struct heci_client_callbacks *cbs;
-	int payload_size;
-
-	if (!heci_is_valid_client_addr(msg->hdr.fw_addr))
-		return;
-
-	if (!heci_is_client_connected(msg->hdr.fw_addr))
-		return;
-
-	cli_ctx = heci_get_client_context(msg->hdr.fw_addr);
-	cbs = cli_ctx->client->cbs;
-	connect = &cli_ctx->connect;
-
-	payload_size = HECI_MSG_LENGTH(msg->hdr.length);
-	if (connect->is_connected &&
-	    msg->hdr.host_addr == connect->host_addr) {
-		if (!connect->ignore_rx_msg &&
-		    connect->rx_msg_length + payload_size > HECI_MAX_MSG_SIZE) {
-			connect->ignore_rx_msg = 1; /* too big. discard */
-		}
-
-		if (!connect->ignore_rx_msg) {
-			memcpy(connect->rx_msg + connect->rx_msg_length,
-			       msg->payload, payload_size);
-
-			connect->rx_msg_length += payload_size;
-		}
-
-		if (HECI_MSG_IS_COMPLETED(msg->hdr.length)) {
-			if (!connect->ignore_rx_msg) {
-				cbs->new_msg_received(
-					TO_HECI_HANDLE(msg->hdr.fw_addr),
-					connect->rx_msg,
-					connect->rx_msg_length);
-			}
-
-			connect->rx_msg_length = 0;
-			connect->ignore_rx_msg = 0;
-
-			heci_send_flow_control(msg->hdr.fw_addr);
-		}
-	}
-}
-
-static int handle_client_disconnect_req(
-			struct hbm_client_disconnect_req *client_disconnect_req)
-{
-	struct hbm_client_disconnect_res *client_disconnect_res;
-	struct heci_msg heci_msg;
-	struct hbm_i2h *i2h;
-	struct heci_client_context *cli_ctx;
-	struct heci_client_connect *connect;
-	const struct heci_client_callbacks *cbs;
-	uint8_t fw_addr, host_addr;
-
-	CPRINTS("Got HECI disconnect request");
-
-	heci_build_hbm_header(&heci_msg.hdr, sizeof(i2h->cmd) +
-					     sizeof(*client_disconnect_res));
-
-	i2h = (struct hbm_i2h *)heci_msg.payload;
-	i2h->cmd = HECI_BUS_MSG_CLIENT_DISCONNECT_RESP;
-	client_disconnect_res = (struct hbm_client_disconnect_res *)&i2h->data;
-
-	memset(client_disconnect_res, 0, sizeof(*client_disconnect_res));
-
-	fw_addr = client_disconnect_req->fw_addr;
-	host_addr = client_disconnect_req->host_addr;
-
-	client_disconnect_res->fw_addr = fw_addr;
-	client_disconnect_res->host_addr = host_addr;
-	if (!heci_is_valid_client_addr(fw_addr) ||
-	    !heci_is_client_connected(fw_addr)) {
-		client_disconnect_res->status =
-					HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
-	} else {
-		connect = heci_get_client_connect(fw_addr);
-		if (connect->host_addr != host_addr) {
-			client_disconnect_res->status =
-				HECI_CONNECT_STATUS_INVALID_PARAMETER;
-		} else {
-			cli_ctx = heci_get_client_context(fw_addr);
-			cbs = cli_ctx->client->cbs;
-			mutex_lock(&connect->lock);
-			if (connect->is_connected) {
-				cbs->disconnected(TO_HECI_HANDLE(fw_addr));
-				connect->is_connected = 0;
-			}
-			mutex_unlock(&connect->lock);
-		}
-	}
-
-	heci_send_heci_msg(&heci_msg);
-
-	return EC_SUCCESS;
-}
-
-/* host stops due to version mismatch */
-static int handle_host_stop_req(struct hbm_host_stop_req *host_stop_req)
-{
-	struct hbm_host_stop_res *host_stop_res;
-	struct heci_msg heci_msg;
-	struct hbm_i2h *i2h;
-
-	heci_build_hbm_header(&heci_msg.hdr,
-			      sizeof(i2h->cmd) + sizeof(*host_stop_res));
-
-	i2h = (struct hbm_i2h *)heci_msg.payload;
-	i2h->cmd = HECI_BUS_MSG_HOST_STOP_RESP;
-	host_stop_res = (struct hbm_host_stop_res *)&i2h->data;
-
-	memset(host_stop_res, 0, sizeof(*host_stop_res));
-
-	heci_send_heci_msg(&heci_msg);
-
-	return EC_SUCCESS;
-}
-
-static int is_hbm_validity(struct hbm_h2i *h2i, size_t length)
-{
-	int valid_msg_len;
-
-	valid_msg_len = sizeof(h2i->cmd);
-
-	switch (h2i->cmd) {
-	case HECI_BUS_MSG_VERSION_REQ:
-		valid_msg_len += sizeof(struct hbm_version_req);
-		break;
-
-	case HECI_BUS_MSG_HOST_ENUM_REQ:
-		valid_msg_len += sizeof(struct hbm_enum_req);
-		break;
-
-	case HECI_BUS_MSG_HOST_CLIENT_PROP_REQ:
-		valid_msg_len += sizeof(struct hbm_client_prop_req);
-		break;
-
-	case HECI_BUS_MSG_CLIENT_CONNECT_REQ:
-		valid_msg_len += sizeof(struct hbm_client_connect_req);
-		break;
-
-	case HECI_BUS_MSG_FLOW_CONTROL:
-		valid_msg_len += sizeof(struct hbm_flow_control);
-		break;
-
-	case HECI_BUS_MSG_CLIENT_DISCONNECT_REQ:
-		valid_msg_len += sizeof(struct hbm_client_disconnect_req);
-		break;
-
-	case HECI_BUS_MSG_HOST_STOP_REQ:
-		valid_msg_len += sizeof(struct hbm_host_stop_req);
-		break;
-
-/* TODO: DMA support for large data */
-#if 0
-	case HECI_BUS_MSG_DMA_REQ:
-		valid_msg_len += sizeof(struct hbm_dma_req);
-		break;
-
-	case HECI_BUS_MSG_DMA_ALLOC_NOTIFY:
-		valid_msg_len += sizeof(struct hbm_dma_alloc_notify);
-		break;
-
-	case HECI_BUS_MSG_DMA_XFER_REQ: /* DMA transfer to FW */
-		valid_msg_len += sizeof(struct hbm_dma_xfer_req);
-		break;
-
-	case HECI_BUS_MSG_DMA_XFER_RESP: /* Ack for DMA transfer from FW */
-		valid_msg_len += sizeof(struct hbm_dma_xfer_resp);
-		break;
-#endif
-	default:
-		break;
-	}
-
-	if (valid_msg_len != length) {
-		CPRINTF("invalid cmd(%d) valid : %d, cur : %zd\n",
-			h2i->cmd, valid_msg_len, length);
-		/* TODO: invalid cmd. not sure to reply with error ? */
-		return 0;
-	}
-
-	return 1;
-}
-
-static void heci_handle_hbm(struct hbm_h2i *h2i, size_t length)
-{
-	void *data = (void *)&h2i->data;
-
-	if (!is_hbm_validity(h2i, length))
-		return;
-
-	switch (h2i->cmd) {
-	case HECI_BUS_MSG_VERSION_REQ:
-		handle_version_req((struct hbm_version_req *)data);
-		break;
-
-	case HECI_BUS_MSG_HOST_ENUM_REQ:
-		handle_enum_req((struct hbm_enum_req *)data);
-		break;
-
-	case HECI_BUS_MSG_HOST_CLIENT_PROP_REQ:
-		handle_client_prop_req((struct hbm_client_prop_req *)data);
-		break;
-
-	case HECI_BUS_MSG_CLIENT_CONNECT_REQ:
-		handle_client_connect_req(
-					(struct hbm_client_connect_req *)data);
-		break;
-
-	case HECI_BUS_MSG_FLOW_CONTROL:
-		handle_flow_control_cmd((struct hbm_flow_control *)data);
-		break;
-
-	case HECI_BUS_MSG_CLIENT_DISCONNECT_REQ:
-		handle_client_disconnect_req(
-				(struct hbm_client_disconnect_req *)data);
-		break;
-
-	case HECI_BUS_MSG_HOST_STOP_REQ:
-		handle_host_stop_req((struct hbm_host_stop_req *)data);
-		break;
-
-/* TODO: DMA transfer if data is too big >= ? KB */
-#if 0
-	case HECI_BUS_MSG_DMA_REQ:
-		handle_dma_req((struct hbm_dma_req *)data);
-		break;
-
-	case HECI_BUS_MSG_DMA_ALLOC_NOTIFY:
-		handle_dma_alloc_notify((struct hbm_dma_alloc_notify *));
-		break;
-
-	case HECI_BUS_MSG_DMA_XFER_REQ: /* DMA transfer to FW */
-		handle_dma_xfer_req((struct hbm_dma_xfer_req *)data);
-		break;
-
-	case HECI_BUS_MSG_DMA_XFER_RESP: /* Ack for DMA transfer from FW */
-		handle_dma_xfer_resp((struct hbm_dma_xfer_resp *)data);
-		break;
-#endif
-	default:
-		break;
-	}
-}
-
-static void heci_handle_heci_msg(struct heci_msg *heci_msg, size_t msg_length)
-{
-	if (!heci_msg->hdr.host_addr) {
-		/*
-		 * message for HECI bus or a fixed client should fit
-		 * into one IPC message
-		 */
-		if (!HECI_MSG_IS_COMPLETED(heci_msg->hdr.length)) {
-			CPRINTS("message not completed");
-			return;
-		}
-
-		if (heci_msg->hdr.fw_addr == HECI_FIXED_SYSTEM_STATE_ADDR)
-			heci_handle_system_state_msg(
-				heci_msg->payload,
-				HECI_MSG_LENGTH(heci_msg->hdr.length));
-		else if (!heci_msg->hdr.fw_addr)
-			/* HECI Bus Message(fw_addr == 0 && host_addr == 0) */
-			heci_handle_hbm((struct hbm_h2i *)heci_msg->payload,
-					HECI_MSG_LENGTH(heci_msg->hdr.length));
-		else
-			CPRINTS("not supported fixed client(%d)",
-				heci_msg->hdr.fw_addr);
-	} else {
-		/* host_addr != 0 : Msg for Dynamic client */
-		heci_handle_client_msg(heci_msg, msg_length);
-	}
-}
-
-/* event flag for HECI msg */
-#define EVENT_FLAG_BIT_HECI_MSG			TASK_EVENT_CUSTOM_BIT(0)
-
-void heci_rx_task(void)
-{
-	int msg_len;
-	struct heci_msg heci_msg;
-	ipc_handle_t ipc_handle;
-
-	/* open IPC for HECI protocol */
-	heci_bus_ctx.ipc_handle = ipc_open(IPC_PEER_ID_HOST, IPC_PROTOCOL_HECI,
-					   EVENT_FLAG_BIT_HECI_MSG);
-
-	ASSERT(heci_bus_ctx.ipc_handle != IPC_INVALID_HANDLE);
-
-	/* get ipc handle */
-	ipc_handle = heci_bus_ctx.ipc_handle;
-
-	while (1) {
-		/* task will be blocked here, waiting for event */
-		msg_len = ipc_read(ipc_handle, &heci_msg, sizeof(heci_msg), -1);
-
-		if (msg_len <= 0) {
-			CPRINTS("discard heci packet");
-			continue;
-		}
-
-		if (HECI_MSG_LENGTH(heci_msg.hdr.length) + sizeof(heci_msg.hdr)
-		    == msg_len)
-			heci_handle_heci_msg(&heci_msg, msg_len);
-		else
-			CPRINTS("msg len mismatch.. discard..");
-	}
-}
diff --git a/chip/ish/heci_client.h b/chip/ish/heci_client.h
deleted file mode 100644
index 9dca4bff90..0000000000
--- a/chip/ish/heci_client.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __HECI_CLIENT_H
-#define __HECI_CLIENT_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#include "hooks.h"
-
-#define HECI_MAX_NUM_OF_CLIENTS			2
-
-#define HECI_MAX_MSG_SIZE			4960
-#define HECI_IPC_PAYLOAD_SIZE   (IPC_MAX_PAYLOAD_SIZE - 4)
-#define HECI_MAX_MSGS				3
-
-enum HECI_ERR {
-	HECI_ERR_TOO_MANY_MSG_ITEMS		= EC_ERROR_INTERNAL_FIRST + 0,
-	HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST	= EC_ERROR_INTERNAL_FIRST + 1,
-	HECI_ERR_CLIENT_IS_NOT_CONNECTED	= EC_ERROR_INTERNAL_FIRST + 2,
-};
-
-typedef void *					heci_handle_t;
-
-#define HECI_INVALID_HANDLE			NULL
-
-struct heci_guid {
-	uint32_t data1;
-	uint16_t data2;
-	uint16_t data3;
-	uint8_t data4[8];
-};
-
-struct heci_client_callbacks {
-	/*
-	 * called while registering heci client.
-	 * if returns non-zero, the registration will fail.
-	 */
-	int (*initialize)(const heci_handle_t handle);
-	/* called when new heci msg for the client is arrived */
-	void (*new_msg_received)(const heci_handle_t handle, uint8_t *msg,
-				 const size_t msg_size);
-	/* called when the heci client is disconnected */
-	void (*disconnected)(const heci_handle_t handle);
-
-	/* called when ISH goes to suspend */
-	int (*suspend)(const heci_handle_t);
-	/* called when ISH resumes */
-	int (*resume)(const heci_handle_t);
-};
-
-struct heci_client {
-	struct heci_guid protocol_id;
-	uint32_t max_msg_size;
-	uint8_t protocol_ver;
-	uint8_t max_n_of_connections;
-	uint8_t dma_header_length :7;
-	uint8_t dma_enabled :1;
-
-	const struct heci_client_callbacks *cbs;
-};
-
-struct heci_msg_item {
-	size_t size;
-	uint8_t *buf;
-};
-
-struct heci_msg_list {
-	int num_of_items;
-	struct heci_msg_item *items[HECI_MAX_MSGS];
-};
-
-/*
- * Do not call this function directly.
- * The function should be called only by HECI_CLIENT_ENTRY()
- */
-heci_handle_t heci_register_client(const struct heci_client *client);
-int heci_set_client_data(const heci_handle_t handle, void *data);
-void *heci_get_client_data(const heci_handle_t handle);
-
-/*
- * Send a client message. Note this function waits a short while for the HECI
- * bus to become available for sending. This method blocks until either the heci
- * message is sent or the message as been queued to send in the lower IPC layer.
- *
- * All callers that use the same underlying IPC channel will be serialized.
- */
-int heci_send_msg(const heci_handle_t handle, uint8_t *buf,
-		  const size_t buf_size);
-int heci_send_msg_timestamp(const heci_handle_t handle, uint8_t *buf,
-		  const size_t buf_size, uint32_t *timestamp);
-/*
- * send client msgs(using list of buffer&size).
- * heci_msg_item with size == 0 is not acceptable.
- */
-int heci_send_msgs(const heci_handle_t handle,
-		   const struct heci_msg_list *msg_list);
-/* send msg to fixed client(system level client) */
-int heci_send_fixed_client_msg(const uint8_t fw_addr, uint8_t *buf,
-			       const size_t buf_size);
-
-#define HECI_CLIENT_ENTRY(heci_client) \
-	void _heci_entry_##heci_client(void) \
-	{ \
-		heci_register_client(&(heci_client)); \
-	} \
-	DECLARE_HOOK(HOOK_INIT, _heci_entry_##heci_client, HOOK_PRIO_LAST - 1)
-
-#endif /* __HECI_CLIENT_H */
diff --git a/chip/ish/hid_device.h b/chip/ish/hid_device.h
deleted file mode 100644
index 0a32e305af..0000000000
--- a/chip/ish/hid_device.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __HID_DEVICE_H
-#define __HID_DEVICE_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#include "hooks.h"
-
-#define HID_SUBSYS_MAX_PAYLOAD_SIZE			4954
-
-enum HID_SUBSYS_ERR {
-	HID_SUBSYS_ERR_NOT_READY		= EC_ERROR_INTERNAL_FIRST + 0,
-	HID_SUBSYS_ERR_TOO_MANY_HID_DEVICES	= EC_ERROR_INTERNAL_FIRST + 1,
-};
-
-typedef void *					hid_handle_t;
-#define HID_INVALID_HANDLE			NULL
-
-struct hid_callbacks {
-	/*
-	 * function called during registration.
-	 * if returns non-zero, the registration will fail.
-	 */
-	int (*initialize)(const hid_handle_t handle);
-
-	/* return size of data copied to buf. if returns <= 0, error */
-	int (*get_hid_descriptor)(const hid_handle_t handle, uint8_t *buf,
-				  const size_t buf_size);
-	/* return size of data copied  to buf. if return <= 0, error */
-	int (*get_report_descriptor)(const hid_handle_t handle, uint8_t *buf,
-				     const size_t buf_size);
-	/* return size of data copied to buf. if return <= 0, error */
-	int (*get_feature_report)(const hid_handle_t handle,
-				  const uint8_t report_id, uint8_t *buf,
-				  const size_t buf_size);
-	/* return tranferred data size. if returns <= 0, error */
-	int (*set_feature_report)(const hid_handle_t handle,
-				  const uint8_t report_id, const uint8_t *data,
-				  const size_t data_size);
-	/* return size of data copied to buf. if returns <= 0, error */
-	int (*get_input_report)(const hid_handle_t handle,
-				const uint8_t report_id, uint8_t *buf,
-				const size_t buf_size);
-
-	/* suspend/resume, if returns non-zero, error */
-	int (*resume)(const hid_handle_t handle);
-	int (*suspend)(const hid_handle_t handle);
-};
-
-struct hid_device {
-	uint8_t dev_class;
-	uint16_t pid;
-	uint16_t vid;
-
-	const struct hid_callbacks *cbs;
-};
-
-/*
- * Do not call this function directly.
- * The function should be called only by HID_DEVICE_ENTRY()
- */
-hid_handle_t hid_subsys_register_device(const struct hid_device *dev_info);
-/* send HID input report */
-int hid_subsys_send_input_report(const hid_handle_t handle, uint8_t *buf,
-				 const size_t buf_size);
-/* store HID device specific data */
-int hid_subsys_set_device_data(const hid_handle_t handle, void *data);
-/* retrieve HID device specific data */
-void *hid_subsys_get_device_data(const hid_handle_t handle);
-
-#define HID_DEVICE_ENTRY(hid_dev) \
-	void _hid_dev_entry_##hid_dev(void) \
-	{ \
-		hid_subsys_register_device(&(hid_dev)); \
-	} \
-	DECLARE_HOOK(HOOK_INIT, _hid_dev_entry_##hid_dev, HOOK_PRIO_LAST - 2)
-
-#endif /* __HID_DEVICE_H */
diff --git a/chip/ish/hid_subsys.c b/chip/ish/hid_subsys.c
deleted file mode 100644
index bd3f331fdc..0000000000
--- a/chip/ish/hid_subsys.c
+++ /dev/null
@@ -1,447 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "compile_time_macros.h"
-#include "console.h"
-#include "heci_client.h"
-#include "hid_device.h"
-#include "util.h"
-
-#ifdef HID_SUBSYS_DEBUG
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-#else
-#define CPUTS(outstr)
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-#endif
-
-#define __packed __attribute__((packed))
-
-#define HECI_CLIENT_HID_GUID { 0x33AECD58, 0xB679, 0x4E54,\
-			 { 0x9B, 0xD9, 0xA0, 0x4D, 0x34, 0xF0, 0xC2, 0x26 } }
-
-#define HID_SUBSYS_MAX_HID_DEVICES			3
-
-/*
- * the following enum values and data structures with __packed are used for
- * communicating with host driver and they are copied from host driver.
- */
-enum {
-	HID_GET_HID_DESCRIPTOR = 0,
-	HID_GET_REPORT_DESCRIPTOR,
-	HID_GET_FEATURE_REPORT,
-	HID_SET_FEATURE_REPORT,
-	HID_GET_INPUT_REPORT,
-	HID_PUBLISH_INPUT_REPORT,
-	HID_PUBLISH_INPUT_REPORT_LIST, /* TODO: need to support batch report */
-
-	HID_HID_CLIENT_READY_CMD = 30,
-	HID_HID_COMMAND_MAX = 31,
-
-	HID_DM_COMMAND_BASE,
-	HID_DM_ENUM_DEVICES,
-	HID_DM_ADD_DEVICE,
-	HID_COMMAND_LAST
-};
-
-struct hid_device_info {
-	uint32_t dev_id;
-	uint8_t dev_class;
-	uint16_t pid;
-	uint16_t vid;
-} __packed;
-
-struct hid_enum_payload	{
-	uint8_t num_of_hid_devices;
-	struct hid_device_info dev_info[0];
-} __packed;
-
-#define COMMAND_MASK			0x7F
-#define RESPONSE_FLAG			0x80
-struct hid_msg_hdr {
-	uint8_t command; /* bit 7 is used to indicate "response" */
-	uint8_t device_id;
-	uint8_t status;
-	uint8_t flags;
-	uint16_t size;
-} __packed;
-
-struct hid_msg {
-	struct hid_msg_hdr hdr;
-	uint8_t payload[HID_SUBSYS_MAX_PAYLOAD_SIZE];
-} __packed;
-
-struct hid_subsys_hid_device {
-	struct hid_device_info info;
-	const struct hid_callbacks *cbs;
-	int can_send_hid_input;
-
-	void *data;
-};
-
-struct hid_subsystem {
-	heci_handle_t heci_handle;
-
-	uint32_t num_of_hid_devices;
-	struct hid_subsys_hid_device hid_devices[HID_SUBSYS_MAX_HID_DEVICES];
-};
-
-static struct hid_subsystem hid_subsys_ctx = {
-	.heci_handle = HECI_INVALID_HANDLE,
-};
-
-#define handle_to_dev_id(_handle)	((uintptr_t)(_handle))
-#define dev_id_to_handle(_dev_id)	((hid_handle_t)(uintptr_t)(_dev_id))
-
-static inline hid_handle_t device_index_to_handle(int device_index)
-{
-	return (hid_handle_t)(uintptr_t)(device_index + 1);
-}
-
-static inline int is_valid_handle(hid_handle_t handle)
-{
-	return (uintptr_t)handle > 0 &&
-	       (uintptr_t)handle <= hid_subsys_ctx.num_of_hid_devices;
-}
-
-static inline
-struct hid_subsys_hid_device *handle_to_hid_device(hid_handle_t handle)
-{
-	if (!is_valid_handle(handle))
-		return NULL;
-
-	return &hid_subsys_ctx.hid_devices[(uintptr_t)handle - 1];
-}
-
-
-hid_handle_t hid_subsys_register_device(const struct hid_device *dev_info)
-{
-	struct hid_subsys_hid_device *hid_device;
-	hid_handle_t handle;
-	int ret, hid_device_index;
-
-	if (hid_subsys_ctx.num_of_hid_devices >= HID_SUBSYS_MAX_HID_DEVICES)
-		return HID_INVALID_HANDLE;
-
-	hid_device_index = hid_subsys_ctx.num_of_hid_devices++;
-
-	handle = device_index_to_handle(hid_device_index);
-
-	hid_device = &hid_subsys_ctx.hid_devices[hid_device_index];
-
-	hid_device->info.dev_class = dev_info->dev_class;
-	hid_device->info.pid = dev_info->pid;
-	hid_device->info.vid = dev_info->vid;
-	hid_device->info.dev_id = handle_to_dev_id(handle);
-
-	hid_device->cbs = dev_info->cbs;
-
-	if (dev_info->cbs->initialize) {
-		ret = dev_info->cbs->initialize(handle);
-		if (ret) {
-			CPRINTF("initialize error %d\n", ret);
-			hid_subsys_ctx.num_of_hid_devices--;
-			return HID_INVALID_HANDLE;
-		}
-	}
-
-	return handle;
-}
-
-int hid_subsys_send_input_report(const hid_handle_t handle, uint8_t *buf,
-				 const size_t buf_size)
-{
-	struct hid_subsys_hid_device *hid_device;
-	struct hid_msg_hdr hid_msg_hdr = {0};
-	struct heci_msg_item msg_item[2];
-	struct heci_msg_list msg_list;
-
-	hid_device = handle_to_hid_device(handle);
-	if (!hid_device)
-		return -EC_ERROR_INVAL;
-
-	if (buf_size > HID_SUBSYS_MAX_PAYLOAD_SIZE)
-		return -EC_ERROR_OVERFLOW;
-
-	if (hid_subsys_ctx.heci_handle == HECI_INVALID_HANDLE)
-		return -HID_SUBSYS_ERR_NOT_READY;
-
-	if (!hid_device->can_send_hid_input)
-		return -HID_SUBSYS_ERR_NOT_READY;
-
-	hid_msg_hdr.command = HID_PUBLISH_INPUT_REPORT;
-	hid_msg_hdr.device_id = hid_device->info.dev_id;
-	hid_msg_hdr.size = buf_size;
-
-	msg_item[0].size = sizeof(hid_msg_hdr);
-	msg_item[0].buf = (uint8_t *)&hid_msg_hdr;
-
-	msg_item[1].size = buf_size;
-	msg_item[1].buf = buf;
-
-	msg_list.num_of_items = 2;
-	msg_list.items[0] = &msg_item[0];
-	msg_list.items[1] = &msg_item[1];
-
-	heci_send_msgs(hid_subsys_ctx.heci_handle, &msg_list);
-
-	return 0;
-}
-
-int hid_subsys_set_device_data(const hid_handle_t handle, void *data)
-{
-	struct hid_subsys_hid_device *hid_device;
-
-	hid_device = handle_to_hid_device(handle);
-	if (!hid_device)
-		return -EC_ERROR_INVAL;
-
-	hid_device->data = data;
-
-	return 0;
-}
-
-void *hid_subsys_get_device_data(const hid_handle_t handle)
-{
-	struct hid_subsys_hid_device *hid_device;
-
-	hid_device = handle_to_hid_device(handle);
-	if (!hid_device)
-		return NULL;
-
-	return hid_device->data;
-}
-
-static int handle_hid_device_msg(struct hid_msg *hid_msg)
-{
-	int ret = 0, payload_size, buf_size;
-	uint8_t *payload;
-	struct hid_subsys_hid_device *hid_dev;
-	const struct hid_callbacks *cbs;
-	hid_handle_t handle;
-
-	handle = dev_id_to_handle(hid_msg->hdr.device_id);
-	hid_dev = handle_to_hid_device(handle);
-
-	if (!hid_dev) {
-		/*
-		 * use HID_HID_COMMAND_MAX as error message.
-		 * host driver will reset ISH.
-		 */
-		hid_msg->hdr.size = 0;
-		hid_msg->hdr.status = 0;
-		hid_msg->hdr.command |= RESPONSE_FLAG | HID_HID_COMMAND_MAX;
-		hid_msg->hdr.flags = 0;
-
-		heci_send_msg(hid_subsys_ctx.heci_handle, (uint8_t *)hid_msg,
-			      sizeof(hid_msg->hdr));
-
-		return 0;
-	}
-
-	cbs = hid_dev->cbs;
-
-	payload = hid_msg->payload;
-	payload_size = hid_msg->hdr.size; /* input data */
-	buf_size = sizeof(hid_msg->payload); /* buffer to be written by cb */
-
-	/*
-	 * re-use hid_msg from host for reply.
-	 */
-	switch (hid_msg->hdr.command & COMMAND_MASK) {
-	case  HID_GET_HID_DESCRIPTOR:
-		if (cbs->get_hid_descriptor)
-			ret = cbs->get_hid_descriptor(handle, payload,
-						      buf_size);
-
-		break;
-	case HID_GET_REPORT_DESCRIPTOR:
-		if (cbs->get_report_descriptor)
-			ret = cbs->get_report_descriptor(handle, payload,
-							 buf_size);
-
-		hid_dev->can_send_hid_input = 1;
-
-		break;
-
-	case HID_GET_FEATURE_REPORT:
-		if (cbs->get_feature_report)
-			ret = cbs->get_feature_report(handle, payload[0],
-						      payload, buf_size);
-
-		break;
-
-	case HID_SET_FEATURE_REPORT:
-		if (cbs->set_feature_report) {
-			ret = cbs->set_feature_report(handle,
-						      payload[0],
-						      payload,
-						      payload_size);
-			/*
-			 * if no error, reply only with the report id.
-			 * re-use the first byte of payload
-			 * from host that has report id
-			 */
-			if (ret >= 0)
-				ret = sizeof(uint8_t);
-		}
-
-		break;
-	case HID_GET_INPUT_REPORT:
-		if (cbs->get_input_report)
-			ret = cbs->get_input_report(handle, payload[0],
-						    payload, buf_size);
-
-		break;
-
-	default:
-		CPRINTF("invalid hid command %d, ignoring request\n",
-			hid_msg->hdr.command & COMMAND_MASK);
-		ret = -1; /* send error */
-	}
-
-	if (ret > 0) {
-		hid_msg->hdr.size = ret;
-		hid_msg->hdr.status = 0;
-	} else { /* error in callback */
-		/*
-		 * Note : errors of HID device should be transferred
-		 * through their HID formatted data.
-		 */
-		hid_msg->hdr.size = 0;
-		hid_msg->hdr.status = -ret;
-	}
-
-	hid_msg->hdr.command |= RESPONSE_FLAG;
-	hid_msg->hdr.flags = 0;
-
-	heci_send_msg(hid_subsys_ctx.heci_handle, (uint8_t *)hid_msg,
-		      sizeof(hid_msg->hdr) + hid_msg->hdr.size);
-
-	return 0;
-}
-
-static int handle_hid_subsys_msg(struct hid_msg *hid_msg)
-{
-	int size = 0, i;
-	struct hid_enum_payload *enum_payload;
-
-	switch (hid_msg->hdr.command & COMMAND_MASK) {
-	case  HID_DM_ENUM_DEVICES:
-		enum_payload = (struct hid_enum_payload *)hid_msg->payload;
-
-		for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) {
-			enum_payload->dev_info[i] =
-					hid_subsys_ctx.hid_devices[i].info;
-		}
-
-		enum_payload->num_of_hid_devices =
-					hid_subsys_ctx.num_of_hid_devices;
-
-		/* reply payload size */
-		size = sizeof(enum_payload->num_of_hid_devices);
-		size += enum_payload->num_of_hid_devices *
-					sizeof(enum_payload->dev_info[0]);
-
-		break;
-
-	default:
-		CPRINTF("invalid hid command %d, ignoring request\n",
-			hid_msg->hdr.command & COMMAND_MASK);
-		size = -1; /* send error */
-	}
-
-	if (size > 0) {
-		hid_msg->hdr.size = size;
-		hid_msg->hdr.status = 0;
-	} else { /* error in callback */
-		hid_msg->hdr.size = 0;
-		hid_msg->hdr.status = -size;
-	}
-
-	hid_msg->hdr.command |= RESPONSE_FLAG;
-	hid_msg->hdr.flags = 0;
-
-	heci_send_msg(hid_subsys_ctx.heci_handle, (uint8_t *)hid_msg,
-		      sizeof(hid_msg->hdr) + hid_msg->hdr.size);
-
-	return 0;
-}
-
-static void hid_subsys_new_msg_received(const heci_handle_t handle,
-					uint8_t *msg, const size_t msg_size)
-{
-	struct hid_msg *hid_msg = (struct hid_msg *)msg;
-
-	/* workaround, since Host driver doesn't set size properly */
-	if (hid_msg->hdr.size == 0 && msg_size > sizeof(hid_msg->hdr))
-		hid_msg->hdr.size = msg_size - sizeof(hid_msg->hdr);
-
-	if (hid_msg->hdr.size > HID_SUBSYS_MAX_PAYLOAD_SIZE) {
-		CPRINTF("too big payload size : %d. discard heci msg\n",
-			hid_msg->hdr);
-		return; /* invalid hdr. discard */
-	}
-
-	if (hid_msg->hdr.device_id)
-		handle_hid_device_msg(hid_msg);
-	else
-		handle_hid_subsys_msg(hid_msg);
-}
-
-static int hid_subsys_initialize(const heci_handle_t heci_handle)
-{
-	hid_subsys_ctx.heci_handle = heci_handle;
-
-	return 0;
-}
-
-/* return zero if resume request handled successfully */
-static int hid_subsys_resume(const heci_handle_t heci_handle)
-{
-	int i, ret = 0;
-
-	for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) {
-		if (hid_subsys_ctx.hid_devices[i].cbs->resume)
-			ret |= hid_subsys_ctx.hid_devices[i].cbs->resume(
-					device_index_to_handle(i));
-	}
-
-	return ret;
-}
-
-/* return zero if suspend request handled successfully */
-static int hid_subsys_suspend(const heci_handle_t heci_handle)
-{
-	int i, ret = 0;
-
-	for (i = hid_subsys_ctx.num_of_hid_devices - 1; i >= 0; i--) {
-		if (hid_subsys_ctx.hid_devices[i].cbs->suspend)
-			ret |= hid_subsys_ctx.hid_devices[i].cbs->suspend(
-					device_index_to_handle(i));
-	}
-
-	return ret;
-}
-
-static const struct heci_client_callbacks hid_subsys_heci_cbs = {
-	.initialize = hid_subsys_initialize,
-	.new_msg_received = hid_subsys_new_msg_received,
-	.suspend = hid_subsys_suspend,
-	.resume = hid_subsys_resume,
-};
-
-static const struct heci_client hid_subsys_heci_client = {
-	.protocol_id = HECI_CLIENT_HID_GUID,
-	.max_msg_size = HECI_MAX_MSG_SIZE,
-	.protocol_ver = 1,
-	.max_n_of_connections = 1,
-
-	.cbs = &hid_subsys_heci_cbs,
-};
-
-HECI_CLIENT_ENTRY(hid_subsys_heci_client);
diff --git a/chip/ish/host_command_heci.c b/chip/ish/host_command_heci.c
deleted file mode 100644
index 2fcab44b8b..0000000000
--- a/chip/ish/host_command_heci.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "heci_client.h"
-#include "host_command.h"
-#include "host_command_heci.h"
-#include "ipc_heci.h"
-#include "ish_fwst.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-
-#define HECI_CLIENT_CROS_EC_ISH_GUID { 0x7b7154d0, 0x56f4, 0x4bdc,\
-			 { 0xb0, 0xd8, 0x9e, 0x7c, 0xda, 0xe0, 0xd6, 0xa0 } }
-
-/* Handle for all heci cros_ec interactions */
-static heci_handle_t heci_cros_ec_handle = HECI_INVALID_HANDLE;
-
-/*
- * If we hit response buffer size issues, we can increase this. This is the
- * current size of a single HECI packet.
- *
- * Aligning with other assumptions in host command stack, only a single host
- * command can be processed at a given time.
- */
-
-struct cros_ec_ishtp_msg_hdr {
-	uint8_t channel;
-	uint8_t status;
-	uint8_t id;	/* Pairs up request and responses */
-	uint8_t reserved;
-} __ec_align4;
-
-#define CROS_EC_ISHTP_MSG_HDR_SIZE sizeof(struct cros_ec_ishtp_msg_hdr)
-#define HECI_CROS_EC_RESPONSE_MAX \
-	(HECI_IPC_PAYLOAD_SIZE - CROS_EC_ISHTP_MSG_HDR_SIZE)
-
-struct cros_ec_ishtp_msg {
-	struct cros_ec_ishtp_msg_hdr hdr;
-	uint8_t data[0];
-} __ec_align4;
-
-enum heci_cros_ec_channel {
-	CROS_EC_COMMAND = 1, /* initiated from AP */
-	CROS_MKBP_EVENT = 2, /* initiated from EC */
-};
-
-static uint8_t response_buffer[IPC_MAX_PAYLOAD_SIZE] __aligned(4);
-static struct host_packet heci_packet;
-
-int heci_send_mkbp_event(uint32_t *timestamp)
-{
-	struct cros_ec_ishtp_msg evt;
-	int rv;
-
-	evt.hdr.channel = CROS_MKBP_EVENT;
-	evt.hdr.status = 0;
-
-	rv = heci_send_msg_timestamp(heci_cros_ec_handle, (uint8_t *)&evt,
-				     sizeof(evt), timestamp);
-	/*
-	 * heci_send_msg_timestamp sends back negative error codes. Change to
-	 * EC style codes
-	 */
-	return rv < 0 ? -rv : EC_SUCCESS;
-}
-
-static void heci_send_hostcmd_response(struct host_packet *pkt)
-{
-	int rv;
-	struct cros_ec_ishtp_msg *out =
-		(struct cros_ec_ishtp_msg *)response_buffer;
-
-	out->hdr.channel = CROS_EC_COMMAND;
-	out->hdr.status = 0;
-	/* id is already set in the receiving method */
-
-	rv = heci_send_msg(heci_cros_ec_handle, (uint8_t *)out,
-			   pkt->response_size + CROS_EC_ISHTP_MSG_HDR_SIZE);
-	if (rv < 0)
-		CPRINTS("HC response failed %d", -rv);
-}
-
-static void cros_ec_ishtp_subsys_new_msg_received(const heci_handle_t handle,
-					uint8_t *msg, const size_t msg_size)
-{
-	struct cros_ec_ishtp_msg *in = (void *) msg;
-	struct cros_ec_ishtp_msg *out = (void *) response_buffer;
-
-	if (in->hdr.channel != CROS_EC_COMMAND) {
-		CPRINTS("Unknown HECI packet 0x%02x", in->hdr.channel);
-		return;
-	}
-	memset(&heci_packet, 0, sizeof(heci_packet));
-
-	/* Copy over id from sender so they can pair up messages */
-	out->hdr.id = in->hdr.id;
-
-	heci_packet.send_response = heci_send_hostcmd_response;
-
-	heci_packet.request = in->data;
-	heci_packet.request_max = HECI_MAX_MSG_SIZE;
-	heci_packet.request_size = msg_size - CROS_EC_ISHTP_MSG_HDR_SIZE;
-
-	heci_packet.response = out->data;
-	heci_packet.response_max = HECI_CROS_EC_RESPONSE_MAX;
-	heci_packet.response_size = 0;
-
-	heci_packet.driver_result = EC_RES_SUCCESS;
-	host_packet_receive(&heci_packet);
-}
-
-/*
- * IPC transfer max is actual 4K, but we don't need kernel buffers that big
- *
- * Basing size off of existing cros_ec implementations ranging from 128 to 512
- */
-#define HECI_CROS_EC_LIMIT_PACKET_SIZE 256
-
-/**
- * Get protocol information
- */
-static enum ec_status heci_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = HECI_CROS_EC_LIMIT_PACKET_SIZE;
-	r->max_response_packet_size = HECI_CROS_EC_RESPONSE_MAX;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, heci_get_protocol_info,
-EC_VER_MASK(0));
-
-static int cros_ec_ishtp_subsys_initialize(const heci_handle_t heci_handle)
-{
-	heci_cros_ec_handle = heci_handle;
-	ish_fwst_set_fw_status(FWSTS_SENSOR_APP_RUNNING);
-	return EC_SUCCESS;
-}
-
-static int cros_ec_ishtp_no_op(const heci_handle_t heci_handle)
-{
-	return EC_SUCCESS;
-}
-
-static void cros_ec_ishtp_disconneted(const heci_handle_t heci_handle)
-{
-}
-
-static const struct heci_client_callbacks cros_ec_ishtp_subsys_heci_cbs = {
-	.initialize = cros_ec_ishtp_subsys_initialize,
-	.new_msg_received = cros_ec_ishtp_subsys_new_msg_received,
-	.suspend = cros_ec_ishtp_no_op,
-	.resume = cros_ec_ishtp_no_op,
-	.disconnected = cros_ec_ishtp_disconneted,
-};
-
-static const struct heci_client cros_ec_ishtp_heci_client = {
-	.protocol_id = HECI_CLIENT_CROS_EC_ISH_GUID,
-	.max_msg_size = HECI_MAX_MSG_SIZE,
-	.protocol_ver = 1,
-	.max_n_of_connections = 1,
-	.cbs = &cros_ec_ishtp_subsys_heci_cbs,
-};
-
-HECI_CLIENT_ENTRY(cros_ec_ishtp_heci_client);
diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h
deleted file mode 100644
index 06738fafb1..0000000000
--- a/chip/ish/hpet.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_HPET_H
-#define __CROS_EC_HPET_H
-
-#include "common.h"
-
-/* ISH HPET config and timer registers */
-
-#define TIMER0_CONF_CAP_REG		0x100
-#define TIMER0_COMP_VAL_REG		0x108
-
-
-/* HPET_GENERAL_CONFIG settings  */
-#define HPET_GENERAL_CONFIG		REG32(ISH_HPET_BASE + 0x10)
-#define HPET_ENABLE_CNF		BIT(0)
-#define HPET_LEGACY_RT_CNF	BIT(1)
-
-/* Interrupt status acknowledge register */
-#define HPET_INTR_CLEAR		REG32(ISH_HPET_BASE + 0x20)
-
-/* Main counter register. 64-bit */
-#define HPET_MAIN_COUNTER_64	REG64(ISH_HPET_BASE + 0xF0)
-#define HPET_MAIN_COUNTER_64_LO	REG32(ISH_HPET_BASE + 0xF0)
-#define HPET_MAIN_COUNTER_64_HI	REG32(ISH_HPET_BASE + 0xF4)
-
-/* HPET Timer 0/1/2 configuration*/
-#define HPET_TIMER_CONF_CAP(x)	REG32(ISH_HPET_BASE + 0x100 + ((x) * 0x20))
-#define HPET_Tn_INT_TYPE_CNF		BIT(1)
-#define HPET_Tn_INT_ENB_CNF		BIT(2)
-#define HPET_Tn_TYPE_CNF		BIT(3)
-#define HPET_Tn_VAL_SET_CNF		BIT(6)
-#define HPET_Tn_32MODE_CNF		BIT(8)
-#define HPET_Tn_INT_ROUTE_CNF_SHIFT	0x9
-#define HPET_Tn_INT_ROUTE_CNF_MASK	(0x1f << 9)
-
-/*
- * HPET Timer 0/1/2 comparator values. 1/2 are always 32-bit. 0 can be
- * configured as 64-bit.
- */
-#define HPET_TIMER_COMP(x)	REG32(ISH_HPET_BASE + 0x108 + ((x) * 0x20))
-#define HPET_TIMER0_COMP_64	REG64(ISH_HPET_BASE + 0x108)
-
-/* ISH 4/5: Special status register
- * Use this register to see HPET timer are settled after a write.
- */
-#define HPET_CTRL_STATUS		REG32(ISH_HPET_BASE + 0x160)
-#define HPET_INT_STATUS_SETTLING	BIT(1)
-#define HPET_MAIN_COUNTER_SETTLING	(BIT(2) | BIT(3))
-#define HPET_T0_CAP_SETTLING		BIT(4)
-#define HPET_T1_CAP_SETTLING		BIT(5)
-#define HPET_T0_CMP_SETTLING		(BIT(7) | BIT(8))
-#define HPET_T1_CMP_SETTLING		BIT(9)
-#define HPET_MAIN_COUNTER_VALID		BIT(13)
-#define HPET_T1_SETTLING		(HPET_T1_CAP_SETTLING | \
-					 HPET_T1_CMP_SETTLING)
-#define HPET_T0_SETTLING		(HPET_T0_CAP_SETTLING | \
-					 HPET_T0_CMP_SETTLING)
-#define HPET_ANY_SETTLING		(BIT(12) - 1)
-
-#if defined(CHIP_FAMILY_ISH3)
-#define ISH_HPET_CLK_FREQ		12000000	/* 12 MHz clock */
-#elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
-#define ISH_HPET_CLK_FREQ		32768		/* 32.768 KHz clock */
-#endif
-
-#endif /* __CROS_EC_HPET_H */
diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c
deleted file mode 100644
index 1259dae7f4..0000000000
--- a/chip/ish/hwtimer.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver for ISH High Precision Event Timers (HPET) */
-
-#include "console.h"
-#include "hpet.h"
-#include "hwtimer.h"
-#include "timer.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-
-static uint32_t last_deadline;
-
-/*
- * The ISH hardware needs at least 25 ticks of leeway to arms the timer.
- * ISH4/5 are the slowest with 32kHz timers, so we wait at least 800us when
- * scheduling events in the future
- */
-#define MINIMUM_EVENT_DELAY_US 800
-
-/*
- * ISH HPET timer HW has latency for interrupt, on ISH5, this latency is about
- * 3 ticks, defined this configuration to calibrate the 'last_deadline' which is
- * updated in event timer interrupt ISR. Without this calibration, we could
- * get negative sleep time in idle task for low power sleep process.
- */
-#define HPET_INT_LATENCY_TICKS 3
-
-/* Scaling helper methods for different ISH chip variants */
-#ifdef CHIP_FAMILY_ISH3
-#define CLOCK_FACTOR 12
-BUILD_ASSERT(CLOCK_FACTOR * SECOND == ISH_HPET_CLK_FREQ);
-
-static inline uint64_t scale_us2ticks(uint64_t us)
-{
-	return us * CLOCK_FACTOR;
-}
-
-static inline uint32_t scale_us2ticks_32(uint32_t us)
-{
-	/* no optimization for ISH3 */
-	return us * CLOCK_FACTOR;
-}
-
-static inline uint64_t scale_ticks2us(uint64_t ticks)
-{
-	return ticks / CLOCK_FACTOR;
-}
-
-static inline void wait_while_settling(uint32_t mask)
-{
-	/* Do nothing on ISH3, only ISH4 and ISH5 need settling */
-}
-
-#elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
-#define CLOCK_SCALE_BITS 15
-BUILD_ASSERT(BIT(CLOCK_SCALE_BITS) == ISH_HPET_CLK_FREQ);
-
-/* Slow version, for 64-bit precision */
-static inline uint64_t scale_us2ticks(uint64_t us)
-{
-	/* ticks = us * ISH_HPET_CLK_FREQ / SECOND */
-
-	return (us << CLOCK_SCALE_BITS) / SECOND;
-}
-
-/* Fast version, for 32-bit precision */
-static inline uint32_t scale_us2ticks_32(uint32_t us)
-{
-	/*
-	 * GCC optimizes this shift/divide into multiplication by a
-	 * magic number
-	 */
-	return (us << CLOCK_SCALE_BITS) / SECOND;
-}
-
-static inline uint64_t scale_ticks2us(uint64_t ticks)
-{
-	return (ticks * SECOND) >> CLOCK_SCALE_BITS;
-}
-
-/*
- * HPET Control & Status register may indicate that a value which has
- * been written still needs propogated by hardware. Before updating
- * HPET_TIMER_CONF_CAP(N), be sure to wait on the value settling with
- * the corresponding mask (see hpet.h).
- */
-static inline void wait_while_settling(uint32_t mask)
-{
-	/* Wait for timer settings to settle ~ 150us */
-	while (HPET_CTRL_STATUS & mask)
-		continue;
-}
-
-#else
-#error "Must define CHIP_FAMILY_ISH(3|4|5)"
-#endif
-
-/*
- * The 64-bit read on a 32-bit chip can tear during the read. Ensure that the
- * value returned for 64-bit didn't rollover while we were reading it.
- */
-static inline uint64_t read_main_timer(void)
-{
-	timestamp_t t;
-	uint32_t hi;
-
-	/* need check main counter if valid when exit low power TCG mode */
-	wait_while_settling(HPET_MAIN_COUNTER_VALID);
-
-	do {
-		t.le.hi = HPET_MAIN_COUNTER_64_HI;
-		t.le.lo = HPET_MAIN_COUNTER_64_LO;
-		hi = HPET_MAIN_COUNTER_64_HI;
-	} while (t.le.hi != hi);
-
-	return t.val;
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint32_t remaining_us;
-	uint32_t current_us;
-	uint64_t current_ticks;
-
-	/* 'current_ticks' is the current absolute 64bit HW timer counter */
-	current_ticks = read_main_timer();
-
-	/*
-	 * 'current_us' is the low 32bit part of current time in 64bit micro
-	 * seconds format, it's can express 2^32 micro seconds in maximum.
-	 */
-	current_us = scale_ticks2us(current_ticks);
-
-	/*
-	 * To ensure HW has enough time to react to the new timer value,
-	 * we make remaining time not less than 'MINIMUM_EVENT_DELAY_US'
-	 */
-	remaining_us = deadline - current_us;
-	remaining_us = MAX(remaining_us, MINIMUM_EVENT_DELAY_US);
-
-	/*
-	 * Set new 64bit absolute timeout ticks to Timer 1 comparator
-	 * register.
-	 * For ISH3, this assumes that remaining_us is less than 360 seconds
-	 * (2^32 us / 12Mhz), otherwise we would need to handle 32-bit rollover
-	 * of 12Mhz timer comparator value. Watchdog refresh happens at least
-	 * every 10 seconds.
-	 */
-	wait_while_settling(HPET_T1_CMP_SETTLING);
-	HPET_TIMER_COMP(1) = current_ticks + scale_us2ticks_32(remaining_us);
-
-	/*
-	 * Update 'last_deadline' and add calibrate delta due to HPET timer
-	 * interrupt latency.
-	 */
-	last_deadline = current_us + remaining_us;
-	last_deadline += scale_ticks2us(HPET_INT_LATENCY_TICKS);
-
-	/* Enable timer interrupt */
-	wait_while_settling(HPET_T1_SETTLING);
-	HPET_TIMER_CONF_CAP(1) |= HPET_Tn_INT_ENB_CNF;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return last_deadline;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/*
-	 * We need to make sure that process_timers is called when the
-	 * event timer rolls over, set for deadline when
-	 * process_timers clears the event timer.
-	 */
-	__hw_clock_event_set(0xFFFFFFFF);
-}
-
-uint64_t __hw_clock_source_read64(void)
-{
-	return scale_ticks2us(read_main_timer());
-}
-
-void __hw_clock_source_set64(uint64_t timestamp)
-{
-	/* Reset both clock and overflow comparators */
-	wait_while_settling(HPET_ANY_SETTLING);
-	HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
-
-	HPET_MAIN_COUNTER_64 = scale_us2ticks(timestamp);
-
-	wait_while_settling(HPET_ANY_SETTLING);
-	HPET_GENERAL_CONFIG |= HPET_ENABLE_CNF;
-}
-
-static void hw_clock_event_isr(void)
-{
-	/* Clear interrupt */
-	wait_while_settling(HPET_INT_STATUS_SETTLING);
-	HPET_INTR_CLEAR = BIT(1);
-
-	process_timers(0);
-}
-DECLARE_IRQ(ISH_HPET_TIMER1_IRQ, hw_clock_event_isr);
-
-int __hw_clock_source_init64(uint64_t start_t)
-{
-	/*
-	 * Timer 1 is used as an event timer. Timer 0 is unused, as
-	 * CONFIG_HWTIMER_64BIT is enabled.
-	 */
-	uint32_t timer1_config = 0x00000000;
-
-	/* Disable HPET */
-	wait_while_settling(HPET_ANY_SETTLING);
-	HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
-
-	/* Disable T0 */
-	HPET_TIMER_CONF_CAP(0) &= ~HPET_Tn_INT_ENB_CNF;
-
-	/* Disable T1 until we get it set up (below) */
-	HPET_TIMER_CONF_CAP(1) &= ~HPET_Tn_INT_ENB_CNF;
-
-	/* Initialize main counter */
-	HPET_MAIN_COUNTER_64 = scale_us2ticks(start_t);
-
-	/* Clear any interrupts from previously running image */
-	HPET_INTR_CLEAR = BIT(0);
-	HPET_INTR_CLEAR = BIT(1);
-
-	/* Timer 1 - IRQ routing */
-	timer1_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK;
-	timer1_config |= (ISH_HPET_TIMER1_IRQ <<
-			  HPET_Tn_INT_ROUTE_CNF_SHIFT);
-
-	/* Level triggered interrupt */
-	timer1_config |= HPET_Tn_INT_TYPE_CNF;
-
-	/* Initialize last_deadline until an event is scheduled */
-	last_deadline = 0xFFFFFFFF;
-
-	/* Before enabling, previous values must have settled */
-	wait_while_settling(HPET_ANY_SETTLING);
-
-	/* Unmask HPET IRQ in IOAPIC */
-	task_enable_irq(ISH_HPET_TIMER1_IRQ);
-
-	/* Copy timer config to hardware register */
-	HPET_TIMER_CONF_CAP(1) |= timer1_config;
-
-	/* Enable HPET */
-	HPET_GENERAL_CONFIG |= (HPET_ENABLE_CNF | HPET_LEGACY_RT_CNF);
-
-	/* Return IRQ value for OS event timer */
-	return ISH_HPET_TIMER1_IRQ;
-}
diff --git a/chip/ish/i2c.c b/chip/ish/i2c.c
deleted file mode 100644
index 7e297a20eb..0000000000
--- a/chip/ish/i2c.c
+++ /dev/null
@@ -1,546 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for ISH */
-
-#include "common.h"
-#include "console.h"
-#include "config_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "ish_i2c.h"
-#include "task.h"
-#include "timer.h"
-#include "hwtimer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-
-/*25MHz, 50MHz, 100MHz, 120MHz, 40MHz, 20MHz, 37MHz*/
-static uint16_t default_hcnt_scl_100[] = {
-	4000, 4420, 4920, 4400, 4000, 4000, 4300
-};
-
-static uint16_t default_lcnt_scl_100[] = {
-	4720, 5180, 4990, 5333, 4700, 5200, 4950
-};
-
-static uint16_t default_hcnt_scl_400[] = {
-	600, 820, 1120, 800, 600, 600, 450
-};
-
-static uint16_t default_lcnt_scl_400[] = {
-	1320, 1380, 1300, 1550, 1300, 1200, 1250
-};
-
-static uint16_t default_hcnt_scl_1000[] = {
-	260, 260, 260, 305, 260, 260, 260
-};
-
-static uint16_t default_lcnt_scl_1000[] = {
-	500, 500, 500, 525, 500, 500, 500
-};
-
-static uint16_t default_hcnt_scl_hs[] = { 160, 300, 160, 166, 175, 150, 162 };
-static uint16_t default_lcnt_scl_hs[] = { 320, 340, 320, 325, 325, 300, 297 };
-
-
-#ifdef CHIP_VARIANT_ISH5P4
-/* Change to I2C_FREQ_100 in real silicon platform */
-static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = {
-	I2C_FREQ_100, I2C_FREQ_100, I2C_FREQ_100
-};
-#else
-static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = {
-	I2C_FREQ_120, I2C_FREQ_120, I2C_FREQ_120
-};
-#endif
-
-static struct i2c_context i2c_ctxs[ISH_I2C_PORT_COUNT] = {
-	{
-		.bus = 0,
-		.base = (uint32_t *) ISH_I2C0_BASE,
-		.speed = I2C_SPEED_400KHZ,
-		.int_pin = ISH_I2C0_IRQ,
-	},
-	{
-		.bus = 1,
-		.base = (uint32_t *) ISH_I2C1_BASE,
-		.speed = I2C_SPEED_400KHZ,
-		.int_pin = ISH_I2C1_IRQ,
-	},
-	{
-		.bus = 2,
-		.base = (uint32_t *) ISH_I2C2_BASE,
-		.speed = I2C_SPEED_400KHZ,
-		.int_pin = ISH_I2C2_IRQ,
-	},
-};
-
-static struct i2c_bus_info board_config[ISH_I2C_PORT_COUNT] = {
-	{
-		.bus_id = 0,
-		.std_speed.sda_hold = DEFAULT_SDA_HOLD_STD,
-		.fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST,
-		.fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS,
-		.high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH,
-	},
-	{
-		.bus_id = 1,
-		.std_speed.sda_hold = DEFAULT_SDA_HOLD_STD,
-		.fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST,
-		.fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS,
-		.high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH,
-	},
-	{
-		.bus_id = 2,
-		.std_speed.sda_hold = DEFAULT_SDA_HOLD_STD,
-		.fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST,
-		.fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS,
-		.high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH,
-	 },
-};
-
-static inline void i2c_mmio_write(uint32_t *base, uint8_t offset,
-				  uint32_t data)
-{
-	REG32((uint32_t) ((uint8_t *)base + offset)) = data;
-}
-
-static inline uint32_t i2c_mmio_read(uint32_t *base, uint8_t offset)
-{
-	return REG32((uint32_t) ((uint8_t *)base + offset));
-}
-
-static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg,
-					  uint8_t offset)
-{
-	uint32_t ret = i2c_mmio_read(addr, reg) >> offset;
-
-	return ret & 0xff;
-}
-
-static void i2c_intr_switch(uint32_t *base, int mode)
-{
-	switch (mode) {
-
-	case ENABLE_WRITE_INT:
-		i2c_mmio_write(base, IC_INTR_MASK, IC_INTR_WRITE_MASK_VAL);
-		break;
-
-	case ENABLE_READ_INT:
-		i2c_mmio_write(base, IC_INTR_MASK, IC_INTR_READ_MASK_VAL);
-		break;
-
-	case DISABLE_INT:
-		i2c_mmio_write(base, IC_INTR_MASK, 0);
-		/* clear interrupts: TX_ABORT
-		 * Because the DW_apb_i2c's TX FIFO is forced into a
-		 * flushed/reset state whenever a TX_ABRT event occurs, it
-		 * is necessary for software to release the DW_apb_i2c from
-		 * this state by reading the IC_CLR_TX_ABRT register before
-		 * attempting to write into the TX FIFO
-		 */
-		i2c_mmio_read(base, IC_CLR_TX_ABRT);
-		/* STOP_DET */
-		i2c_mmio_read(base, IC_CLR_STOP_DET);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void i2c_init_transaction(struct i2c_context *ctx,
-				 uint16_t slave_addr, uint8_t flags)
-{
-	uint32_t con_value;
-	uint32_t *base = ctx->base;
-	struct i2c_bus_info *bus_info = &board_config[ctx->bus];
-	uint32_t clk_in_val = clk_in[bus_freq[ctx->bus]];
-
-	/* disable interrupts */
-	i2c_intr_switch(base, DISABLE_INT);
-
-	i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE);
-	i2c_mmio_write(base, IC_TAR, (slave_addr << IC_TAR_OFFSET) |
-			TAR_SPECIAL_VAL | IC_10BITADDR_MASTER_VAL);
-
-	/* set Clock SCL Count */
-	switch (ctx->speed) {
-
-	case I2C_SPEED_100KHZ:
-		i2c_mmio_write(base, IC_SS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->std_speed.hcnt,
-					     clk_in_val));
-		i2c_mmio_write(base, IC_SS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->std_speed.lcnt,
-					     clk_in_val));
-		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->std_speed.sda_hold,
-					     clk_in_val));
-		break;
-
-	case I2C_SPEED_400KHZ:
-		i2c_mmio_write(base, IC_FS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.hcnt,
-					     clk_in_val));
-		i2c_mmio_write(base, IC_FS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.lcnt,
-					     clk_in_val));
-		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->fast_speed.sda_hold,
-					     clk_in_val));
-		break;
-
-	case I2C_SPEED_1MHZ:
-		i2c_mmio_write(base, IC_FS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt,
-					     clk_in_val));
-		i2c_mmio_write(base, IC_FS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt,
-					     clk_in_val));
-		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold,
-					     clk_in_val));
-		break;
-
-	case I2C_SPEED_3M4HZ:
-		i2c_mmio_write(base, IC_HS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->high_speed.hcnt,
-					     clk_in_val));
-		i2c_mmio_write(base, IC_HS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->high_speed.lcnt,
-					     clk_in_val));
-		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->high_speed.sda_hold,
-					     clk_in_val));
-
-		i2c_mmio_write(base, IC_FS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.hcnt,
-					     clk_in_val));
-		i2c_mmio_write(base, IC_FS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.lcnt,
-					     clk_in_val));
-		break;
-
-	default:
-		break;
-	}
-
-	/* in SPT HW we need to sync between I2C clock and data signals */
-	con_value = i2c_mmio_read(base, IC_CON);
-
-	if (flags != 0)
-		con_value |= IC_RESTART_EN_VAL;
-	else
-		con_value &= ~IC_RESTART_EN_VAL;
-
-	i2c_mmio_write(base, IC_CON, con_value);
-	i2c_mmio_write(base, IC_FS_SPKLEN, spkln[bus_freq[ctx->bus]]);
-	i2c_mmio_write(base, IC_HS_SPKLEN, spkln[bus_freq[ctx->bus]]);
-	i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_ENABLE);
-}
-
-static void i2c_write_buffer(uint32_t *base, uint8_t len,
-			     const uint8_t *buffer, ssize_t *cur_index,
-			     ssize_t total_len)
-{
-	int i;
-	uint16_t out;
-
-	for (i = 0; i < len; i++) {
-
-		++(*cur_index);
-		out = (buffer[i] << DATA_CMD_DAT_OFFSET) | DATA_CMD_WRITE_VAL;
-
-		/* if Write ONLY and Last byte */
-		if (*cur_index == total_len) {
-			out |= DATA_CMD_STOP_VAL;
-		}
-
-		i2c_mmio_write(base, IC_DATA_CMD, out);
-	}
-}
-
-static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data,
-					unsigned restart_flag)
-{
-	/* this routine just set RX FIFO's control bit(s),
-	 * READ command or RESTART */
-	int i;
-	uint32_t data_cmd;
-
-	for (i = 0; i < len; i++) {
-		data_cmd = DATA_CMD_READ_VAL;
-
-		if ((i == 0) && restart_flag)
-			/* if restart for first byte */
-			data_cmd |= DATA_CMD_RESTART_VAL;
-
-		/* if last byte & less than FIFO size
-		 * or only one byte to read */
-		if (i == (len - 1) && !more_data)
-			data_cmd |= DATA_CMD_STOP_VAL;
-
-		i2c_mmio_write(base, IC_DATA_CMD, data_cmd);
-	}
-}
-
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	int i;
-	ssize_t total_len;
-	uint64_t expire_ts;
-	struct i2c_context *ctx;
-	ssize_t curr_index = 0;
-	uint16_t addr = I2C_GET_ADDR(slave_addr_flags);
-	int begin_indx;
-	uint8_t repeat_start = 0;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	if (port < 0 || port >= ISH_I2C_PORT_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Check for reserved I2C addresses, pg. 74 in DW_apb_i2c.pdf
-	 * Address cannot be any of the reserved address locations
-	 */
-	if (addr < I2C_FIRST_VALID_ADDR || addr > I2C_LAST_VALID_ADDR)
-		return EC_ERROR_INVAL;
-
-	/* assume that if both out_size and in_size are not zero,
-	 * then, it is 'repeated Start' condition. */
-	if (in_size != 0 && out_size != 0)
-		repeat_start = 1;
-
-	ctx = &i2c_ctxs[port];
-	ctx->error_flag = 0;
-	ctx->wait_task_id = task_get_current();
-
-	total_len = in_size + out_size;
-
-	i2c_init_transaction(ctx, addr, repeat_start);
-
-	/* Write W data */
-	if (out_size)
-		i2c_write_buffer(ctx->base, out_size, out,
-				&curr_index, total_len);
-
-	/* Wait here until Tx is completed so that FIFO becomes empty.
-	 * This is optimized for smaller Tx data size.
-	 * If need to write big data ( > ISH_I2C_FIFO_SIZE ),
-	 * it is better to use Tx FIFO threshold interrupt(as in Rx) for
-	 * better CPU usuage.
-	 * */
-	expire_ts = __hw_clock_source_read() + I2C_TX_FLUSH_TIMEOUT_USEC;
-	if (in_size > (ISH_I2C_FIFO_SIZE - out_size)) {
-
-		while ((i2c_mmio_read(ctx->base, IC_STATUS) &
-			BIT(IC_STATUS_TFE)) == 0) {
-
-			if (__hw_clock_source_read() >= expire_ts) {
-				ctx->error_flag = 1;
-				break;
-			}
-			CPU_RELAX();
-		}
-	}
-
-	begin_indx = 0;
-	while (in_size) {
-		int rd_size;  /* read size for on i2c transaction */
-
-		/*
-		 * check if in_size > ISH_I2C_FIFO_SIZE, then try to read
-		 * FIFO_SIZE each time.
-		 */
-		if (in_size > ISH_I2C_FIFO_SIZE) {
-			rd_size = ISH_I2C_FIFO_SIZE;
-			in_size -= ISH_I2C_FIFO_SIZE;
-		} else {
-			rd_size = in_size;
-			in_size = 0;
-		}
-		/* Set rx_threshold */
-		i2c_mmio_write(ctx->base, IC_RX_TL, rd_size - 1);
-
-		i2c_intr_switch(ctx->base, ENABLE_READ_INT);
-
-		/*
-		 * RESTART only once for entire i2c transaction.
-		 * assume that if both out_size and in_size are not zero,
-		 * then, it is 'repeated Start' condition.
-		 * set R commands bit, start to read
-		 */
-		i2c_write_read_commands(ctx->base, rd_size, in_size,
-				(begin_indx == 0) && (repeat_start != 0));
-
-
-		/* need timeout in case no ACK from slave */
-		task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2*MSEC);
-
-		if (ctx->interrupts & M_TX_ABRT) {
-			ctx->error_flag = 1;
-			break; /* when bus abort, no more reading !*/
-		}
-
-		/* read data */
-		for (i = begin_indx; i < begin_indx + rd_size; i++)
-			in[i] = i2c_read_byte(ctx->base,
-					IC_DATA_CMD, 0);
-
-		begin_indx += rd_size;
-	} /* while (in_size) */
-
-	ctx->reason = 0;
-	ctx->interrupts = 0;
-
-	/* do not disable device before master is idle */
-	expire_ts = __hw_clock_source_read() + I2C_TSC_TIMEOUT;
-
-	while ((i2c_mmio_read(ctx->base, IC_STATUS) &
-		(BIT(IC_STATUS_MASTER_ACTIVITY) | BIT(IC_STATUS_TFE))) !=
-	       BIT(IC_STATUS_TFE)) {
-
-		if (__hw_clock_source_read() >= expire_ts) {
-			ctx->error_flag = 1;
-			break;
-		}
-	}
-
-	i2c_intr_switch(ctx->base, DISABLE_INT);
-	i2c_mmio_write(ctx->base, IC_ENABLE, IC_ENABLE_DISABLE);
-
-	if (ctx->error_flag)
-		return EC_ERROR_INVAL;
-
-	return EC_SUCCESS;
-}
-
-static void i2c_interrupt_handler(struct i2c_context *ctx)
-{
-	uint32_t raw_intr;
-
-	if (IS_ENABLED(INTR_DEBUG))
-		raw_intr = 0x0000FFFF & i2c_mmio_read(ctx->base,
-						      IC_RAW_INTR_STAT);
-
-	/* check interrupts */
-	ctx->interrupts = i2c_mmio_read(ctx->base, IC_INTR_STAT);
-	ctx->reason = (uint16_t) i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE);
-
-	if (IS_ENABLED(INTR_DEBUG))
-		CPRINTS("INTR_STAT = 0x%04x, TX_ABORT_SRC = 0x%04x, "
-			"RAW_INTR_STAT = 0x%04x",
-			ctx->interrupts, ctx->reason, raw_intr);
-
-	/* disable interrupts */
-	i2c_intr_switch(ctx->base, DISABLE_INT);
-	task_set_event(ctx->wait_task_id, TASK_EVENT_I2C_IDLE, 0);
-}
-
-static void i2c_isr_bus0(void)
-{
-	i2c_interrupt_handler(&i2c_ctxs[0]);
-}
-DECLARE_IRQ(ISH_I2C0_IRQ, i2c_isr_bus0);
-
-static void i2c_isr_bus1(void)
-{
-	i2c_interrupt_handler(&i2c_ctxs[1]);
-}
-DECLARE_IRQ(ISH_I2C1_IRQ, i2c_isr_bus1);
-
-static void i2c_isr_bus2(void)
-{
-	i2c_interrupt_handler(&i2c_ctxs[2]);
-}
-DECLARE_IRQ(ISH_I2C2_IRQ, i2c_isr_bus2);
-
-static void  i2c_config_speed(struct i2c_context *ctx, int kbps)
-{
-
-	if (kbps > 1000)
-		ctx->speed = I2C_SPEED_3M4HZ;
-	else if (kbps > 400)
-		ctx->speed = I2C_SPEED_1MHZ;
-	else if (kbps > 100)
-		ctx->speed = I2C_SPEED_400KHZ;
-	else
-		ctx->speed = I2C_SPEED_100KHZ;
-
-}
-
-static void i2c_init_hardware(struct i2c_context *ctx)
-{
-	static const uint8_t speed_val_arr[] = {
-		[I2C_SPEED_100KHZ] = STD_SPEED_VAL,
-		[I2C_SPEED_400KHZ] = FAST_SPEED_VAL,
-		[I2C_SPEED_1MHZ]   = FAST_SPEED_VAL,
-		[I2C_SPEED_3M4HZ]  = HIGH_SPEED_VAL,
-	};
-
-	uint32_t *base = ctx->base;
-
-	/* disable interrupts */
-	i2c_intr_switch(base, DISABLE_INT);
-	i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE);
-	i2c_mmio_write(base, IC_CON, (MASTER_MODE_VAL
-				| speed_val_arr[ctx->speed]
-				| IC_RESTART_EN_VAL
-				| IC_SLAVE_DISABLE_VAL));
-
-	i2c_mmio_write(base, IC_FS_SPKLEN, spkln[bus_freq[ctx->bus]]);
-	i2c_mmio_write(base, IC_HS_SPKLEN, spkln[bus_freq[ctx->bus]]);
-
-	/* get RX_FIFO and TX_FIFO depth */
-	ctx->max_rx_depth = i2c_read_byte(base, IC_COMP_PARAM_1,
-					RX_BUFFER_DEPTH_OFFSET) + 1;
-	ctx->max_tx_depth = i2c_read_byte(base, IC_COMP_PARAM_1,
-					TX_BUFFER_DEPTH_OFFSET) + 1;
-}
-
-static void i2c_initial_board_config(struct i2c_context *ctx)
-{
-	uint8_t freq = bus_freq[ctx->bus];
-	struct i2c_bus_info *bus_info = &board_config[ctx->bus];
-
-	bus_info->std_speed.hcnt = default_hcnt_scl_100[freq];
-	bus_info->std_speed.lcnt = default_lcnt_scl_100[freq];
-
-	bus_info->fast_speed.hcnt = default_hcnt_scl_400[freq];
-	bus_info->fast_speed.lcnt = default_lcnt_scl_400[freq];
-
-	bus_info->fast_plus_speed.hcnt = default_hcnt_scl_1000[freq];
-	bus_info->fast_plus_speed.lcnt = default_lcnt_scl_1000[freq];
-
-	bus_info->high_speed.hcnt = default_hcnt_scl_hs[freq];
-	bus_info->high_speed.lcnt = default_lcnt_scl_hs[freq];
-}
-
-void i2c_init(void)
-{
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++) {
-		int port = i2c_ports[i].port;
-		i2c_initial_board_config(&i2c_ctxs[port]);
-		/* Config speed from i2c_ports[] defined in board.c */
-		i2c_config_speed(&i2c_ctxs[port], i2c_ports[i].kbps);
-		i2c_init_hardware(&i2c_ctxs[port]);
-
-		task_enable_irq((&i2c_ctxs[port])->int_pin);
-	}
-
-	CPRINTS("Done i2c_init");
-}
diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c
deleted file mode 100644
index 5271aa3a91..0000000000
--- a/chip/ish/ipc_heci.c
+++ /dev/null
@@ -1,743 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IPC module for ISH */
-
-/**
- * IPC - Inter Processor Communication
- * -----------------------------------
- *
- * IPC is a bi-directional doorbell based message passing interface sans
- * session and transport layers, between hardware blocks. ISH uses IPC to
- * communicate with the Host, PMC (Power Management Controller), CSME
- * (Converged Security and Manageability Engine), Audio, Graphics and ISP.
- *
- * Both the initiator and target ends each have a 32-bit doorbell register and
- * 128-byte message regions. In addition, the following register pairs help in
- * synchronizing IPC.
- *
- *  - Peripheral Interrupt Status Register (PISR)
- *  - Peripheral Interrupt Mask Register (PIMR)
- *  - Doorbell Clear Status Register (DB CSR)
- */
-
-#include "registers.h"
-#include "console.h"
-#include "task.h"
-#include "util.h"
-#include "ipc_heci.h"
-#include "ish_fwst.h"
-#include "queue.h"
-#include "hooks.h"
-#include "hwtimer.h"
-
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-
-/*
- * comminucation protocol is defined in Linux Documentation
- * <kernel_root>/Documentation/hid/intel-ish-hid.txt
- */
-
-/* MNG commands */
-/* The ipc_mng_task manages IPC link. It should be the highest priority */
-#define MNG_RX_CMPL_ENABLE              0
-#define MNG_RX_CMPL_DISABLE             1
-#define MNG_RX_CMPL_INDICATION          2
-#define MNG_RESET_NOTIFY                3
-#define MNG_RESET_NOTIFY_ACK            4
-#define MNG_SYNC_FW_CLOCK               5
-#define MNG_ILLEGAL_CMD                 0xFF
-
-/* Doorbell */
-#define IPC_DB_MSG_LENGTH_FIELD		0x3FF
-#define IPC_DB_MSG_LENGTH_SHIFT		0
-#define IPC_DB_MSG_LENGTH_MASK \
-	  (IPC_DB_MSG_LENGTH_FIELD << IPC_DB_MSG_LENGTH_SHIFT)
-
-#define IPC_DB_PROTOCOL_FIELD		0x0F
-#define IPC_DB_PROTOCOL_SHIFT		10
-#define IPC_DB_PROTOCOL_MASK (IPC_DB_PROTOCOL_FIELD << IPC_DB_PROTOCOL_SHIFT)
-
-#define IPC_DB_CMD_FIELD		0x0F
-#define IPC_DB_CMD_SHIFT		16
-#define IPC_DB_CMD_MASK			(IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT)
-
-#define IPC_DB_BUSY_SHIFT		31
-#define IPC_DB_BUSY_MASK		BIT(IPC_DB_BUSY_SHIFT)
-
-#define IPC_DB_MSG_LENGTH(drbl) \
-	  (((drbl) & IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT)
-#define IPC_DB_PROTOCOL(drbl) \
-	  (((drbl) & IPC_DB_PROTOCOL_MASK) >> IPC_DB_PROTOCOL_SHIFT)
-#define IPC_DB_CMD(drbl) \
-	  (((drbl) & IPC_DB_CMD_MASK) >> IPC_DB_CMD_SHIFT)
-#define IPC_DB_BUSY(drbl)		(!!((drbl) & IPC_DB_BUSY_MASK))
-
-#define IPC_BUILD_DB(length, proto, cmd, busy) \
-	(((busy) << IPC_DB_BUSY_SHIFT) | ((cmd) << IPC_DB_CMD_SHIFT) | \
-	((proto) << IPC_DB_PROTOCOL_SHIFT) | \
-		((length) << IPC_DB_MSG_LENGTH_SHIFT))
-
-#define IPC_BUILD_MNG_DB(cmd, length) \
-	IPC_BUILD_DB(length, IPC_PROTOCOL_MNG, cmd, 1)
-
-#define IPC_BUILD_HECI_DB(length) \
-	IPC_BUILD_DB(length, IPC_PROTOCOL_HECI, 0, 1)
-
-#define IPC_MSG_MAX_SIZE		0x80
-#define IPC_HOST_MSG_QUEUE_SIZE		8
-#define IPC_PMC_MSG_QUEUE_SIZE		2
-
-#define IPC_HANDLE_PEER_ID_SHIFT	4
-#define IPC_HANDLE_PROTOCOL_SHIFT	0
-#define IPC_HANDLE_PROTOCOL_MASK	0x0F
-#define IPC_BUILD_HANDLE(peer_id, protocol) \
-	((ipc_handle_t)(((peer_id) << IPC_HANDLE_PEER_ID_SHIFT) | (protocol)))
-#define IPC_BUILD_MNG_HANDLE(peer_id) \
-	IPC_BUILD_HANDLE((peer_id), IPC_PROTOCOL_MNG)
-#define IPC_BUILD_HOST_MNG_HANDLE() IPC_BUILD_MNG_HANDLE(IPC_PEER_ID_HOST)
-#define IPC_HANDLE_PEER_ID(handle) \
-	((uint32_t)(handle) >> IPC_HANDLE_PEER_ID_SHIFT)
-#define IPC_HANDLE_PROTOCOL(handle) \
-	((uint32_t)(handle) & IPC_HANDLE_PROTOCOL_MASK)
-#define IPC_IS_VALID_HANDLE(handle) \
-	(IPC_HANDLE_PEER_ID(handle) < IPC_PEERS_COUNT && \
-	    IPC_HANDLE_PROTOCOL(handle) < IPC_PROTOCOL_COUNT)
-
-struct ipc_msg {
-	uint32_t drbl;
-	uint32_t *timestamp_of_outgoing_doorbell;
-	uint8_t payload[IPC_MSG_MAX_SIZE];
-} __packed;
-
-struct ipc_rst_payload {
-	uint16_t reset_id;
-	uint16_t reserved;
-};
-
-struct ipc_oob_msg {
-	uint32_t address;
-	uint32_t length;
-};
-
-struct ipc_msg_event {
-	task_id_t task_id;
-	uint32_t event;
-	uint8_t enabled;
-};
-
-/*
- * IPC interface context
- * This is per-IPC context.
- */
-struct ipc_if_ctx {
-	volatile uint8_t *in_msg_reg;
-	volatile uint8_t *out_msg_reg;
-	volatile uint32_t *in_drbl_reg;
-	volatile uint32_t *out_drbl_reg;
-	uint32_t clr_busy_bit;
-	uint32_t pimr_2ish_bit;
-	uint32_t pimr_2host_clearing_bit;
-	uint8_t irq_in;
-	uint8_t irq_clr;
-	uint16_t reset_id;
-	struct ipc_msg_event msg_events[IPC_PROTOCOL_COUNT];
-	struct mutex lock;
-	struct mutex write_lock;
-
-	struct queue tx_queue;
-	uint8_t is_tx_ipc_busy;
-	uint8_t initialized;
-};
-
-/* list of peer contexts */
-static struct ipc_if_ctx ipc_peer_ctxs[IPC_PEERS_COUNT] = {
-	[IPC_PEER_ID_HOST] = {
-		.in_msg_reg = IPC_HOST2ISH_MSG_BASE,
-		.out_msg_reg = IPC_ISH2HOST_MSG_BASE,
-		.in_drbl_reg = IPC_HOST2ISH_DOORBELL_ADDR,
-		.out_drbl_reg = IPC_ISH2HOST_DOORBELL_ADDR,
-		.clr_busy_bit = IPC_DB_CLR_STS_ISH2HOST_BIT,
-		.pimr_2ish_bit = IPC_PIMR_HOST2ISH_BIT,
-		.pimr_2host_clearing_bit = IPC_PIMR_ISH2HOST_CLR_BIT,
-		.irq_in = ISH_IPC_HOST2ISH_IRQ,
-		.irq_clr = ISH_IPC_ISH2HOST_CLR_IRQ,
-		.tx_queue = QUEUE_NULL(IPC_HOST_MSG_QUEUE_SIZE, struct ipc_msg),
-	},
-	/* Other peers (PMC, CSME, etc) to be added when required */
-};
-
-static inline struct ipc_if_ctx *ipc_get_if_ctx(const uint32_t peer_id)
-{
-	return &ipc_peer_ctxs[peer_id];
-}
-
-static inline struct ipc_if_ctx *ipc_handle_to_if_ctx(const ipc_handle_t handle)
-{
-	return ipc_get_if_ctx(IPC_HANDLE_PEER_ID(handle));
-}
-
-static inline void ipc_enable_pimr_db_interrupt(const struct ipc_if_ctx *ctx)
-{
-	IPC_PIMR |= ctx->pimr_2ish_bit;
-}
-
-static inline void ipc_disable_pimr_db_interrupt(const struct ipc_if_ctx *ctx)
-{
-	IPC_PIMR &= ~ctx->pimr_2ish_bit;
-}
-
-static inline void ipc_enable_pimr_clearing_interrupt(
-						const struct ipc_if_ctx *ctx)
-{
-	IPC_PIMR |= ctx->pimr_2host_clearing_bit;
-}
-
-static inline void ipc_disable_pimr_clearing_interrupt(
-						const struct ipc_if_ctx *ctx)
-{
-	IPC_PIMR &= ~ctx->pimr_2host_clearing_bit;
-}
-
-static void write_payload_and_ring_drbl(const struct ipc_if_ctx *ctx,
-					uint32_t drbl,
-					const uint8_t *payload,
-					size_t payload_size)
-{
-	memcpy((void *)(ctx->out_msg_reg), payload, payload_size);
-	*(ctx->out_drbl_reg) = drbl;
-}
-
-static int ipc_write_raw_timestamp(struct ipc_if_ctx *ctx, uint32_t drbl,
-				   const uint8_t *payload, size_t payload_size,
-				   uint32_t *timestamp)
-{
-	struct queue *q = &ctx->tx_queue;
-	struct ipc_msg *msg;
-	size_t tail, space;
-	int res = 0;
-
-	mutex_lock(&ctx->write_lock);
-
-	ipc_disable_pimr_clearing_interrupt(ctx);
-	if (ctx->is_tx_ipc_busy) {
-		space = queue_space(q);
-		if (space) {
-			tail = q->state->tail & (q->buffer_units - 1);
-			msg = (struct ipc_msg *)q->buffer + tail;
-			msg->drbl = drbl;
-			msg->timestamp_of_outgoing_doorbell = timestamp;
-			memcpy(msg->payload, payload, payload_size);
-			queue_advance_tail(q, 1);
-		} else {
-			CPRINTS("tx queue is full");
-			res = -IPC_ERR_TX_QUEUE_FULL;
-		}
-
-		ipc_enable_pimr_clearing_interrupt(ctx);
-		goto write_unlock;
-	}
-	ctx->is_tx_ipc_busy = 1;
-	ipc_enable_pimr_clearing_interrupt(ctx);
-
-	write_payload_and_ring_drbl(ctx, drbl, payload, payload_size);
-
-	/* We wrote inline, take timestamp now */
-	if (timestamp)
-		*timestamp = __hw_clock_source_read();
-
-write_unlock:
-	mutex_unlock(&ctx->write_lock);
-	return res;
-}
-
-static int ipc_write_raw(struct ipc_if_ctx *ctx, uint32_t drbl,
-			 const uint8_t *payload, size_t payload_size)
-{
-	return ipc_write_raw_timestamp(ctx, drbl, payload, payload_size, NULL);
-}
-
-static int ipc_send_reset_notify(const ipc_handle_t handle)
-{
-	struct ipc_rst_payload *ipc_rst;
-	struct ipc_if_ctx *ctx;
-	struct ipc_msg msg;
-
-	ctx = ipc_handle_to_if_ctx(handle);
-	ctx->reset_id = (uint16_t)ish_fwst_get_reset_id();
-	ipc_rst = (struct ipc_rst_payload *)msg.payload;
-	ipc_rst->reset_id = ctx->reset_id;
-
-	msg.drbl = IPC_BUILD_MNG_DB(MNG_RESET_NOTIFY, sizeof(*ipc_rst));
-	ipc_write_raw(ctx, msg.drbl, msg.payload, IPC_DB_MSG_LENGTH(msg.drbl));
-
-	return 0;
-}
-
-static int ipc_send_cmpl_indication(struct ipc_if_ctx *ctx)
-{
-	struct ipc_msg msg;
-
-	msg.drbl = IPC_BUILD_MNG_DB(MNG_RX_CMPL_INDICATION, 0);
-	ipc_write_raw(ctx, msg.drbl, msg.payload, IPC_DB_MSG_LENGTH(msg.drbl));
-
-	return 0;
-}
-
-static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx,
-				 const uint32_t protocol,
-				 uint8_t *buf, const size_t buf_size)
-{
-	int len = 0, payload_size;
-	uint8_t *src = NULL, *dest = NULL;
-	struct ipc_msg *msg;
-	uint32_t drbl_val;
-
-	drbl_val = *(ctx->in_drbl_reg);
-	payload_size = IPC_DB_MSG_LENGTH(drbl_val);
-
-	if (payload_size > IPC_MAX_PAYLOAD_SIZE) {
-		CPRINTS("invalid msg : payload is too big");
-		return -IPC_ERR_INVALID_MSG;
-	}
-
-	switch (protocol) {
-	case IPC_PROTOCOL_HECI:
-		/* copy only payload which is a heci packet */
-		len = payload_size;
-		break;
-	case IPC_PROTOCOL_MNG:
-		/* copy including doorbell which forms a ipc packet */
-		len = payload_size + sizeof(drbl_val);
-		break;
-	default:
-		CPRINTS("protocol %d not supported yet", protocol);
-		break;
-	}
-
-	if (len > buf_size) {
-		CPRINTS("buffer is smaller than payload");
-		return -IPC_ERR_TOO_SMALL_BUFFER;
-	}
-
-	if (IS_ENABLED(IPC_HECI_DEBUG))
-		CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n",
-			protocol, drbl_val,
-			IPC_DB_MSG_LENGTH(drbl_val));
-
-	switch (protocol) {
-	case IPC_PROTOCOL_HECI:
-		src = (uint8_t *)ctx->in_msg_reg;
-		dest = buf;
-		break;
-	case IPC_PROTOCOL_MNG:
-		src = (uint8_t *)ctx->in_msg_reg;
-		msg = (struct ipc_msg *)buf;
-		msg->drbl = drbl_val;
-		dest = msg->payload;
-		break;
-	default :
-		break;
-	}
-
-	if (src && dest)
-		memcpy(dest, src, payload_size);
-
-	return len;
-}
-
-static void set_pimr_and_send_rx_complete(struct ipc_if_ctx *ctx)
-{
-	ipc_enable_pimr_db_interrupt(ctx);
-	ipc_send_cmpl_indication(ctx);
-}
-
-static void handle_msg_recv_interrupt(const uint32_t peer_id)
-{
-	struct ipc_if_ctx *ctx;
-	uint32_t drbl_val, payload_size, protocol, invalid_msg = 0;
-
-	ctx = ipc_get_if_ctx(peer_id);
-	ipc_disable_pimr_db_interrupt(ctx);
-
-	drbl_val = *(ctx->in_drbl_reg);
-	protocol = IPC_DB_PROTOCOL(drbl_val);
-	payload_size = IPC_DB_MSG_LENGTH(drbl_val);
-
-	if (payload_size > IPC_MSG_MAX_SIZE)
-		invalid_msg = 1;
-
-	if (!ctx->msg_events[protocol].enabled)
-		invalid_msg = 2;
-
-	if (!invalid_msg) {
-		/* send event to task */
-		task_set_event(ctx->msg_events[protocol].task_id,
-			       ctx->msg_events[protocol].event, 0);
-	} else {
-		CPRINTS("discard msg (%d) : %d", protocol, invalid_msg);
-
-		*(ctx->in_drbl_reg) = 0;
-		set_pimr_and_send_rx_complete(ctx);
-	}
-}
-
-static void handle_busy_clear_interrupt(const uint32_t peer_id)
-{
-	struct ipc_if_ctx *ctx;
-	struct ipc_msg *msg;
-	struct queue *q;
-	size_t head;
-
-	ctx = ipc_get_if_ctx(peer_id);
-
-	/*
-	 * Resetting interrupt status bit should be done
-	 * before sending an item in tx_queue.
-	 */
-	IPC_BUSY_CLEAR = ctx->clr_busy_bit;
-
-	/*
-	 * No need to use sync mechanism here since the accesing the queue
-	 * happens only when either this IRQ is disabled or
-	 * in ISR context(here) of this IRQ.
-	 */
-	if (!queue_is_empty(&ctx->tx_queue)) {
-		q = &ctx->tx_queue;
-		head = q->state->head & (q->buffer_units - 1);
-		msg = (struct ipc_msg *)(q->buffer + head * q->unit_bytes);
-		write_payload_and_ring_drbl(ctx, msg->drbl, msg->payload,
-					    IPC_DB_MSG_LENGTH(msg->drbl));
-		if (msg->timestamp_of_outgoing_doorbell)
-			*msg->timestamp_of_outgoing_doorbell =
-				__hw_clock_source_read();
-
-		queue_advance_head(q, 1);
-	} else {
-		ctx->is_tx_ipc_busy = 0;
-	}
-}
-
-/**
- * IPC interrupts are received by the FW when a) Host SW rings doorbell and
- * b) when Host SW clears doorbell busy bit [31].
- *
- * Doorbell Register (DB) bits
- * ----+-------+--------+-----------+--------+------------+--------------------
- *  31 | 30 29 |  28-20 |19 18 17 16| 15 14  | 13 12 11 10| 9 8 7 6 5 4 3 2 1 0
- * ----+-------+--------+-----------+--------+------------+--------------------
- * Busy|Options|Reserved|  Command  |Reserved|   Protocol |    Message Length
- * ----+-------+--------+-----------+--------+------------+--------------------
- *
- * ISH Peripheral Interrupt Status Register:
- *  Bit 0 - If set, indicates interrupt was caused by setting Host2ISH DB
- *
- * ISH Peripheral Interrupt Mask Register
- *  Bit 0 - If set, mask interrupt caused by Host2ISH DB
- *
- * ISH Peripheral DB Clear Status Register
- *  Bit 0 - If set, indicates interrupt was caused by clearing Host2ISH DB
- */
-static void ipc_host2ish_isr(void)
-{
-	uint32_t pisr = IPC_PISR;
-	uint32_t pimr = IPC_PIMR;
-
-	/*
-	 * Ensure that the host IPC write power is requested after getting an
-	 * interrupt otherwise the resume message will never get delivered (via
-	 * host ipc communication). Resume is where we would like to restore all
-	 * power settings, but that is too late for this power request.
-	 */
-	if (IS_ENABLED(CHIP_FAMILY_ISH5))
-		PMU_VNN_REQ = VNN_REQ_IPC_HOST_WRITE & ~PMU_VNN_REQ;
-
-	if ((pisr & IPC_PISR_HOST2ISH_BIT) && (pimr & IPC_PIMR_HOST2ISH_BIT))
-		handle_msg_recv_interrupt(IPC_PEER_ID_HOST);
-}
-#ifndef CONFIG_ISH_HOST2ISH_COMBINED_ISR
-DECLARE_IRQ(ISH_IPC_HOST2ISH_IRQ, ipc_host2ish_isr);
-#endif
-
-static void ipc_host2ish_busy_clear_isr(void)
-{
-	uint32_t busy_clear = IPC_BUSY_CLEAR;
-	uint32_t pimr = IPC_PIMR;
-
-	if ((busy_clear & IPC_DB_CLR_STS_ISH2HOST_BIT) &&
-	    (pimr & IPC_PIMR_ISH2HOST_CLR_BIT))
-		handle_busy_clear_interrupt(IPC_PEER_ID_HOST);
-}
-#ifndef CONFIG_ISH_HOST2ISH_COMBINED_ISR
-DECLARE_IRQ(ISH_IPC_ISH2HOST_CLR_IRQ, ipc_host2ish_busy_clear_isr);
-#endif
-
-static __maybe_unused void ipc_host2ish_combined_isr(void)
-{
-	ipc_host2ish_isr();
-	ipc_host2ish_busy_clear_isr();
-}
-#ifdef CONFIG_ISH_HOST2ISH_COMBINED_ISR
-DECLARE_IRQ(ISH_IPC_HOST2ISH_IRQ, ipc_host2ish_combined_isr);
-#endif
-
-int ipc_write_timestamp(const ipc_handle_t handle, const void *buf,
-			const size_t buf_size, uint32_t *timestamp)
-{
-	int ret;
-	struct ipc_if_ctx *ctx;
-	uint32_t drbl = 0;
-	const uint8_t *payload = NULL;
-	int payload_size;
-	uint32_t protocol;
-
-	if (!IPC_IS_VALID_HANDLE(handle))
-		return -EC_ERROR_INVAL;
-
-	protocol = IPC_HANDLE_PROTOCOL(handle);
-	ctx = ipc_handle_to_if_ctx(handle);
-
-	if (ctx->initialized == 0) {
-		CPRINTS("open_ipc() for the peer is never called");
-		return -EC_ERROR_INVAL;
-	}
-
-	if (!ctx->msg_events[protocol].enabled) {
-		CPRINTS("call open_ipc() for the protocol first");
-		return -EC_ERROR_INVAL;
-	}
-
-	switch (protocol) {
-	case IPC_PROTOCOL_BOOT:
-		break;
-	case IPC_PROTOCOL_HECI:
-		drbl = IPC_BUILD_HECI_DB(buf_size);
-		payload = buf;
-		break;
-	case IPC_PROTOCOL_MCTP:
-		break;
-	case IPC_PROTOCOL_MNG:
-		drbl = ((struct ipc_msg *)buf)->drbl;
-		payload = ((struct ipc_msg *)buf)->payload;
-		break;
-	case IPC_PROTOCOL_ECP:
-		/* TODO : EC protocol */
-		break;
-	}
-
-	payload_size = IPC_DB_MSG_LENGTH(drbl);
-	if (payload_size > IPC_MSG_MAX_SIZE) {
-		/* too much input */
-		return -EC_ERROR_OVERFLOW;
-	}
-
-	ret = ipc_write_raw_timestamp(ctx, drbl, payload, payload_size,
-				      timestamp);
-	if (ret)
-		return ret;
-
-	return buf_size;
-}
-
-ipc_handle_t ipc_open(const enum ipc_peer_id peer_id,
-		      const enum ipc_protocol protocol,
-		      const uint32_t event)
-{
-	struct ipc_if_ctx *ctx;
-
-	if (protocol >= IPC_PROTOCOL_COUNT ||
-	    peer_id >= IPC_PEERS_COUNT)
-		return IPC_INVALID_HANDLE;
-
-	ctx = ipc_get_if_ctx(peer_id);
-	mutex_lock(&ctx->lock);
-	if (ctx->msg_events[protocol].enabled) {
-		mutex_unlock(&ctx->lock);
-		return IPC_INVALID_HANDLE;
-	}
-
-	ctx->msg_events[protocol].task_id = task_get_current();
-	ctx->msg_events[protocol].enabled = 1;
-	ctx->msg_events[protocol].event = event;
-
-	 /* For HECI protocol, set HECI UP status when IPC link is ready */
-	if (peer_id == IPC_PEER_ID_HOST &&
-	    protocol == IPC_PROTOCOL_HECI && ish_fwst_is_ilup_set())
-		ish_fwst_set_hup();
-
-	if (ctx->initialized == 0) {
-		task_enable_irq(ctx->irq_in);
-		if (!IS_ENABLED(CONFIG_ISH_HOST2ISH_COMBINED_ISR))
-			task_enable_irq(ctx->irq_clr);
-
-		ipc_enable_pimr_db_interrupt(ctx);
-		ipc_enable_pimr_clearing_interrupt(ctx);
-
-		ctx->initialized = 1;
-	}
-	mutex_unlock(&ctx->lock);
-
-	return IPC_BUILD_HANDLE(peer_id, protocol);
-}
-
-static void handle_mng_commands(const ipc_handle_t handle,
-				const struct ipc_msg *msg)
-{
-	struct ipc_rst_payload *ipc_rst;
-	struct ipc_if_ctx *ctx;
-	uint32_t peer_id = IPC_HANDLE_PEER_ID(handle);
-
-	ctx = ipc_handle_to_if_ctx(handle);
-
-	switch (IPC_DB_CMD(msg->drbl)) {
-	case MNG_RX_CMPL_ENABLE:
-	case MNG_RX_CMPL_DISABLE:
-	case MNG_RX_CMPL_INDICATION:
-	case MNG_RESET_NOTIFY:
-		CPRINTS("msg not handled %d", IPC_DB_CMD(msg->drbl));
-		break;
-	case MNG_RESET_NOTIFY_ACK:
-		ipc_rst = (struct ipc_rst_payload *)msg->payload;
-		if (peer_id == IPC_PEER_ID_HOST &&
-		    ipc_rst->reset_id == ctx->reset_id) {
-			ish_fwst_set_ilup();
-			if (ctx->msg_events[IPC_PROTOCOL_HECI].enabled)
-				ish_fwst_set_hup();
-		}
-
-		break;
-	case MNG_SYNC_FW_CLOCK:
-		/* Not supported currently, but kernel sends this about ~20s */
-		break;
-	}
-}
-
-static int do_ipc_read(struct ipc_if_ctx *ctx, const uint32_t protocol,
-		       uint8_t *buf, const size_t buf_size)
-{
-	int len;
-
-	len = ipc_get_protocol_data(ctx, protocol, buf, buf_size);
-
-	*(ctx->in_drbl_reg) = 0;
-	set_pimr_and_send_rx_complete(ctx);
-
-	return len;
-}
-
-static int ipc_check_read_validity(const struct ipc_if_ctx *ctx,
-				   const uint32_t protocol)
-{
-	if (ctx->initialized == 0)
-		return -EC_ERROR_INVAL;
-
-	if (!ctx->msg_events[protocol].enabled)
-		return -EC_ERROR_INVAL;
-
-	/* ipc_read() should be called by the same task called ipc_open() */
-	if (ctx->msg_events[protocol].task_id != task_get_current())
-		return -IPC_ERR_INVALID_TASK;
-
-	return 0;
-}
-
-/*
- * ipc_read should be called by the same task context which called ipc_open()
- */
-int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size,
-	     int timeout_us)
-{
-	struct ipc_if_ctx *ctx;
-	uint32_t events, protocol, drbl_protocol, drbl_val;
-	int ret;
-
-	if (!IPC_IS_VALID_HANDLE(handle))
-		return -EC_ERROR_INVAL;
-
-	protocol = IPC_HANDLE_PROTOCOL(handle);
-	ctx = ipc_handle_to_if_ctx(handle);
-
-	ret = ipc_check_read_validity(ctx, protocol);
-	if (ret)
-		return ret;
-
-	if (timeout_us) {
-		events = task_wait_event_mask(ctx->msg_events[protocol].event,
-					      timeout_us);
-
-		if (events & TASK_EVENT_TIMER)
-			return -EC_ERROR_TIMEOUT;
-
-		if (!(events & ctx->msg_events[protocol].event))
-			return -EC_ERROR_UNKNOWN;
-	} else {
-		/* check if msg for the protocol is available */
-		drbl_val = *(ctx->in_drbl_reg);
-		drbl_protocol = IPC_DB_PROTOCOL(drbl_val);
-		if (!(protocol == drbl_protocol) || !IPC_DB_BUSY(drbl_val))
-			return -IPC_ERR_MSG_NOT_AVAILABLE;
-	}
-
-	return do_ipc_read(ctx, protocol, buf, buf_size);
-}
-
-/* event flag for MNG msg */
-#define EVENT_FLAG_BIT_MNG_MSG			TASK_EVENT_CUSTOM_BIT(0)
-
-/*
- * This task handles MNG messages
- */
-void ipc_mng_task(void)
-{
-	int payload_size;
-	struct ipc_msg msg;
-	ipc_handle_t handle;
-
-	/*
-	 * Ensure that power for host IPC writes is requested and ack'ed
-	 */
-	if (IS_ENABLED(CHIP_FAMILY_ISH5)) {
-		PMU_VNN_REQ = VNN_REQ_IPC_HOST_WRITE & ~PMU_VNN_REQ;
-		while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS))
-			continue;
-	}
-
-	handle = ipc_open(IPC_PEER_ID_HOST, IPC_PROTOCOL_MNG,
-			  EVENT_FLAG_BIT_MNG_MSG);
-
-	ASSERT(handle != IPC_INVALID_HANDLE);
-
-	ipc_send_reset_notify(handle);
-
-	while (1) {
-		payload_size = ipc_read(handle, &msg, sizeof(msg), -1);
-
-		/* allow doorbell with any payload */
-		if (payload_size < 0) {
-			CPRINTS("ipc_read error. discard msg");
-			continue; /* TODO: retry several and exit */
-		}
-
-		/* handle MNG commands */
-		handle_mng_commands(handle, &msg);
-	}
-}
-
-void ipc_init(void)
-{
-	int i;
-	struct ipc_if_ctx *ctx;
-
-	for (i = 0; i < IPC_PEERS_COUNT; i++) {
-		ctx = ipc_get_if_ctx(i);
-		queue_init(&ctx->tx_queue);
-	}
-
-	/* inform host firmware is running */
-	ish_fwst_set_fw_status(FWSTS_FW_IS_RUNNING);
-}
-DECLARE_HOOK(HOOK_INIT, ipc_init, HOOK_PRIO_DEFAULT);
diff --git a/chip/ish/ipc_heci.h b/chip/ish/ipc_heci.h
deleted file mode 100644
index 183e6a2c6b..0000000000
--- a/chip/ish/ipc_heci.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IPC module for ISH */
-#ifndef __IPC_HECI_H
-#define __IPC_HECI_H
-
-enum IPC_ERR {
-	IPC_ERR_IPC_IS_NOT_READY	= EC_ERROR_INTERNAL_FIRST + 0,
-	IPC_ERR_TOO_SMALL_BUFFER	= EC_ERROR_INTERNAL_FIRST + 1,
-	IPC_ERR_TX_QUEUE_FULL		= EC_ERROR_INTERNAL_FIRST + 2,
-	IPC_ERR_INVALID_TASK		= EC_ERROR_INTERNAL_FIRST + 3,
-	IPC_ERR_MSG_NOT_AVAILABLE	= EC_ERROR_INTERNAL_FIRST + 4,
-	IPC_ERR_INVALID_MSG		= EC_ERROR_INTERNAL_FIRST + 5,
-};
-
-enum ipc_peer_id {
-	IPC_PEER_ID_HOST	= 0, /* x64 host */
-#if 0 /* other peers are not implemented yet */
-	IPC_PEER_ID_PMC		= 1, /* Power Management Controller */
-	IPC_PEER_ID_CSME	= 2, /* Converged Security Management Engine */
-	IPC_PEER_ID_CAVS    = 3, /* Audio, Voice, and Speech engine */
-	IPC_PEER_ID_ISP 	= 4, /* Image Signal Processor */
-#endif
-	IPC_PEERS_COUNT,
-};
-/*
- * Currently ipc handle encoding only allows maximum 16 peers which is
- * enough for ISH3, ISH4, and ISH5. They have 5 peers.
- */
-BUILD_ASSERT(IPC_PEERS_COUNT <= 0x0F);
-
-enum ipc_protocol {
-	IPC_PROTOCOL_BOOT = 0,	/* Not supported */
-	IPC_PROTOCOL_HECI,	/* Host Embedded Controller Interface */
-	IPC_PROTOCOL_MCTP,	/* not supported */
-	IPC_PROTOCOL_MNG,	/* Management protocol */
-	IPC_PROTOCOL_ECP,	/* EC Protocol. not supported */
-	IPC_PROTOCOL_COUNT
-};
-/*
- * IPC handle enconding only supports 16 protocols which is the
- * maximum protocols supported by IPC doorbell encoding.
- */
-BUILD_ASSERT(IPC_PROTOCOL_COUNT <= 0x0F);
-
-typedef void *				ipc_handle_t;
-
-#define IPC_MAX_PAYLOAD_SIZE		128
-#define IPC_INVALID_HANDLE		NULL
-
-/*
- * Open ipc channel
- *
- * @param peer_id	select peer to communicate.
- * @param protocol	select protocol
- * @param event		set event flag
- *
- * @return		ipc handle or IPC_INVALID_HANDLE if there's error
- */
-ipc_handle_t ipc_open(const enum ipc_peer_id peer_id,
-		      const enum ipc_protocol protocol,
-		      const uint32_t event);
-void ipc_close(const ipc_handle_t handle);
-
-/*
- * Read message from ipc channel.
- * The function should be call by the same task called ipc_open().
- * The function waits until message is available.
- * @param timeout_us	if == -1, wait until message is available.
- *			if == 0, return immediately.
- *			if > 0, wait for the specified microsecond duration time
- */
-int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size,
-             int timeout_us);
-
-/* Write message to ipc channel. */
-int ipc_write_timestamp(const ipc_handle_t handle, const void *buf,
-	      const size_t buf_size, uint32_t *timestamp);
-
-#endif /* __IPC_HECI_H */
diff --git a/chip/ish/ish_dma.h b/chip/ish/ish_dma.h
deleted file mode 100644
index 2c76c7d319..0000000000
--- a/chip/ish/ish_dma.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ISH_DMA_H
-#define __CROS_EC_ISH_DMA_H
-
-/* DMA return codes */
-#define DMA_RC_OK 0 /* Success */
-#define DMA_RC_TO 1 /* Time out */
-#define DMA_RC_HW 2 /* HW error (OCP) */
-
-/* DMA channels */
-#define PAGING_CHAN 0
-#define KERNEL_CHAN 1
-
-#define DST_IS_DRAM BIT(0)
-#define SRC_IS_DRAM BIT(1)
-#define NON_SNOOP BIT(2)
-
-/* ISH5 and on */
-#define RS0 0x0
-#define RS3 0x3
-#define RS_SRC_OFFSET 3
-#define RS_DST_OFFSET 5
-
-#define PAGE_SIZE 4096
-
-/**
- * SRAM: ISH local static ram
- * UMA: Protected system DRAM region dedicated for ISH
- * HOST_DRAM: OS owned buffer in system DRAM
- */
-enum dma_mode {
-	SRAM_TO_SRAM = 0,
-	SRAM_TO_UMA = DST_IS_DRAM | (RS3 << RS_DST_OFFSET),
-	UMA_TO_SRAM = SRC_IS_DRAM | (RS3 << RS_SRC_OFFSET),
-	HOST_DRAM_TO_SRAM = SRC_IS_DRAM | (RS0 << RS_SRC_OFFSET),
-	SRAM_TO_HOST_DRAM = DST_IS_DRAM | (RS0 << RS_DST_OFFSET)
-};
-
-/* Disable DMA engine */
-void ish_dma_disable(void);
-/* Initialize  DMA engine */
-void ish_dma_init(void);
-
-/**
- * Main DMA transfer function
- *
- * @param chan          DMA channel
- * @param dst           Destination address
- * @param src           Source address
- * @param length        Transfer size
- * @param mode          Transfer mode
- * @return DMA_RC_OK, or non-zero if error.
- */
-int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length,
-		 enum dma_mode mode);
-/**
- * Set upper 32 bits address for DRAM
- *
- * @param chan          DMA channel
- * @param dst_msb       Destination DRAM upper 32 bits address
- * @param src_msb       Source DRAM upper 32 bits address
- */
-void ish_dma_set_msb(uint32_t chan, uint32_t dst_msb, uint32_t src_msb);
-
-/**
- * Wait for DMA transfer finish
- *
- * @param chan          DMA channel
- * @return DMA_RC_OK, or non-zero if error.
- */
-int ish_wait_for_dma_done(uint32_t ch);
-
-/* Disable OCP (Open Core Protocol) fabric time out */
-void ish_dma_ocp_timeout_disable(void);
-#endif
diff --git a/chip/ish/ish_fwst.h b/chip/ish/ish_fwst.h
deleted file mode 100644
index c114db3241..0000000000
--- a/chip/ish/ish_fwst.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/*
- * ISH Firmware status register contains currnet ISH FW status.
- * Communication protocol for Host(x64), CSME, and PMC uses this register.
- */
-
-#ifndef __ISH_FWST_H
-#define __ISH_FWST_H
-
-#include "common.h"
-#include "registers.h"
-
-/*
- * IPC link is up(ready)
- * IPC can be used by other protocols
- */
-#define IPC_ISH_FWSTS_ILUP_FIELD		0x01
-#define IPC_ISH_FWSTS_ILUP_SHIFT		0
-#define IPC_ISH_FWSTS_ILUP_MASK	\
-	  (IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT)
-
-/*
- * HECI layer is up(ready)
- */
-#define IPC_ISH_FWSTS_HUP_FIELD			0x01
-#define IPC_ISH_FWSTS_HUP_SHIFT			1
-#define IPC_ISH_FWSTS_HUP_MASK \
-	  (IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT)
-
-/*
- * ISH FW reason reason
- */
-#define IPC_ISH_FWSTS_FAIL_REASON_FIELD		0x0F
-#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT		2
-#define IPC_ISH_FWSTS_FAIL_REASON_MASK \
-	  (IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT)
-
-/*
- * ISH FW reset ID
- */
-#define IPC_ISH_FWSTS_RESET_ID_FIELD		0x0F
-#define IPC_ISH_FWSTS_RESET_ID_SHIFT		8
-#define IPC_ISH_FWSTS_RESET_ID_MASK \
-	  (IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT)
-
-/*
- * ISH FW status type
- */
-enum {
-	FWSTS_AFTER_RESET               = 0,
-	FWSTS_WAIT_FOR_HOST             = 4,
-	FWSTS_START_KERNEL_DMA          = 5,
-	FWSTS_FW_IS_RUNNING             = 7,
-	FWSTS_SENSOR_APP_LOADED         = 8,
-	FWSTS_SENSOR_APP_RUNNING        = 15
-};
-
-/*
- * General ISH FW status
- */
-#define IPC_ISH_FWSTS_FW_STATUS_FIELD		0x0F
-#define IPC_ISH_FWSTS_FW_STATUS_SHIFT		12
-#define IPC_ISH_FWSTS_FW_STATUS_MASK \
-	  (IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT)
-
-#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT		16
-#define IPC_ISH_FWSTS_DMA0_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT)
-
-#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT		17
-#define IPC_ISH_FWSTS_DMA1_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT)
-
-#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT		18
-#define IPC_ISH_FWSTS_DMA2_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT)
-
-#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT		19
-#define IPC_ISH_FWSTS_DMA3_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT)
-
-#define IPC_ISH_FWSTS_POWER_STATE_FIELD		0x0F
-#define IPC_ISH_FWSTS_POWER_STATE_SHIFT		20
-#define IPC_ISH_FWSTS_POWER_STATE_MASK \
-	  (IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT)
-
-#define IPC_ISH_FWSTS_AON_CHECK_FIELD		0x07
-#define IPC_ISH_FWSTS_AON_CHECK_SHIFT		24
-#define IPC_ISH_FWSTS_AON_CHECK_MASK \
-	  (IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT)
-
-/* get ISH FW status register */
-static inline uint32_t ish_fwst_get(void)
-{
-	return IPC_ISH_FWSTS;
-}
-
-/* set IPC link up */
-static inline void ish_fwst_set_ilup(void)
-{
-	IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_ILUP_SHIFT);
-}
-
-/* clear IPC link up */
-static inline void ish_fwst_clear_ilup(void)
-{
-	IPC_ISH_FWSTS &= ~IPC_ISH_FWSTS_ILUP_MASK;
-}
-
-/* return IPC link up state */
-static inline int ish_fwst_is_ilup_set(void)
-{
-	return !!(IPC_ISH_FWSTS & IPC_ISH_FWSTS_ILUP_MASK);
-}
-
-/* set HECI up */
-static inline void ish_fwst_set_hup(void)
-{
-	IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_HUP_SHIFT);
-}
-
-/* clear HECI up */
-static inline void ish_fwst_clear_hup(void)
-{
-	IPC_ISH_FWSTS &= ~IPC_ISH_FWSTS_HUP_MASK;
-}
-
-/* get HECI up status */
-static inline int ish_fwst_is_hup_set(void)
-{
-	return !!(IPC_ISH_FWSTS & IPC_ISH_FWSTS_HUP_MASK);
-}
-
-/* set fw failure reason */
-static inline void ish_fwst_set_fail_reason(uint32_t val)
-{
-	uint32_t fwst = IPC_ISH_FWSTS;
-
-	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FAIL_REASON_MASK) |
-		(val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT);
-}
-
-/* get fw failure reason */
-static inline uint32_t ish_fwst_get_fail_reason(void)
-{
-	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK)
-		>> IPC_ISH_FWSTS_FAIL_REASON_SHIFT;
-}
-
-/* set reset id */
-static inline void ish_fwst_set_reset_id(uint32_t val)
-{
-	uint32_t fwst = IPC_ISH_FWSTS;
-
-	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) |
-		(val << IPC_ISH_FWSTS_RESET_ID_SHIFT);
-}
-
-/* get reset id */
-static inline uint32_t ish_fwst_get_reset_id(void)
-{
-	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK)
-		>> IPC_ISH_FWSTS_RESET_ID_SHIFT;
-}
-
-/* set general fw status */
-static inline void ish_fwst_set_fw_status(uint32_t val)
-{
-	uint32_t fwst = IPC_ISH_FWSTS;
-
-	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) |
-		(val << IPC_ISH_FWSTS_FW_STATUS_SHIFT);
-}
-
-/* get general fw status */
-static inline uint32_t ish_fwst_get_fw_status(void)
-{
-	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK)
-		>> IPC_ISH_FWSTS_FW_STATUS_SHIFT;
-}
-
-#endif /* __ISH_FWST_H */
diff --git a/chip/ish/ish_i2c.h b/chip/ish/ish_i2c.h
deleted file mode 100644
index 5b30de775c..0000000000
--- a/chip/ish/ish_i2c.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ISH_I2C_H
-#define __CROS_EC_ISH_I2C_H
-
-#include <stdint.h>
-#include "task.h"
-
-#define I2C_TSC_TIMEOUT			2000000
-#define I2C_CALIB_ADDRESS		0x3
-#define I2C_INTERRUPT_TIMEOUT		(TICKFREQ / 20)
-#define NS_IN_SEC			1000
-#define DEFAULT_SDA_HOLD		240
-#define DEFAULT_SDA_HOLD_STD		2400
-#define DEFAULT_SDA_HOLD_FAST		600
-#define DEFAULT_SDA_HOLD_FAST_PLUS	300
-#define DEFAULT_SDA_HOLD_HIGH		140
-#define NS_2_COUNTERS(ns, clk)		((ns * clk)/NS_IN_SEC)
-#define COUNTERS_2_NS(counters, clk)	(counters * (NANOSECONDS_IN_SEC / \
-					(clk * HZ_IN_MEGAHZ)))
-#define I2C_TX_FLUSH_TIMEOUT_USEC	200
-
-#define ISH_I2C_FIFO_SIZE 64
-
-
-enum {
-	/* freq mode values */
-	I2C_FREQ_25 = 0,
-	I2C_FREQ_50 = 1,
-	I2C_FREQ_100 = 2,
-	I2C_FREQ_120 = 3,
-	I2C_FREQ_40 = 4,
-	I2C_FREQ_20 = 5,
-	I2C_FREQ_37 = 6
-};
-
-const unsigned int clk_in[] = {
-	[I2C_FREQ_25] = 25,
-	[I2C_FREQ_50] = 50,
-	[I2C_FREQ_100] = 100,
-	[I2C_FREQ_120] = 120,
-	[I2C_FREQ_40] = 40,
-	[I2C_FREQ_20] = 20,
-	[I2C_FREQ_37] = 37,
-};
-
-const uint8_t spkln[] = {
-	[I2C_FREQ_25] = 2,
-	[I2C_FREQ_50] = 3,
-	[I2C_FREQ_100] = 5,
-	[I2C_FREQ_120] = 6,
-	[I2C_FREQ_40] = 2,
-	[I2C_FREQ_20] = 1,
-	[I2C_FREQ_37] = 2,
-};
-
-enum {
-	I2C_READ,
-	I2C_WRITE
-};
-
-enum {
-	/* REGISTERS */
-	IC_ENABLE = 0x6c,
-	IC_STATUS = 0x70,
-	IC_ENABLE_STATUS = 0x9c,
-	IC_CON = 0x00,
-	IC_TAR = 0x04,
-	IC_DATA_CMD = 0x10,
-	IC_RX_TL = 0x38,
-	IC_TX_TL = 0x3c,
-	IC_COMP_PARAM_1 = 0xf4,
-	IC_INTR_MASK = 0x30,
-	IC_RAW_INTR_STAT = 0x34,
-	IC_INTR_STAT = 0x2c,
-	IC_CLR_TX_ABRT = 0x54,
-	IC_TX_ABRT_SOURCE = 0x80,
-	IC_SS_SCL_HCNT = 0x14,
-	IC_SS_SCL_LCNT = 0x18,
-	IC_FS_SCL_HCNT = 0x1c,
-	IC_FS_SCL_LCNT = 0x20,
-	IC_HS_SCL_HCNT = 0x24,
-	IC_HS_SCL_LCNT = 0x28,
-	IC_CLR_STOP_DET = 0x60,
-	IC_CLR_START_DET = 0x64,
-	IC_TXFLR = 0x74,
-	IC_SDA_HOLD = 0x7c,
-	IC_FS_SPKLEN = 0xA0,
-	IC_HS_SPKLEN = 0xA4,
-	/* IC_ENABLE VALUES */
-	IC_ENABLE_ENABLE = 1,
-	IC_ENABLE_DISABLE = 0,
-	/* IC_STATUS OFFSETS */
-	IC_STATUS_MASTER_ACTIVITY = 5,
-	IC_STATUS_TFE = 2,
-	/* IC_CON OFFSETS */
-	MASTER_MODE_OFFSET = 0,
-	SPEED_OFFSET = 1,
-	IC_RESTART_EN_OFFSET = 5,
-	IC_SLAVE_DISABLE_OFFSET = 6,
-	/* IC_CON VALUES */
-	MASTER_MODE = 1,
-	STD_SPEED = 1,
-	FAST_SPEED = 2,
-	HIGH_SPEED = 3,
-	IC_RESTART_EN = 1,
-	IC_SLAVE_DISABLE = 1,
-	/* IC_CON WRITE VALUES */
-	MASTER_MODE_VAL = (MASTER_MODE << MASTER_MODE_OFFSET),
-	STD_SPEED_VAL = (STD_SPEED << SPEED_OFFSET),
-	FAST_SPEED_VAL = (FAST_SPEED << SPEED_OFFSET),
-	HIGH_SPEED_VAL = (HIGH_SPEED << SPEED_OFFSET),
-	SPEED_MASK = (0x3 << SPEED_OFFSET),
-	IC_RESTART_EN_VAL = (IC_RESTART_EN << IC_RESTART_EN_OFFSET),
-	IC_SLAVE_DISABLE_VAL = (IC_SLAVE_DISABLE << IC_SLAVE_DISABLE_OFFSET),
-	/* IC_TAR OFFSETS */
-	IC_TAR_OFFSET = 0,
-	SPECIAL_OFFSET = 11,
-	IC_10BITADDR_MASTER_OFFSET = 12,
-	/* IC_TAR VALUES */
-	TAR_SPECIAL = 0,
-	IC_10BITADDR_MASTER = 0,
-	/* IC_TAR WRITE VALUES */
-	IC_10BITADDR_MASTER_VAL =
-	    (IC_10BITADDR_MASTER << IC_10BITADDR_MASTER_OFFSET),
-	TAR_SPECIAL_VAL = (TAR_SPECIAL << SPECIAL_OFFSET),
-	/* IC_DATA_CMD OFFSETS */
-	DATA_CMD_DAT_OFFSET = 0,
-	DATA_CMD_CMD_OFFSET = 8,
-	DATA_CMD_STOP_OFFSET = 9,
-	DATA_CMD_RESTART_OFFSET = 10,
-	/* IC_DATA_CMD VALUES */
-	DATA_CMD_READ = 1,
-	DATA_CMD_WRITE = 0,
-	DATA_CMD_STOP = 1,
-	DATA_CMD_RESTART = 1,
-	/* IC_DATA_CMD WRITE VALUES */
-	DATA_CMD_WRITE_VAL = (DATA_CMD_WRITE << DATA_CMD_CMD_OFFSET),
-	DATA_CMD_READ_VAL = (DATA_CMD_READ << DATA_CMD_CMD_OFFSET),
-	DATA_CMD_STOP_VAL = (DATA_CMD_STOP << DATA_CMD_STOP_OFFSET),
-	DATA_CMD_RESTART_VAL = (DATA_CMD_RESTART << DATA_CMD_RESTART_OFFSET),
-	/* IC_TX_TL */
-	IC_TX_TL_VAL = 0,
-	/* IC_COM_PARAM_OFFSETS */
-	TX_BUFFER_DEPTH_OFFSET = 16,
-	RX_BUFFER_DEPTH_OFFSET = 8,
-	/* IC_INTR_MASK VALUES */
-	M_RX_FULL = BIT(2),
-	M_TX_EMPTY = BIT(4),
-	M_TX_ABRT = BIT(6),
-	M_STOP_DET = BIT(9),
-	M_START_DET = BIT(10),
-	IC_INTR_WRITE_MASK_VAL = (M_STOP_DET | M_TX_ABRT),
-	IC_INTR_READ_MASK_VAL = (M_RX_FULL | M_TX_ABRT),
-	DISABLE_INT = 0,
-	ENABLE_WRITE_INT = 1,
-	ENABLE_READ_INT = 2,
-	/* IC_ENABLE_STATUS_OFFSETS */
-	IC_EN_OFFSET = 0,
-	/* IC_ENABLE_STATUS_VALUES */
-	IC_EN_DISABLED_VAL = 0,
-	IC_EN_DISABLED = (IC_EN_DISABLED_VAL << IC_EN_OFFSET),
-	IC_EN_MASK = BIT(IC_EN_OFFSET),
-	/* IC_TX_ABRT_SOURCE bits */
-	ABRT_7B_ADDR_NOACK = 1,
-};
-
-struct i2c_bus_data {
-	uint16_t hcnt;
-	uint16_t lcnt;
-	uint16_t sda_hold;
-};
-
-struct i2c_bus_info {
-	uint8_t bus_id;
-	struct i2c_bus_data std_speed;
-	struct i2c_bus_data fast_speed;
-	struct i2c_bus_data fast_plus_speed;
-	struct i2c_bus_data high_speed;
-} __attribute__ ((__packed__));
-
-enum i2c_speed {
-	I2C_SPEED_100KHZ,	/* 100kHz */
-	I2C_SPEED_400KHZ,	/* 400kHz */
-	I2C_SPEED_1MHZ,		/*   1MHz */
-	I2C_SPEED_3M4HZ,	/* 3.4MHz */
-};
-
-struct i2c_context {
-	uint32_t *base;
-	uint8_t max_rx_depth;
-	uint8_t max_tx_depth;
-	uint8_t bus;
-	enum i2c_speed speed;
-	uint32_t interrupts;
-	uint32_t reason;
-	uint32_t int_pin;
-	uint8_t error_flag;
-	task_id_t wait_task_id;
-};
-
-#endif /* __CROS_EC_ISH_I2C_H */
diff --git a/chip/ish/ish_persistent_data.c b/chip/ish/ish_persistent_data.c
deleted file mode 100644
index 003f781d5f..0000000000
--- a/chip/ish/ish_persistent_data.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "config.h"
-#include "hooks.h"
-#include "system.h"
-#include "ish_persistent_data.h"
-
-#define PERSISTENT_DATA_MAGIC 0x49534864 /* "ISHd" */
-
-struct ish_persistent_data ish_persistent_data = {
-	.magic = PERSISTENT_DATA_MAGIC,
-	.reset_flags = EC_RESET_FLAG_POWER_ON,
-	.watchdog_counter = 0,
-	.panic_data = {0},
-};
-
-/*
- * When AON task firmware is not available (perhaps in the early
- * stages of bringing up a new board), we have no way to persist data
- * across reset. Allocate a memory region for "persistent data" which
- * will never persist, this way we can use ish_persistent_data in a
- * consistent manner without having to worry if the AON task firmware
- * is available.
- *
- * Otherwise (AON task firmware is available), the
- * ish_persistent_data_aon symbol is exported by the linker script.
- */
-#ifdef CONFIG_ISH_PM_AONTASK
-extern struct ish_persistent_data ish_persistent_data_aon;
-#else
-static struct ish_persistent_data ish_persistent_data_aon;
-#endif
-
-void ish_persistent_data_init(void)
-{
-	if (ish_persistent_data_aon.magic == PERSISTENT_DATA_MAGIC) {
-		/* Stored data is valid, load a copy */
-		memcpy(&ish_persistent_data,
-		       &ish_persistent_data_aon,
-		       sizeof(struct ish_persistent_data));
-
-		/* Invalidate stored data, in case commit fails to happen */
-		ish_persistent_data_aon.magic = 0;
-	}
-
-	/* Update the system module's copy of the reset flags */
-	system_set_reset_flags(chip_read_reset_flags());
-}
-
-void ish_persistent_data_commit(void)
-{
-	memcpy(&ish_persistent_data_aon,
-	       &ish_persistent_data,
-	       sizeof(struct ish_persistent_data));
-}
diff --git a/chip/ish/ish_persistent_data.h b/chip/ish/ish_persistent_data.h
deleted file mode 100644
index 0fd973e1bb..0000000000
--- a/chip/ish/ish_persistent_data.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ISH_PERSISTENT_DATA_H
-#define __CROS_EC_ISH_PERSISTENT_DATA_H
-
-#include "panic.h"
-
-/*
- * If you make backwards-incompatible changes to this struct, (that
- * is, reading a previous version of the data would be incorrect),
- * simply change the magic number in ish_persistent_data.c. This will
- * cause the struct to be re-initialized when the firmware loads.
- */
-struct ish_persistent_data {
-	uint32_t magic;
-	uint32_t reset_flags;
-	uint32_t watchdog_counter;
-	struct panic_data panic_data;
-};
-
-/*
- * Local copy of persistent data, which is copied from AON memory only
- * if the data in AON memory is valid.
- */
-extern struct ish_persistent_data ish_persistent_data;
-
-/*
- * Copy the AON persistent data into the local copy and initialize
- * system reset flags, only if magic number is correct.
- */
-void ish_persistent_data_init(void);
-
-/*
- * Commit the local copy to the AON memory (to be called at reset).
- */
-void ish_persistent_data_commit(void);
-
-/**
- * SNOWBALL - registers about UMA/IMR DDR information and FW location
- * in it.  ISH Bringup will set these register values at boot
- */
-struct snowball_struct {
-	uint32_t reserved[28];
-	uint32_t volatile uma_base_hi;
-	uint32_t volatile uma_base_lo;
-	uint32_t volatile uma_limit;
-	uint32_t volatile fw_offset;
-};
-
-#endif /* __CROS_EC_ISH_PERSISTENT_DATA_H */
diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c
deleted file mode 100644
index f6ef5f8e0b..0000000000
--- a/chip/ish/power_mgt.c
+++ /dev/null
@@ -1,739 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "aontaskfw/ish_aon_share.h"
-#include "console.h"
-#include "hwtimer.h"
-#include "interrupts.h"
-#include "ish_dma.h"
-#include "ish_persistent_data.h"
-#include "power_mgt.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
-
-/* defined in link script: core/minute-ia/ec.lds.S */
-extern uint32_t __aon_ro_start;
-extern uint32_t __aon_ro_end;
-extern uint32_t __aon_rw_start;
-extern uint32_t __aon_rw_end;
-
-/**
- * on ISH, uart interrupt can only wakeup ISH from low power state via
- * CTS pin, but most ISH platforms only have Rx and Tx pins, no CTS pin
- * exposed, so, we need block ISH enter low power state for a while when
- * console is in use.
- * fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the low speed clock is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-
-/* power management internal context data structure */
-struct pm_context {
-	/* aontask image valid flag */
-	int aon_valid;
-	/* point to the aon shared data in aontask */
-	struct ish_aon_share *aon_share;
-	/* TSS segment selector for task switching */
-	int aon_tss_selector[2];
-	/* console expire time */
-	timestamp_t console_expire_time;
-	/* console in use timeout */
-	int console_in_use_timeout_sec;
-} __packed;
-
-static struct pm_context pm_ctx = {
-	.aon_valid = 0,
-	/* aon shared data located in the start of aon memory */
-	.aon_share = (struct ish_aon_share *)CONFIG_AON_RAM_BASE,
-	.console_in_use_timeout_sec = 60
-};
-
-/* D0ix statistics data, including each state's count and total stay time */
-struct pm_stat {
-	uint64_t count;
-	uint64_t total_time_us;
-};
-
-struct pm_statistics {
-	struct pm_stat d0i0;
-	struct pm_stat d0i1;
-	struct pm_stat d0i2;
-	struct pm_stat d0i3;
-};
-
-static struct pm_statistics pm_stats;
-
-/*
- * Log a new statistic
- *
- * t0: start time, in us
- * t1: end time, in us
- */
-static void log_pm_stat(struct pm_stat *stat, uint32_t t0, uint32_t t1)
-{
-	stat->total_time_us += t1 - t0;
-	stat->count++;
-}
-
-#ifdef CONFIG_ISH_PM_AONTASK
-
-/* The GDT which initialized in init.S */
-extern struct gdt_entry __gdt[];
-extern struct gdt_header __gdt_ptr[];
-
-/* TSS desccriptor for saving main FW's cpu context during aontask switching */
-static struct tss_entry main_tss;
-
-/**
- * add new entry in GDT
- * if defined 'CONFIG_ISH_PM_AONTASK', the GDT which defined in init.S will
- * have 3 more empty placeholder entries, this function is help to update
- * these entries which needed by x86's HW task switching method
- *
- * @param desc_lo	lower DWORD of the entry descriptor
- * @param desc_up	upper DWORD of the entry descriptor
- *
- * @return		the descriptor selector index of the added entry
- */
-static uint32_t add_gdt_entry(uint32_t desc_lo, uint32_t desc_up)
-{
-	int index;
-
-	/**
-	 * get the first empty entry of GDT which defined in init.S
-	 * each entry has a fixed size of 8 bytes
-	 */
-	index = __gdt_ptr[0].limit >> 3;
-
-	/* add the new entry descriptor to the GDT */
-	__gdt[index].dword_lo = desc_lo;
-	__gdt[index].dword_up = desc_up;
-
-	/* update GDT's limit size */
-	__gdt_ptr[0].limit += sizeof(struct gdt_entry);
-
-	return __gdt_ptr[0].limit - sizeof(struct gdt_entry);
-}
-
-static void init_aon_task(void)
-{
-	uint32_t desc_lo, desc_up;
-	struct ish_aon_share *aon_share = pm_ctx.aon_share;
-	struct tss_entry *aon_tss = aon_share->aon_tss;
-
-	if (aon_share->magic_id != AON_MAGIC_ID) {
-		pm_ctx.aon_valid = 0;
-		return;
-	}
-
-	pm_ctx.aon_valid = 1;
-
-	pm_ctx.aon_tss_selector[0] = 0;
-
-	/* fill in the 3 placeholder GDT entries */
-
-	/* TSS's limit specified as 0x67, to allow the task has permission to
-	 * access I/O port using IN/OUT instructions,'iomap_base_addr' field
-	 * must be greater than or equal to TSS' limit
-	 * see 'I/O port permissions' on
-	 *	https://en.wikipedia.org/wiki/Task_state_segment
-	 */
-	main_tss.iomap_base_addr = GDT_DESC_TSS_LIMIT;
-
-	/* set GDT entry 3 for TSS descriptor of main FW
-	 * limit: 0x67
-	 * Present = 1, DPL = 0
-	 */
-	desc_lo = GEN_GDT_DESC_LO((uint32_t)&main_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
-	desc_up = GEN_GDT_DESC_UP((uint32_t)&main_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
-	add_gdt_entry(desc_lo, desc_up);
-
-	/* set GDT entry 4 for TSS descriptor of aontask
-	 * limit: 0x67
-	 * Present = 1, DPL = 0, Accessed = 1
-	 */
-	desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
-	desc_up = GEN_GDT_DESC_UP((uint32_t)aon_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
-	pm_ctx.aon_tss_selector[1] = add_gdt_entry(desc_lo, desc_up);
-
-	/* set GDT entry 5 for LDT descriptor of aontask
-	 * Present = 1, DPL = 0, Readable = 1
-	 */
-	desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_share->aon_ldt,
-				  aon_share->aon_ldt_size, GDT_DESC_LDT_FLAGS);
-	desc_up = GEN_GDT_DESC_UP((uint32_t)aon_share->aon_ldt,
-				  aon_share->aon_ldt_size, GDT_DESC_LDT_FLAGS);
-	aon_tss->ldt_seg_selector = add_gdt_entry(desc_lo, desc_up);
-
-	/* update GDT register and set current TSS as main_tss (GDT entry 3) */
-	__asm__ volatile("lgdt __gdt_ptr;\n"
-			 "push %eax;\n"
-			 "movw $0x18, %ax;\n"
-			 "ltr %ax;\n"
-			 "pop %eax;");
-
-	aon_share->main_fw_ro_addr = (uint32_t)&__aon_ro_start;
-	aon_share->main_fw_ro_size = (uint32_t)&__aon_ro_end -
-				     (uint32_t)&__aon_ro_start;
-
-	aon_share->main_fw_rw_addr = (uint32_t)&__aon_rw_start;
-	aon_share->main_fw_rw_size = (uint32_t)&__aon_rw_end -
-				     (uint32_t)&__aon_rw_start;
-
-	ish_dma_init();
-}
-
-static inline void check_aon_task_status(void)
-{
-	struct ish_aon_share *aon_share = pm_ctx.aon_share;
-
-	if (aon_share->last_error != AON_SUCCESS) {
-		CPRINTF("aontask has errors:\n");
-		CPRINTF("    last error:   %d\n", aon_share->last_error);
-		CPRINTF("    error counts: %d\n", aon_share->error_count);
-	}
-}
-
-static void switch_to_aontask(void)
-{
-	interrupt_disable();
-
-	__sync_synchronize();
-
-	/* disable cache and flush cache */
-	__asm__ volatile("movl %%cr0, %%eax;\n"
-			 "orl $0x60000000, %%eax;\n"
-			 "movl %%eax, %%cr0;\n"
-			 "wbinvd;"
-			 :
-			 :
-			 : "eax");
-
-	/* switch to aontask through a far call with aontask's TSS selector */
-	__asm__ volatile("lcall *%0;" ::"m"(*pm_ctx.aon_tss_selector) :);
-
-	/* clear TS (Task Switched) flag and enable cache */
-	__asm__ volatile("clts;\n"
-			 "movl %%cr0, %%eax;\n"
-			 "andl $0x9FFFFFFF, %%eax;\n"
-			 "movl %%eax, %%cr0;"
-			 :
-			 :
-			 : "eax");
-
-	interrupt_enable();
-}
-
-__attribute__ ((noreturn))
-static void handle_reset_in_aontask(enum ish_pm_state pm_state)
-{
-	pm_ctx.aon_share->pm_state = pm_state;
-
-	/* only enable PMU wakeup interrupt */
-	disable_all_interrupts();
-	task_enable_irq(ISH_PMU_WAKEUP_IRQ);
-
-	if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP))
-		task_enable_irq(ISH_RESET_PREP_IRQ);
-
-	/* enable Trunk Clock Gating (TCG) of ISH */
-	CCU_TCG_EN = 1;
-
-	/* enable power gating of RF(Cache) and ROMs */
-	PMU_RF_ROM_PWR_CTRL = 1;
-
-	switch_to_aontask();
-
-	__builtin_unreachable();
-}
-
-#endif
-
-static void enter_d0i0(void)
-{
-	uint32_t t0, t1;
-
-	t0 = __hw_clock_source_read();
-	pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I0;
-
-	/* halt ISH cpu, will wakeup from any interrupt */
-	ish_mia_halt();
-
-	t1 = __hw_clock_source_read();
-	pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0;
-	log_pm_stat(&pm_stats.d0i0, t0, t1);
-}
-
-/**
- * ISH PMU does not support both-edge interrupt triggered gpio configuration.
- * If both edges are configured, then the ISH can't stay in low poer mode
- * because it will exit immediately.
- *
- * As a workaround, we scan all gpio pins which have been configured as
- * both-edge triggered, and then temporarily set each gpio pin to the single
- * edge trigger that is opposite of its value, then restore the both-edge
- * trigger configuration immediately after exiting low power mode.
- */
-static uint32_t convert_both_edge_gpio_to_single_edge(void)
-{
-	uint32_t both_edge_pins = 0;
-	int i = 0;
-
-	/**
-	 * scan GPIO GFER, GRER and GIMR registers to find the both edge
-	 * interrupt trigger mode enabled pins.
-	 */
-	for (i = 0; i < 32; i++) {
-		if (ISH_GPIO_GIMR & BIT(i) &&
-		    ISH_GPIO_GRER & BIT(i) &&
-		    ISH_GPIO_GFER & BIT(i)) {
-
-			/* Record the pin so we can restore it later */
-			both_edge_pins |= BIT(i);
-
-			if (ISH_GPIO_GPLR & BIT(i)) {
-				/* pin is high, just keep falling edge mode */
-				ISH_GPIO_GRER &= ~BIT(i);
-			} else {
-				/* pin is low, just keep rising edge mode */
-				ISH_GPIO_GFER &= ~BIT(i);
-			}
-		}
-	}
-
-	return both_edge_pins;
-}
-
-static void restore_both_edge_gpio_config(uint32_t both_edge_pin_map)
-{
-	ISH_GPIO_GRER |= both_edge_pin_map;
-	ISH_GPIO_GFER |= both_edge_pin_map;
-}
-
-static void enter_d0i1(void)
-{
-	uint64_t current_irq_map;
-	uint32_t both_edge_gpio_pins;
-	uint32_t t0, t1;
-
-	/* only enable PMU wakeup interrupt */
-	current_irq_map = disable_all_interrupts();
-	task_enable_irq(ISH_PMU_WAKEUP_IRQ);
-
-	if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP))
-		task_enable_irq(ISH_RESET_PREP_IRQ);
-
-	t0 = __hw_clock_source_read();
-	pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I1;
-
-	both_edge_gpio_pins = convert_both_edge_gpio_to_single_edge();
-
-	/* enable Trunk Clock Gating (TCG) of ISH */
-	CCU_TCG_EN = 1;
-
-	/* halt ISH cpu, will wakeup from PMU wakeup interrupt */
-	ish_mia_halt();
-
-	/* disable Trunk Clock Gating (TCG) of ISH */
-	CCU_TCG_EN = 0;
-
-	restore_both_edge_gpio_config(both_edge_gpio_pins);
-
-	pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0;
-	t1 = __hw_clock_source_read();
-	log_pm_stat(&pm_stats.d0i1, t0, t1);
-
-	/* Reload watchdog before enabling interrupts again */
-	watchdog_reload();
-
-	/* restore interrupts */
-	task_disable_irq(ISH_PMU_WAKEUP_IRQ);
-	restore_interrupts(current_irq_map);
-}
-
-static void enter_d0i2(void)
-{
-	uint64_t current_irq_map;
-	uint32_t both_edge_gpio_pins;
-	uint32_t t0, t1;
-
-	/* only enable PMU wakeup interrupt */
-	current_irq_map = disable_all_interrupts();
-	task_enable_irq(ISH_PMU_WAKEUP_IRQ);
-
-	if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP))
-		task_enable_irq(ISH_RESET_PREP_IRQ);
-
-	t0 = __hw_clock_source_read();
-	pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I2;
-
-	both_edge_gpio_pins = convert_both_edge_gpio_to_single_edge();
-
-	/* enable Trunk Clock Gating (TCG) of ISH */
-	CCU_TCG_EN = 1;
-
-	/* enable power gating of RF(Cache) and ROMs */
-	PMU_RF_ROM_PWR_CTRL = 1;
-
-	switch_to_aontask();
-
-	/* returned from aontask */
-
-	/* disable power gating of RF(Cache) and ROMs */
-	PMU_RF_ROM_PWR_CTRL = 0;
-
-	/* disable Trunk Clock Gating (TCG) of ISH */
-	CCU_TCG_EN = 0;
-
-	restore_both_edge_gpio_config(both_edge_gpio_pins);
-
-	t1 = __hw_clock_source_read();
-	pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0;
-	log_pm_stat(&pm_stats.d0i2, t0, t1);
-
-	/* Reload watchdog before enabling interrupts again */
-	watchdog_reload();
-
-	/* restore interrupts */
-	task_disable_irq(ISH_PMU_WAKEUP_IRQ);
-	restore_interrupts(current_irq_map);
-}
-
-static void enter_d0i3(void)
-{
-	uint64_t current_irq_map;
-	uint32_t both_edge_gpio_pins;
-	uint32_t t0, t1;
-
-	/* only enable PMU wakeup interrupt */
-	current_irq_map = disable_all_interrupts();
-	task_enable_irq(ISH_PMU_WAKEUP_IRQ);
-
-	if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP))
-		task_enable_irq(ISH_RESET_PREP_IRQ);
-
-	t0 = __hw_clock_source_read();
-	pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I3;
-
-	both_edge_gpio_pins = convert_both_edge_gpio_to_single_edge();
-
-	/* enable Trunk Clock Gating (TCG) of ISH */
-	CCU_TCG_EN = 1;
-
-	/* enable power gating of RF(Cache) and ROMs */
-	PMU_RF_ROM_PWR_CTRL = 1;
-
-	switch_to_aontask();
-
-	/* returned from aontask */
-
-	/* disable power gating of RF(Cache) and ROMs */
-	PMU_RF_ROM_PWR_CTRL = 0;
-
-	/* disable Trunk Clock Gating (TCG) of ISH */
-	CCU_TCG_EN = 0;
-
-	restore_both_edge_gpio_config(both_edge_gpio_pins);
-
-	t1 = __hw_clock_source_read();
-	pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0;
-	log_pm_stat(&pm_stats.d0i3, t0, t1);
-
-	/* Reload watchdog before enabling interrupts again */
-	watchdog_reload();
-
-	/* restore interrupts */
-	task_disable_irq(ISH_PMU_WAKEUP_IRQ);
-	restore_interrupts(current_irq_map);
-}
-
-static int d0ix_decide(timestamp_t cur_time, uint32_t idle_us)
-{
-	int pm_state = ISH_PM_STATE_D0I0;
-
-	if (DEEP_SLEEP_ALLOWED) {
-
-		/* check if the console use has expired. */
-		if (sleep_mask & SLEEP_MASK_CONSOLE) {
-			if (cur_time.val > pm_ctx.console_expire_time.val) {
-				enable_sleep(SLEEP_MASK_CONSOLE);
-				ccprints("Disabling console in deep sleep");
-			} else {
-				return pm_state;
-			}
-		}
-
-		if (IS_ENABLED(CONFIG_ISH_PM_D0I3) &&
-		    idle_us >= CONFIG_ISH_D0I3_MIN_USEC &&
-		    pm_ctx.aon_valid)
-			pm_state = ISH_PM_STATE_D0I3;
-
-		else if (IS_ENABLED(CONFIG_ISH_PM_D0I2) &&
-			 idle_us >= CONFIG_ISH_D0I2_MIN_USEC &&
-			 pm_ctx.aon_valid)
-			pm_state = ISH_PM_STATE_D0I2;
-
-		else if (IS_ENABLED(CONFIG_ISH_PM_D0I1))
-			pm_state = ISH_PM_STATE_D0I1;
-	}
-
-	return pm_state;
-}
-
-static void pm_process(timestamp_t cur_time, uint32_t idle_us)
-{
-	int decide;
-
-	decide = d0ix_decide(cur_time, idle_us);
-
-	switch (decide) {
-	case ISH_PM_STATE_D0I1:
-		enter_d0i1();
-		break;
-	case ISH_PM_STATE_D0I2:
-		enter_d0i2();
-		check_aon_task_status();
-		break;
-	case ISH_PM_STATE_D0I3:
-		enter_d0i3();
-		check_aon_task_status();
-		break;
-	default:
-		enter_d0i0();
-		break;
-	}
-}
-
-void ish_pm_init(void)
-{
-	/* clear reset bit */
-	ISH_RST_REG = 0;
-
-	/* clear reset history register in CCU */
-	CCU_RST_HST = CCU_RST_HST;
-
-	/* disable TCG and disable BCG */
-	CCU_TCG_EN = 0;
-	CCU_BCG_EN = 0;
-
-	if (IS_ENABLED(CONFIG_ISH_PM_AONTASK))
-		init_aon_task();
-
-	/* unmask all wake up events */
-	PMU_MASK_EVENT = ~PMU_MASK_EVENT_BIT_ALL;
-
-	if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) {
-		/* unmask reset prep avail interrupt */
-		PMU_RST_PREP = 0;
-
-		task_enable_irq(ISH_RESET_PREP_IRQ);
-	}
-
-	if (IS_ENABLED(CONFIG_ISH_PM_D3)) {
-		/* unmask D3 and BME interrupts */
-		PMU_D3_STATUS &= (PMU_D3_BIT_SET | PMU_BME_BIT_SET);
-
-		if ((!(PMU_D3_STATUS & PMU_D3_BIT_SET)) &&
-		    (PMU_D3_STATUS & PMU_BME_BIT_SET))
-			PMU_D3_STATUS = PMU_D3_STATUS;
-
-		task_enable_irq(ISH_D3_RISE_IRQ);
-		task_enable_irq(ISH_D3_FALL_IRQ);
-		task_enable_irq(ISH_BME_RISE_IRQ);
-		task_enable_irq(ISH_BME_FALL_IRQ);
-	}
-}
-
-__attribute__ ((noreturn))
-void ish_pm_reset(enum ish_pm_state pm_state)
-{
-	if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) &&
-	    pm_ctx.aon_valid) {
-		handle_reset_in_aontask(pm_state);
-	} else {
-		ish_mia_reset();
-	}
-
-	__builtin_unreachable();
-}
-
-void __idle(void)
-{
-	timestamp_t t0;
-	int next_delay = 0;
-
-	/**
-	 * initialize console in use to true and specify the console expire
-	 * time in order to give a fixed window on boot
-	 */
-	disable_sleep(SLEEP_MASK_CONSOLE);
-	pm_ctx.console_expire_time.val = get_time().val +
-					 CONSOLE_IN_USE_ON_BOOT_TIME;
-
-	while (1) {
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		/*
-		 * Most of the time, 'next_delay' will be positive. But, due to
-		 * interrupt latency, it's possible that get_time() returns
-		 * the value bigger than the one from __hw_clock_event_get()
-		 * which is supposed to be updated by ISR before control reaches
-		 * to the get_time().
-		 *
-		 * Here, we handle the delayed update by changing negative to 0.
-		 */
-		pm_process(t0, MAX(0, next_delay));
-	}
-}
-
-/*
- * helper for command_idle_stats
- */
-static void print_stats(const char *name, const struct pm_stat *stat)
-{
-	if (stat->count)
-		ccprintf("    %s:\n"
-			 "        counts: %llu\n"
-			 "        time:   %.6llus\n",
-			 name, stat->count, stat->total_time_us);
-}
-
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	struct ish_aon_share *aon_share = pm_ctx.aon_share;
-
-	ccprintf("Aontask exists: %s\n", pm_ctx.aon_valid ? "Yes" : "No");
-	ccprintf("Total time on: %.6llus\n", get_time().val);
-	ccprintf("Idle sleep:\n");
-	print_stats("D0i0", &pm_stats.d0i0);
-
-	ccprintf("Deep sleep:\n");
-	print_stats("D0i1", &pm_stats.d0i1);
-	print_stats("D0i2", &pm_stats.d0i2);
-	print_stats("D0i3", &pm_stats.d0i3);
-
-	if (pm_ctx.aon_valid) {
-		ccprintf("    Aontask status:\n");
-		ccprintf("        last error:   %u\n", aon_share->last_error);
-		ccprintf("        error counts: %u\n", aon_share->error_count);
-	}
-
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
-			"Print power management statistics");
-
-
-/**
- * main FW only need handle PMU wakeup interrupt for D0i1 state, aontask will
- * handle PMU wakeup interrupt for other low power states
- */
-__maybe_unused
-static void pmu_wakeup_isr(void)
-{
-	/* at current nothing need to do */
-}
-
-#ifdef CONFIG_ISH_PM_D0I1
-DECLARE_IRQ(ISH_PMU_WAKEUP_IRQ, pmu_wakeup_isr);
-#endif
-
-/**
- * from ISH5.0, when system doing S0->Sx transition, will receive reset prep
- * interrupt, will switch to aontask for handling
- *
- */
-
-__maybe_unused __attribute__ ((noreturn))
-static void reset_prep_isr(void)
-{
-	/* mask reset prep avail interrupt */
-	PMU_RST_PREP = PMU_RST_PREP_INT_MASK;
-
-	/*
-	 * Indicate completion of servicing the interrupt to IOAPIC first
-	 * then indicate completion of servicing the interrupt to LAPIC
-	 */
-	IOAPIC_EOI_REG = ISH_RESET_PREP_VEC;
-	LAPIC_EOI_REG = 0x0;
-
-	system_reset(0);
-	__builtin_unreachable();
-}
-
-#ifdef CONFIG_ISH_PM_RESET_PREP
-DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_isr);
-#endif
-
-__maybe_unused
-static void handle_d3(uint32_t irq_vec)
-{
-	PMU_D3_STATUS = PMU_D3_STATUS;
-
-	if (PMU_D3_STATUS & (PMU_D3_BIT_RISING_EDGE_STATUS | PMU_D3_BIT_SET)) {
-		/*
-		 * Indicate completion of servicing the interrupt to IOAPIC
-		 * first then indicate completion of servicing the interrupt
-		 * to LAPIC
-		 */
-		IOAPIC_EOI_REG = irq_vec;
-		LAPIC_EOI_REG = 0x0;
-
-		ish_persistent_data_commit();
-		ish_pm_reset(ISH_PM_STATE_D3);
-	}
-}
-
-static void d3_rise_isr(void)
-{
-	handle_d3(ISH_D3_RISE_VEC);
-}
-
-static void d3_fall_isr(void)
-{
-	handle_d3(ISH_D3_FALL_VEC);
-}
-
-static void bme_rise_isr(void)
-{
-	handle_d3(ISH_BME_RISE_VEC);
-}
-
-static void bme_fall_isr(void)
-{
-	handle_d3(ISH_BME_FALL_VEC);
-}
-
-#ifdef CONFIG_ISH_PM_D3
-DECLARE_IRQ(ISH_D3_RISE_IRQ, d3_rise_isr);
-DECLARE_IRQ(ISH_D3_FALL_IRQ, d3_fall_isr);
-DECLARE_IRQ(ISH_BME_RISE_IRQ, bme_rise_isr);
-DECLARE_IRQ(ISH_BME_FALL_IRQ, bme_fall_isr);
-#endif
-
-void ish_pm_refresh_console_in_use(void)
-{
-	disable_sleep(SLEEP_MASK_CONSOLE);
-
-	/* Set console in use expire time. */
-	pm_ctx.console_expire_time = get_time();
-	pm_ctx.console_expire_time.val +=
-				pm_ctx.console_in_use_timeout_sec * SECOND;
-}
diff --git a/chip/ish/power_mgt.h b/chip/ish/power_mgt.h
deleted file mode 100644
index d66bb96550..0000000000
--- a/chip/ish/power_mgt.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_POWER_MGT_H
-#define __CROS_EC_POWER_MGT_H
-
-#include "common.h"
-#include "registers.h"
-
-/* power states for ISH */
-enum ish_pm_state {
-	/* D0 state: active mode */
-	ISH_PM_STATE_D0 = 0,
-	/* sleep state: cpu halt */
-	ISH_PM_STATE_D0I0,
-	/* deep sleep state 1: Trunk Clock Gating(TCG), cpu halt*/
-	ISH_PM_STATE_D0I1,
-	/* deep sleep state 2: TCG, SRAM retention, cpu halt */
-	ISH_PM_STATE_D0I2,
-	/* deep sleep state 3: TCG, SRAM power off, cpu halt*/
-	ISH_PM_STATE_D0I3,
-	/**
-	 * D3 state: power off state, on ISH5.0, can't do real power off,
-	 * similar to D0I3, but will reset ISH
-	 */
-	ISH_PM_STATE_D3,
-	/**
-	 * reset ISH, main FW received 'reboot' command
-	 */
-	ISH_PM_STATE_RESET,
-	/**
-	 * reset ISH, main FW received reset_prep interrupt during
-	 * S0->Sx transition.
-	 */
-	ISH_PM_STATE_RESET_PREP,
-	ISH_PM_STATE_NUM
-};
-
-/* halt ISH minute-ia cpu core */
-static inline void ish_mia_halt(void)
-{
-	/* make sure interrupts are enabled before halting */
-	__asm__ volatile("sti;\n"
-			 "hlt;");
-}
-
-/* reset ISH mintue-ia cpu core  */
-__attribute__((noreturn))
-static inline void ish_mia_reset(void)
-{
-	/**
-	 * ISH HW looks at the rising edge of this bit to
-	 * trigger a MIA reset.
-	 */
-	ISH_RST_REG = 0;
-	ISH_RST_REG = 1;
-
-	__builtin_unreachable();
-}
-
-/* Initialize power management module. */
-#ifdef CONFIG_LOW_POWER_IDLE
-void ish_pm_init(void);
-#else
-__maybe_unused static void ish_pm_init(void)
-{
-}
-#endif
-
-/**
- * reset ISH (reset minute-ia cpu core, and power off main SRAM)
- */
-void ish_pm_reset(enum ish_pm_state pm_state) __attribute__((noreturn));
-
-/**
- * notify the power management module that the UART for the console is in use.
- */
-void ish_pm_refresh_console_in_use(void);
-
-#endif /* __CROS_EC_POWER_MGT_H */
diff --git a/chip/ish/registers.h b/chip/ish/registers.h
deleted file mode 100644
index d4ac2ea47a..0000000000
--- a/chip/ish/registers.h
+++ /dev/null
@@ -1,373 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Registers and interrupts for Intel(R) Integrated Sensor Hub
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#ifndef __ASSEMBLER__
-#include "common.h"
-#include "compile_time_macros.h"
-
-/* ISH GPIO has only one port */
-#define DUMMY_GPIO_BANK -1
-
-/*
- * ISH3.0 has 3 controllers. Locking must occur by-controller (not by-port).
- */
-enum ish_i2c_port {
-	ISH_I2C0   = 0,      /* Controller 0 */
-	ISH_I2C1   = 1,      /* Controller 1 */
-	ISH_I2C2   = 2,      /* Controller 2 */
-	I2C_PORT_COUNT,
-};
-
-#endif
-
-#define ISH_I2C_PORT_COUNT	I2C_PORT_COUNT
-
-/* In ISH, the devices are mapped to pre-defined addresses in the 32-bit
- * linear address space.
- */
-#ifdef CHIP_VARIANT_ISH5P4
-#define ISH_I2C0_BASE     0x00000000
-#define ISH_I2C1_BASE     0x00002000
-#define ISH_I2C2_BASE     0x00004000
-#define ISH_UART_BASE     0x08100000
-#define ISH_GPIO_BASE     0x00100000
-#define ISH_PMU_BASE      0x04200000
-#define ISH_OCP_BASE      0xFFFFFFFF
-#define ISH_MISC_BASE     0xFFFFFFFF
-#define ISH_DMA_BASE      0x10100000
-#define ISH_CCU_BASE      0x04300000
-#define ISH_IPC_BASE      0x04100000
-#define ISH_WDT_BASE      0x04900000
-#define ISH_IOAPIC_BASE   0xFEC00000
-#define ISH_HPET_BASE     0x04700000
-#define ISH_LAPIC_BASE    0xFEE00000
-#else
-#define ISH_I2C0_BASE     0x00100000
-#define ISH_I2C1_BASE     0x00102000
-#define ISH_I2C2_BASE     0x00105000
-#define ISH_UART_BASE     0x00103000
-#define ISH_GPIO_BASE     0x001F0000
-#define ISH_PMU_BASE      0x00800000
-#define ISH_OCP_BASE      0x00700000
-#define ISH_MISC_BASE     0x00C00000
-#define ISH_DMA_BASE      0x00400000
-#define ISH_CCU_BASE      0x00900000
-#define ISH_IPC_BASE      0x00B00000
-#define ISH_WDT_BASE      0xFDE00000
-#define ISH_IOAPIC_BASE   0xFEC00000
-#define ISH_HPET_BASE     0xFED00000
-#define ISH_LAPIC_BASE    0xFEE00000
-#endif
-
-/* HW interrupt pins mapped to IOAPIC, from I/O sources */
-#ifdef CHIP_VARIANT_ISH5P4
-#define ISH_I2C0_IRQ               15
-#define ISH_I2C1_IRQ               16
-#define ISH_FABRIC_IRQ             12
-#define ISH_I2C2_IRQ               17
-#define ISH_WDT_IRQ                26
-#define ISH_GPIO_IRQ               13
-#define ISH_HPET_TIMER1_IRQ        14
-#define ISH_IPC_HOST2ISH_IRQ       0
-#define ISH_PMU_WAKEUP_IRQ         10
-#define ISH_D3_RISE_IRQ            9
-#define ISH_D3_FALL_IRQ            9
-#define ISH_BME_RISE_IRQ           9
-#define ISH_BME_FALL_IRQ           9
-#define ISH_IPC_ISH2HOST_CLR_IRQ   0
-#define ISH_UART0_IRQ              23
-#define ISH_UART1_IRQ              24
-#define ISH_RESET_PREP_IRQ         6
-#else
-#define ISH_I2C0_IRQ               0
-#define ISH_I2C1_IRQ               1
-#define ISH_FABRIC_IRQ             5
-#define ISH_I2C2_IRQ               40
-#define ISH_WDT_IRQ                6
-#define ISH_GPIO_IRQ               7
-#define ISH_HPET_TIMER1_IRQ        8
-#define ISH_IPC_HOST2ISH_IRQ       12
-#define ISH_PMU_WAKEUP_IRQ         18
-#define ISH_D3_RISE_IRQ            19
-#define ISH_D3_FALL_IRQ            29
-#define ISH_BME_RISE_IRQ           50
-#define ISH_BME_FALL_IRQ           51
-#define ISH_IPC_ISH2HOST_CLR_IRQ   24
-#define ISH_UART0_IRQ              34
-#define ISH_UART1_IRQ              35
-#define ISH_RESET_PREP_IRQ         62
-#endif
-
-/* Interrupt vectors 0-31 are architecture reserved.
- * Vectors 32-255 are user-defined.
- */
-#define USER_VEC_START   32
-/* Map IRQs to vectors after offset 10 for certain APIC interrupts */
-#define IRQ_TO_VEC(irq)  ((irq) + USER_VEC_START + 10)
-#define VEC_TO_IRQ(vec)  ((vec) - USER_VEC_START - 10)
-
-/* ISH GPIO Registers */
-#define ISH_GPIO_GCCR REG32(ISH_GPIO_BASE + 0x000) /* Direction lock */
-#define ISH_GPIO_GPLR REG32(ISH_GPIO_BASE + 0x004) /* Pin level */
-#define ISH_GPIO_GPDR REG32(ISH_GPIO_BASE + 0x01C) /* Pin direction */
-#define ISH_GPIO_GPSR REG32(ISH_GPIO_BASE + 0x034) /* Output set */
-#define ISH_GPIO_GPCR REG32(ISH_GPIO_BASE + 0x04C) /* Output clear */
-#define ISH_GPIO_GRER REG32(ISH_GPIO_BASE + 0x064) /* Rising edge detect */
-#define ISH_GPIO_GFER REG32(ISH_GPIO_BASE + 0x07C) /* Falling edge detect */
-#define ISH_GPIO_GFBR REG32(ISH_GPIO_BASE + 0x094) /* Glitch Filter disable */
-#define ISH_GPIO_GIMR REG32(ISH_GPIO_BASE + 0x0AC) /* Interrupt Enable */
-#define ISH_GPIO_GISR REG32(ISH_GPIO_BASE + 0x0C4) /* Interrupt Source */
-#define ISH_GPIO_GWMR REG32(ISH_GPIO_BASE + 0x100) /* Wake Enable */
-#define ISH_GPIO_GWSR REG32(ISH_GPIO_BASE + 0x118) /* Wake Source */
-#define ISH_GPIO_GSEC REG32(ISH_GPIO_BASE + 0x130) /* Secure Input */
-
-/* APIC interrupt vectors */
-#define ISH_TS_VECTOR              0x20  /* Task switch vector */
-#define LAPIC_LVT_ERROR_VECTOR     0x21  /* Clears IOAPIC/LAPIC sync errors */
-#define SOFTIRQ_VECTOR             0x22  /* Handles software generated IRQs */
-#define LAPIC_SPURIOUS_INT_VECTOR  0xff
-
-/* Interrupt to vector mapping. To be programmed into IOAPIC */
-#define ISH_I2C0_VEC               IRQ_TO_VEC(ISH_I2C0_IRQ)
-#define ISH_I2C1_VEC               IRQ_TO_VEC(ISH_I2C1_IRQ)
-#define ISH_I2C2_VEC               IRQ_TO_VEC(ISH_I2C2_IRQ)
-#define ISH_WDT_VEC                IRQ_TO_VEC(ISH_WDT_IRQ)
-#define ISH_GPIO_VEC               IRQ_TO_VEC(ISH_GPIO_IRQ)
-#define ISH_HPET_TIMER1_VEC        IRQ_TO_VEC(ISH_HPET_TIMER1_IRQ)
-#define ISH_IPC_ISH2HOST_CLR_VEC   IRQ_TO_VEC(ISH_IPC_ISH2HOST_CLR_IRQ)
-#define ISH_UART0_VEC              IRQ_TO_VEC(ISH_UART0_IRQ)
-#define ISH_UART1_VEC              IRQ_TO_VEC(ISH_UART1_IRQ)
-#define ISH_IPC_VEC                IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ)
-#define ISH_RESET_PREP_VEC         IRQ_TO_VEC(ISH_RESET_PREP_IRQ)
-#define ISH_PMU_WAKEUP_VEC         IRQ_TO_VEC(ISH_PMU_WAKEUP_IRQ)
-#define ISH_D3_RISE_VEC            IRQ_TO_VEC(ISH_D3_RISE_IRQ)
-#define ISH_D3_FALL_VEC            IRQ_TO_VEC(ISH_D3_FALL_IRQ)
-#define ISH_BME_RISE_VEC           IRQ_TO_VEC(ISH_BME_RISE_IRQ)
-#define ISH_BME_FALL_VEC           IRQ_TO_VEC(ISH_BME_FALL_IRQ)
-#define ISH_FABRIC_VEC             IRQ_TO_VEC(ISH_FABRIC_IRQ)
-
-#define ISH_DEBUG_UART			UART_PORT_0
-#define ISH_DEBUG_UART_IRQ		ISH_UART0_IRQ
-#define ISH_DEBUG_UART_VEC		ISH_UART0_VEC
-
-/* IPC_Registers */
-#define IPC_PISR			REG32(ISH_IPC_BASE + 0x0)
-#define IPC_PISR_HOST2ISH_BIT		BIT(0)
-
-#define IPC_PIMR			REG32(ISH_IPC_BASE + 0x4)
-#define IPC_PIMR_HOST2ISH_BIT		BIT(0)
-#define IPC_PIMR_ISH2HOST_CLR_BIT	BIT(11)
-#define IPC_PIMR_CSME_CSR_BIT		BIT(23)
-#define IPC_ISH2HOST_MSG_BASE		REG8_ADDR(ISH_IPC_BASE + 0x60)
-#define IPC_ISH_FWSTS			REG32(ISH_IPC_BASE + 0x34)
-#define IPC_HOST2ISH_DOORBELL_ADDR	REG32_ADDR(ISH_IPC_BASE + 0x48)
-#define IPC_HOST2ISH_MSG_BASE		REG8_ADDR(ISH_IPC_BASE + 0xE0)
-#define IPC_ISH2HOST_DOORBELL_ADDR	REG32_ADDR(ISH_IPC_BASE + 0x54)
-#define IPC_ISH2PMC_DOORBELL		REG32(ISH_IPC_BASE + 0x58)
-#define IPC_ISH2PMC_MSG_BASE		(ISH_IPC_BASE + 0x260)
-#define IPC_ISH_RMP0			REG32(ISH_IPC_BASE + 0x360)
-#define IPC_ISH_RMP1			REG32(ISH_IPC_BASE + 0x364)
-#define IPC_ISH_RMP2			REG32(ISH_IPC_BASE + 0x368)
-#define DMA_ENABLED_MASK		BIT(0)
-#define IPC_BUSY_CLEAR			REG32(ISH_IPC_BASE + 0x378)
-#define IPC_DB_CLR_STS_ISH2HOST_BIT	BIT(0)
-
-#define IPC_UMA_RANGE_LOWER_0		REG32(ISH_IPC_BASE + 0x380)
-#define IPC_UMA_RANGE_LOWER_1		REG32(ISH_IPC_BASE + 0x384)
-#define IPC_UMA_RANGE_UPPER_0		REG32(ISH_IPC_BASE + 0x388)
-#define IPC_UMA_RANGE_UPPER_1		REG32(ISH_IPC_BASE + 0x38C)
-
-/* PMU Registers */
-#define PMU_SRAM_PG_EN			REG32(ISH_PMU_BASE + 0x0)
-#define PMU_D3_STATUS			REG32(ISH_PMU_BASE + 0x4)
-#define PMU_D3_BIT_SET			BIT(0)
-#define PMU_D3_BIT_RISING_EDGE_STATUS	BIT(1)
-#define PMU_D3_BIT_FALLING_EDGE_STATUS	BIT(2)
-#define PMU_D3_BIT_RISING_EDGE_MASK	BIT(3)
-#define PMU_D3_BIT_FALLING_EDGE_MASK	BIT(4)
-#define PMU_BME_BIT_SET		BIT(5)
-#define PMU_BME_BIT_RISING_EDGE_STATUS	BIT(6)
-#define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(7)
-#define PMU_BME_BIT_RISING_EDGE_MASK	BIT(8)
-#define PMU_BME_BIT_FALLING_EDGE_MASK	BIT(9)
-#define PMU_VNN_REQ			REG32(ISH_PMU_BASE + 0x3c)
-#define VNN_REQ_IPC_HOST_WRITE		BIT(3) /* Power for IPC host write */
-
-#define PMU_VNN_REQ_ACK		REG32(ISH_PMU_BASE + 0x40)
-#define PMU_VNN_REQ_ACK_STATUS		BIT(0) /* VNN req and ack status */
-
-#define PMU_RST_PREP			REG32(ISH_PMU_BASE + 0x5c)
-#define PMU_RST_PREP_GET		BIT(0)
-#define PMU_RST_PREP_AVAIL		BIT(1)
-#define PMU_RST_PREP_INT_MASK		BIT(31)
-
-#define VNN_ID_DMA0             4
-#define VNN_ID_DMA(chan)        (VNN_ID_DMA0 + chan)
-
-/* OCP registers */
-#define OCP_IOSF2OCP_BRIDGE      (ISH_OCP_BASE + 0x9400)
-#define OCP_AGENT_CONTROL        REG32(OCP_IOSF2OCP_BRIDGE + 0x20)
-#define OCP_RESPONSE_TO_DISABLE  0xFFFFF8FF
-
-/* MISC registers */
-#define MISC_REG_BASE            ISH_MISC_BASE
-#define MISC_CHID_CFG_REG        REG32(MISC_REG_BASE + 0x40)
-#define MISC_DMA_CTL_REG(ch)     REG32(MISC_REG_BASE + (4 * (ch)))
-#define MISC_SRC_FILLIN_DMA(ch)  REG32(MISC_REG_BASE + 0x20 + (4 * (ch)))
-#define MISC_DST_FILLIN_DMA(ch)  REG32(MISC_REG_BASE + 0x80 + (4 * (ch)))
-#define MISC_ISH_ECC_ERR_SRESP   REG32(MISC_REG_BASE + 0x94)
-
-/* DMA registers */
-#define DMA_REG_BASE                  ISH_DMA_BASE
-#define DMA_CH_REGS_SIZE              0x58
-#define DMA_CLR_BLOCK_REG             REG32(DMA_REG_BASE + 0x340)
-#define DMA_CLR_ERR_REG               REG32(DMA_REG_BASE + 0x358)
-#define DMA_EN_REG_ADDR               (DMA_REG_BASE + 0x3A0)
-#define DMA_EN_REG                    REG32(DMA_EN_REG_ADDR)
-#define DMA_CFG_REG                   REG32(DMA_REG_BASE + 0x398)
-#define DMA_PSIZE_01                  REG32(DMA_REG_BASE + 0x400)
-#define DMA_PSIZE_CHAN0_SIZE          512
-#define DMA_PSIZE_CHAN0_OFFSET        0
-#define DMA_PSIZE_CHAN1_SIZE          128
-#define DMA_PSIZE_CHAN1_OFFSET        13
-#define DMA_PSIZE_UPDATE	      BIT(26)
-#define DMA_MAX_CHANNEL               4
-#define DMA_SAR(chan)                 REG32(chan + 0x000)
-#define DMA_DAR(chan)                 REG32(chan + 0x008)
-#define DMA_LLP(chan)                 REG32(chan + 0x010)
-#define DMA_CTL_LOW(chan)             REG32(chan + 0x018)
-#define DMA_CTL_HIGH(chan)            REG32(chan + 0x018 + 0x4)
-#define DMA_CTL_INT_ENABLE	      BIT(0)
-#define DMA_CTL_DST_TR_WIDTH_SHIFT    1
-#define DMA_CTL_SRC_TR_WIDTH_SHIFT    4
-#define DMA_CTL_DINC_SHIFT            7
-#define DMA_CTL_SINC_SHIFT            9
-#define DMA_CTL_ADDR_INC              0
-#define DMA_CTL_DEST_MSIZE_SHIFT      11
-#define DMA_CTL_SRC_MSIZE_SHIFT       14
-#define DMA_CTL_TT_FC_SHIFT           20
-#define DMA_CTL_TT_FC_M2M_DMAC        0
-#define DMA_ENABLE		      BIT(0)
-#define DMA_CH_EN_BIT(n)	      BIT(n)
-#define DMA_CH_EN_WE_BIT(n)	      BIT(8 + (n))
-#define DMA_MAX_BLOCK_SIZE	      (4096)
-#define SRC_TR_WIDTH                  2
-#define SRC_BURST_SIZE                3
-#define DEST_TR_WIDTH                 2
-#define DEST_BURST_SIZE               3
-
-#define PMU_MASK_EVENT			REG32(ISH_PMU_BASE + 0x10)
-#define PMU_MASK_EVENT_BIT_GPIO(pin)	BIT(pin)
-#define PMU_MASK_EVENT_BIT_HPET	BIT(16)
-#define PMU_MASK_EVENT_BIT_IPC		BIT(17)
-#define PMU_MASK_EVENT_BIT_D3		BIT(18)
-#define PMU_MASK_EVENT_BIT_DMA		BIT(19)
-#define PMU_MASK_EVENT_BIT_I2C0	BIT(20)
-#define PMU_MASK_EVENT_BIT_I2C1	BIT(21)
-#define PMU_MASK_EVENT_BIT_SPI		BIT(22)
-#define PMU_MASK_EVENT_BIT_UART	BIT(23)
-#define PMU_MASK_EVENT_BIT_ALL		(0xffffffff)
-
-#define PMU_RF_ROM_PWR_CTRL		REG32(ISH_PMU_BASE + 0x30)
-
-#define PMU_LDO_CTRL			REG32(ISH_PMU_BASE + 0x44)
-#define PMU_LDO_ENABLE_BIT		BIT(0)
-#define PMU_LDO_RETENTION_BIT		BIT(1)
-#define PMU_LDO_CALIBRATION_BIT	BIT(2)
-#define PMU_LDO_READY_BIT		BIT(3)
-
-/* CCU Registers */
-#define CCU_TCG_EN		REG32(ISH_CCU_BASE + 0x0)
-#define CCU_BCG_EN		REG32(ISH_CCU_BASE + 0x4)
-#define CCU_WDT_CD		REG32(ISH_CCU_BASE + 0x8)
-#define CCU_RST_HST		REG32(ISH_CCU_BASE + 0x34) /* Reset history */
-#define CCU_TCG_ENABLE		REG32(ISH_CCU_BASE + 0x38)
-#define CCU_BCG_ENABLE		REG32(ISH_CCU_BASE + 0x3c)
-#define CCU_BCG_BIT_MIA	BIT(0)
-#define CCU_BCG_BIT_DMA	BIT(1)
-#define CCU_BCG_BIT_I2C0	BIT(2)
-#define CCU_BCG_BIT_I2C1	BIT(3)
-#define CCU_BCG_BIT_SPI	BIT(4)
-#define CCU_BCG_BIT_SRAM	BIT(5)
-#define CCU_BCG_BIT_HPET	BIT(6)
-#define CCU_BCG_BIT_UART	BIT(7)
-#define CCU_BCG_BIT_GPIO	BIT(8)
-#define CCU_BCG_BIT_I2C2	BIT(9)
-#define CCU_BCG_BIT_SPI2	BIT(10)
-#define CCU_BCG_BIT_ALL	(0x7ff)
-
-/* Bitmasks for CCU_RST_HST */
-#define CCU_SW_RST	BIT(0)  /* Used to indicate SW reset */
-#define CCU_WDT_RST	BIT(1)  /* Used to indicate WDT reset */
-#define CCU_MIASS_RST	BIT(2)  /* Used to indicate UIA shutdown reset */
-#define CCU_SRECC_RST	BIT(3)  /* Used to indicate SRAM ECC reset */
-
-/* Fabric Agent Status register */
-#define FABRIC_AGENT_STATUS		REG32(ISH_OCP_BASE + 0x7828)
-#define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29)
-#define FABRIC_INBAND_ERR_PRIMARY_BIT	BIT(28)
-#define FABRIC_M_ERR_BIT		BIT(24)
-#define FABRIC_MIA_STATUS_BIT_ERR	(FABRIC_INBAND_ERR_SECONDARY_BIT | \
-					 FABRIC_INBAND_ERR_PRIMARY_BIT | \
-					 FABRIC_M_ERR_BIT)
-
-/* CSME Registers */
-#ifdef CHIP_VARIANT_ISH5P4
-#define SEC_OFFSET			0x10000
-#else
-#define SEC_OFFSET			0x0
-#endif
-#define ISH_RST_REG			REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44)
-
-/* IOAPIC registers */
-#define IOAPIC_IDX			REG32(ISH_IOAPIC_BASE + 0x0)
-#define IOAPIC_WDW			REG32(ISH_IOAPIC_BASE + 0x10)
-/* Bare address needed for assembler (ISH_IOAPIC_BASE + 0x40) */
-#define IOAPIC_EOI_REG_ADDR		0xFEC00040
-#define IOAPIC_EOI_REG			REG32(IOAPIC_EOI_REG_ADDR)
-
-#define IOAPIC_VERSION			(0x1)
-#define IOAPIC_IOREDTBL			(0x10)
-#define IOAPIC_REDTBL_DELMOD_FIXED	(0x00000000)
-#define IOAPIC_REDTBL_DESTMOD_PHYS	(0x00000000)
-#define IOAPIC_REDTBL_INTPOL_HIGH	(0x00000000)
-#define IOAPIC_REDTBL_INTPOL_LOW	(0x00002000)
-#define IOAPIC_REDTBL_IRR		(0x00004000)
-#define IOAPIC_REDTBL_TRIGGER_EDGE	(0x00000000)
-#define IOAPIC_REDTBL_TRIGGER_LEVEL	(0x00008000)
-#define IOAPIC_REDTBL_MASK		(0x00010000)
-
-/* WDT (Watchdog Timer) Registers */
-#define WDT_CONTROL			REG32(ISH_WDT_BASE + 0x0)
-#define WDT_RELOAD			REG32(ISH_WDT_BASE + 0x4)
-#define WDT_VALUES			REG32(ISH_WDT_BASE + 0x8)
-#define WDT_CONTROL_ENABLE_BIT		BIT(17)
-
-/* LAPIC registers */
-/* Bare address needed for assembler (ISH_LAPIC_BASE + 0xB0) */
-#define LAPIC_EOI_REG_ADDR		0xFEE000B0
-#define LAPIC_EOI_REG			REG32(LAPIC_EOI_REG_ADDR)
-#define LAPIC_ISR_REG			REG32(ISH_LAPIC_BASE + 0x100)
-#define LAPIC_ISR_LAST_REG		REG32(ISH_LAPIC_BASE + 0x170)
-#define LAPIC_IRR_REG			REG32(ISH_LAPIC_BASE + 0x200)
-#define LAPIC_ESR_REG			REG32(ISH_LAPIC_BASE + 0x280)
-#define LAPIC_ERR_RECV_ILLEGAL		BIT(6)
-#define LAPIC_ICR_REG			REG32(ISH_LAPIC_BASE + 0x300)
-
-/* SRAM control registers */
-#define ISH_SRAM_CTRL_BASE		0x00500000
-#define ISH_SRAM_CTRL_CSFGR		REG32(ISH_SRAM_CTRL_BASE + 0x00)
-#define ISH_SRAM_CTRL_INTR		REG32(ISH_SRAM_CTRL_BASE + 0x04)
-#define ISH_SRAM_CTRL_INTR_MASK	REG32(ISH_SRAM_CTRL_BASE + 0x08)
-#define ISH_SRAM_CTRL_ERASE_CTRL	REG32(ISH_SRAM_CTRL_BASE + 0x0c)
-#define ISH_SRAM_CTRL_ERASE_ADDR	REG32(ISH_SRAM_CTRL_BASE + 0x10)
-#define ISH_SRAM_CTRL_BANK_STATUS	REG32(ISH_SRAM_CTRL_BASE + 0x2c)
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/ish/reset_prep_wr.c b/chip/ish/reset_prep_wr.c
deleted file mode 100644
index c192fb3723..0000000000
--- a/chip/ish/reset_prep_wr.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Workaround for ISH5.4 reset prep handling before full PM is enabled */
-#include "common.h"
-#include "hooks.h"
-#include "interrupts.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-
-/*
- * IRQ fires when we receive a RESET_PREP message from AP. This happens at S0
- * entry.
- */
-static void reset_prep_wr_isr(void)
-{
-	system_reset(SYSTEM_RESET_HARD);
-}
-DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_wr_isr);
-
-void reset_prep_init(void)
-{
-	/* Clear reset bit */
-	ISH_RST_REG = 0;
-
-	/* Clear reset history register from previous boot. */
-	CCU_RST_HST = CCU_RST_HST;
-	/* Unmask reset prep avail interrupt mask */
-	PMU_RST_PREP = 0;
-	/* Clear TCG Enable, no trunk level clock gating*/
-	CCU_TCG_ENABLE = 0;
-	/* Clear BCG Enable, no block level clock gating*/
-	CCU_BCG_ENABLE = 0;
-
-	task_enable_irq(ISH_RESET_PREP_IRQ);
-}
-DECLARE_HOOK(HOOK_INIT, reset_prep_init, HOOK_PRIO_DEFAULT);
diff --git a/chip/ish/system.c b/chip/ish/system.c
deleted file mode 100644
index 280bf57fa4..0000000000
--- a/chip/ish/system.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "interrupts.h"
-#include "ish_fwst.h"
-#include "ish_persistent_data.h"
-#include "power_mgt.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-int system_is_reboot_warm(void)
-{
-	return !(system_get_reset_flags() &
-		 (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_HARD));
-}
-
-void system_pre_init(void)
-{
-	ish_fwst_set_fw_status(FWSTS_FW_IS_RUNNING);
-	if (IS_ENABLED(CONFIG_ISH_CLEAR_FABRIC_ERRORS))
-		task_enable_irq(ISH_FABRIC_IRQ);
-	ish_pm_init();
-	ish_persistent_data_init();
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	ish_persistent_data.reset_flags = flags;
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return ish_persistent_data.reset_flags;
-}
-
-/*
- * Kill the Minute-IA core and don't come back alive.
- *
- * Used when the watchdog timer exceeds max retries and we want to
- * disable ISH completely.
- */
-__attribute__((noreturn))
-static void system_halt(void)
-{
-	cflush();
-
-	while (1) {
-		disable_all_interrupts();
-		WDT_CONTROL = 0;
-		CCU_TCG_EN = 1;
-		__asm__ volatile (
-			"cli\n"
-			"hlt\n");
-	}
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags;
-
-	/*
-	 * We can't save any data when we do an ish_mia_reset(). Take
-	 * the quick path out.
-	 */
-	if (!IS_ENABLED(CONFIG_ISH_PM_AONTASK) || flags & SYSTEM_RESET_HARD) {
-		ish_mia_reset();
-		__builtin_unreachable();
-	}
-
-	system_encode_save_flags(flags, &save_flags);
-
-	if (flags & SYSTEM_RESET_AP_WATCHDOG) {
-		save_flags |= EC_RESET_FLAG_WATCHDOG;
-		ish_persistent_data.watchdog_counter += 1;
-		if (ish_persistent_data.watchdog_counter
-		    >= CONFIG_WATCHDOG_MAX_RETRIES) {
-			CPRINTS("Halting ISH due to max watchdog resets");
-			system_halt();
-		}
-	}
-
-	chip_save_reset_flags(save_flags);
-
-	ish_persistent_data_commit();
-	ish_pm_reset(ISH_PM_STATE_RESET);
-	__builtin_unreachable();
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "intel";
-}
-
-const char *system_get_chip_name(void)
-{
-	return "intel";
-}
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char buf[3];
-	uint8_t rev = 0x86;
-
-	buf[0] = to_hex(rev / 16);
-	buf[1] = to_hex(rev & 0xf);
-	buf[2] = '\0';
-	return buf;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	return EC_SUCCESS;
-}
-
-uint32_t system_get_scratchpad(void)
-{
-	return 0;
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-}
-
-void htimer_interrupt(void)
-{
-	/* Time to wake up */
-}
-
-enum system_image_copy_t system_get_shrspi_image_copy(void)
-{
-	return 0;
-}
-
-uint32_t system_get_lfw_address(void)
-{
-	return 0;
-}
-
-void system_set_image_copy(enum system_image_copy_t copy)
-{
-}
-
-static __maybe_unused void fabric_isr(void)
-{
-	/**
-	 * clear fabric error status, otherwise it will wakeup ISH immediately
-	 * when entered low power mode.
-	 * TODO(b:130740646): figure out why this issue happens.
-	 */
-	if (FABRIC_AGENT_STATUS & FABRIC_MIA_STATUS_BIT_ERR)
-		FABRIC_AGENT_STATUS = FABRIC_AGENT_STATUS;
-}
-#ifdef CONFIG_ISH_CLEAR_FABRIC_ERRORS
-DECLARE_IRQ(ISH_FABRIC_IRQ, fabric_isr);
-#endif
diff --git a/chip/ish/system_state.h b/chip/ish/system_state.h
deleted file mode 100644
index 20de1aaf4b..0000000000
--- a/chip/ish/system_state.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __SYSTEM_STATE_H
-#define __SYSTEM_STATE_H
-
-#define HECI_FIXED_SYSTEM_STATE_ADDR				13
-
-struct ss_subsys_device;
-
-struct system_state_callbacks {
-	int (*resume)(struct ss_subsys_device *ss_device);
-	int (*suspend)(struct ss_subsys_device *ss_device);
-};
-
-struct ss_subsys_device {
-	struct system_state_callbacks *cbs;
-};
-
-/* register system state client */
-int ss_subsys_register_client(struct ss_subsys_device *ss_device);
-
-/*
- * this function is called by HECI layer when there's a message for
- * system state subsystem
- */
-void heci_handle_system_state_msg(uint8_t *msg, const size_t length);
-
-#endif /* __SYSTEM_STATE_H */
diff --git a/chip/ish/system_state_subsys.c b/chip/ish/system_state_subsys.c
deleted file mode 100644
index 36b79c747a..0000000000
--- a/chip/ish/system_state_subsys.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "heci_client.h"
-#include "registers.h"
-#include "system_state.h"
-#include "console.h"
-
-#ifdef SS_SUBSYSTEM_DEBUG
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-#else
-#define CPUTS(outstr)
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-#endif
-
-
-/* the following "define"s and structures are from host driver
- * and they are slightly modified for look&feel purpose.
- */
-#define SYSTEM_STATE_SUBSCRIBE		0x1
-#define SYSTEM_STATE_STATUS		0x2
-#define SYSTEM_STATE_QUERY_SUBSCRIBERS	0x3
-#define SYSTEM_STATE_STATE_CHANGE_REQ	0x4
-
-#define SUSPEND_STATE_BIT		BIT(1) /* suspend/resume */
-
-/* Cached state of ISH's requested power rails when AP suspends */
-static uint32_t cached_vnn_request;
-
-struct ss_header {
-	uint32_t cmd;
-	uint32_t cmd_status;
-} __packed;
-
-struct ss_query_subscribers {
-	struct ss_header hdr;
-} __packed;
-
-struct ss_subscribe {
-	struct ss_header hdr;
-	uint32_t states;
-} __packed;
-
-struct ss_status {
-	struct ss_header hdr;
-	uint32_t supported_states;
-	uint32_t states_status;
-} __packed;
-
-/* change request from device but host doesn't support it */
-struct ss_state_change_req {
-	struct ss_header hdr;
-	uint32_t requested_states;
-	uint32_t states_status;
-} __packed;
-
-/*
- * TODO: For now, every HECI client with valid .suspend or .resume callback is
- * automatically registered as client of system state subsystem.
- * so MAX_SS_CLIENTS should be HECI_MAX_NUM_OF_CLIENTS.
- * if an object wants to get system state event then it can embeds
- * "struct ss_subsys_device" in it and calls ss_subsys_register_client() like
- * HECI client.
- */
-#define MAX_SS_CLIENTS				HECI_MAX_NUM_OF_CLIENTS
-
-struct ss_subsystem_context {
-	uint32_t registered_state;
-
-	int num_of_ss_client;
-	struct ss_subsys_device *clients[MAX_SS_CLIENTS];
-};
-
-static struct ss_subsystem_context ss_subsys_ctx;
-
-int ss_subsys_register_client(struct ss_subsys_device *ss_device)
-{
-	int handle;
-
-	if (ss_subsys_ctx.num_of_ss_client == MAX_SS_CLIENTS)
-		return -1;
-
-	if (ss_device->cbs->resume || ss_device->cbs->suspend) {
-		handle = ss_subsys_ctx.num_of_ss_client++;
-		ss_subsys_ctx.registered_state |= SUSPEND_STATE_BIT;
-		ss_subsys_ctx.clients[handle] = ss_device;
-	} else {
-		return -1;
-	}
-
-	return handle;
-}
-
-static int ss_subsys_suspend(void)
-{
-	int i;
-
-	for (i = ss_subsys_ctx.num_of_ss_client - 1; i >= 0; i--) {
-		if (ss_subsys_ctx.clients[i]->cbs->suspend)
-			ss_subsys_ctx.clients[i]->cbs->suspend(
-						ss_subsys_ctx.clients[i]);
-	}
-
-	/*
-	 * PMU_VNN_REQ is used by ISH FW to assert power requirements of ISH to
-	 * PMC. The system won't enter S0ix if ISH is requesting any power
-	 * rails. Setting a bit to 1 both sets and clears a requested value.
-	 * Cache the value of request power so we can restore it on resume.
-	 */
-	if (IS_ENABLED(CHIP_FAMILY_ISH5)) {
-		cached_vnn_request = PMU_VNN_REQ;
-		PMU_VNN_REQ = cached_vnn_request;
-	}
-	return EC_SUCCESS;
-}
-
-static int ss_subsys_resume(void)
-{
-	int i;
-
-	/*
-	 * Restore VNN power request from before suspend.
-	 */
-	if (IS_ENABLED(CHIP_FAMILY_ISH5) &&
-	    cached_vnn_request) {
-		/* Request all cached power rails that are not already on. */
-		PMU_VNN_REQ = cached_vnn_request & ~PMU_VNN_REQ;
-		/* Wait for power request to get acknowledged */
-		while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS))
-			continue;
-	}
-
-	for (i = 0; i < ss_subsys_ctx.num_of_ss_client; i++) {
-		if (ss_subsys_ctx.clients[i]->cbs->resume)
-			ss_subsys_ctx.clients[i]->cbs->resume(
-						ss_subsys_ctx.clients[i]);
-	}
-
-	return EC_SUCCESS;
-}
-
-void heci_handle_system_state_msg(uint8_t *msg, const size_t length)
-{
-	struct ss_header *hdr = (struct ss_header *)msg;
-	struct ss_subscribe subscribe;
-	struct ss_status *status;
-
-	switch (hdr->cmd) {
-	case SYSTEM_STATE_QUERY_SUBSCRIBERS:
-		subscribe.hdr.cmd = SYSTEM_STATE_SUBSCRIBE;
-		subscribe.hdr.cmd_status = 0;
-		subscribe.states = ss_subsys_ctx.registered_state;
-
-		heci_send_fixed_client_msg(HECI_FIXED_SYSTEM_STATE_ADDR,
-					   (uint8_t *)&subscribe,
-					   sizeof(subscribe));
-
-		break;
-	case SYSTEM_STATE_STATUS:
-		status = (struct ss_status *)msg;
-		if (status->supported_states & SUSPEND_STATE_BIT) {
-			if (status->states_status & SUSPEND_STATE_BIT)
-				ss_subsys_suspend();
-			else
-				ss_subsys_resume();
-		}
-
-		break;
-	}
-}
diff --git a/chip/ish/uart.c b/chip/ish/uart.c
deleted file mode 100644
index 93df2c6504..0000000000
--- a/chip/ish/uart.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for ISH */
-#include "common.h"
-#include "math_util.h"
-#include "console.h"
-#include "uart_defs.h"
-#include "atomic.h"
-#include "task.h"
-#include "registers.h"
-#include "uart.h"
-#include "uart_defs.h"
-#include "interrupts.h"
-#include "system.h"
-
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-
-static const uint32_t baud_conf[][BAUD_TABLE_MAX] = {
-	{B9600, 9600},
-	{B57600, 57600},
-	{B115200, 115200},
-	{B921600, 921600},
-	{B2000000, 2000000},
-	{B3000000, 3000000},
-	{B3250000, 3250000},
-	{B3500000, 3500000},
-	{B4000000, 4000000},
-	{B19200, 19200},
-};
-
-static struct uart_ctx uart_ctx[UART_DEVICES] = {
-	{
-		.id = 0,
-		.base = UART0_BASE,
-		.input_freq = UART_ISH_INPUT_FREQ,
-		.addr_interval = UART_ISH_ADDR_INTERVAL,
-		.uart_state = UART_STATE_CG,
-	},
-	{
-		.id = 1,
-		.base = UART1_BASE,
-		.input_freq = UART_ISH_INPUT_FREQ,
-		.addr_interval = UART_ISH_ADDR_INTERVAL,
-		.uart_state = UART_STATE_CG,
-	},
-	{
-		.id = 2,
-		.base = UART2_BASE,
-		.input_freq = UART_ISH_INPUT_FREQ,
-		.addr_interval = UART_ISH_ADDR_INTERVAL,
-		.uart_state = UART_STATE_CG,
-	}
-};
-
-static int init_done;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	if (!IS_ENABLED(CONFIG_POLLING_UART)) {
-		if (IER(ISH_DEBUG_UART) & IER_TDRQ)
-			return;
-
-		/* Do not allow deep sleep while transmit in progress */
-		disable_sleep(SLEEP_MASK_UART);
-
-		IER(ISH_DEBUG_UART) |= IER_TDRQ;
-	}
-}
-
-void uart_tx_stop(void)
-{
-	if (!IS_ENABLED(CONFIG_POLLING_UART)) {
-		/* Re-allow deep sleep */
-		enable_sleep(SLEEP_MASK_UART);
-
-		IER(ISH_DEBUG_UART) &= ~IER_TDRQ;
-	}
-}
-
-void uart_tx_flush(void)
-{
-	if (!IS_ENABLED(CONFIG_POLLING_UART)) {
-		while (!(LSR(ISH_DEBUG_UART) & LSR_TEMT))
-			continue;
-	}
-}
-
-int uart_tx_ready(void)
-{
-	return LSR(ISH_DEBUG_UART) & LSR_TEMT;
-}
-
-int uart_rx_available(void)
-{
-	if (IS_ENABLED(CONFIG_POLLING_UART))
-		return 0;
-
-	return LSR(ISH_DEBUG_UART) & LSR_DR;
-}
-
-void uart_write_char(char c)
-{
-	/* Wait till receiver is ready */
-	while (!uart_tx_ready())
-		continue;
-
-	THR(ISH_DEBUG_UART) = c;
-}
-
-int uart_read_char(void)
-{
-	return RBR(ISH_DEBUG_UART);
-}
-
-void uart_ec_interrupt(void)
-{
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-}
-#ifndef CONFIG_POLLING_UART
-DECLARE_IRQ(ISH_DEBUG_UART_IRQ, uart_ec_interrupt);
-#endif
-
-static int uart_return_baud_rate_by_id(int baud_rate_id)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(baud_conf); i++) {
-		if (baud_conf[i][BAUD_IDX] == baud_rate_id)
-			return baud_conf[i][BAUD_SPEED];
-	}
-
-	return -1;
-}
-
-static void uart_hw_init(enum UART_PORT id)
-{
-	uint32_t divisor;	/* baud rate divisor */
-	uint8_t mcr = 0;
-	uint8_t fcr = 0;
-	struct uart_ctx *ctx = &uart_ctx[id];
-	uint8_t fraction;
-
-	/* Calculate baud rate divisor */
-	divisor = (ctx->input_freq / ctx->baud_rate) >> 4;
-	if (IS_ENABLED(CONFIG_ISH_DW_UART)) {
-		/* calculate the fractional part */
-		fraction = ceil_for(ctx->input_freq, ctx->baud_rate) - (divisor << 4);
-	} else {
-		MUL(ctx->id) = (divisor * ctx->baud_rate);
-		DIV(ctx->id) = (ctx->input_freq / 16);
-		PS(ctx->id) = 16;
-	}
-
-	/* Set the DLAB to access the baud rate divisor registers */
-	LCR(ctx->id) = LCR_DLAB;
-	DLL(ctx->id) = (divisor & 0xff);
-	DLH(ctx->id) = ((divisor >> 8) & 0xff);
-	if (IS_ENABLED(CONFIG_ISH_DW_UART))
-		DLF(ctx->id) = fraction;
-
-	/* 8 data bits, 1 stop bit, no parity, clear DLAB */
-	LCR(ctx->id) = LCR_8BIT_CHR;
-
-	if (ctx->client_flags & UART_CONFIG_HW_FLOW_CONTROL)
-		mcr = MCR_AUTO_FLOW_EN;
-
-	/* needs to be set regardless of flow control */
-	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
-		mcr |= MCR_INTR_ENABLE;
-
-	mcr |= (MCR_RTS | MCR_DTR);
-	MCR(ctx->id) = mcr;
-
-	if (IS_ENABLED(CONFIG_ISH_DW_UART))
-		fcr = FCR_TET_EMPTY | FCR_RT_1CHAR;
-	else
-		fcr = FCR_FIFO_SIZE_64 | FCR_ITL_FIFO_64_BYTES_1;
-
-	/* configure FIFOs */
-	FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE
-			| FCR_RESET_RX | FCR_RESET_TX);
-
-	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
-		/* enable UART unit */
-		ABR(ctx->id) = ABR_UUE;
-
-	/* clear the port */
-	RBR(ctx->id);
-
-	if (IS_ENABLED(CONFIG_POLLING_UART))
-		IER(ctx->id) = 0x00;
-	else
-		IER(ctx->id) = IER_RECV;
-}
-
-static void uart_stop_hw(enum UART_PORT id)
-{
-	int i;
-	uint32_t fifo_len;
-
-	if (!IS_ENABLED(CONFIG_ISH_DW_UART)) {
-		/* Manually clearing the fifo from possible noise.
-	 	 * Entering D0i3 when fifo is not cleared may result in a hang.
-	 	 */
-		fifo_len = (FOR(id) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS;
-
-		for (i = 0; i < fifo_len; i++)
-			(void)RBR(id);
-	}
-
-	/* No interrupts are enabled */
-	IER(id) = 0;
-	MCR(id) = 0;
-
-	/* Clear and disable FIFOs */
-	FCR(id) = (FCR_RESET_RX | FCR_RESET_TX);
-
-	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
-		/* Disable uart unit */
-		ABR(id) = 0;
-}
-
-static int uart_client_init(enum UART_PORT id, uint32_t baud_rate_id, int flags)
-{
-	if ((uart_ctx[id].base == 0) || (id >= UART_DEVICES))
-		return UART_ERROR;
-
-	if (!bool_compare_and_swap_u32(&uart_ctx[id].is_open, 0, 1))
-		return UART_BUSY;
-
-	uart_ctx[id].baud_rate = uart_return_baud_rate_by_id(baud_rate_id);
-
-	if ((uart_ctx[id].baud_rate == -1) || (uart_ctx[id].baud_rate == 0))
-		uart_ctx[id].baud_rate = UART_DEFAULT_BAUD_RATE;
-
-	uart_ctx[id].client_flags = flags;
-
-	atomic_and(&uart_ctx[id].uart_state, ~UART_STATE_CG);
-	uart_hw_init(id);
-
-	return EC_SUCCESS;
-}
-
-static void uart_drv_init(void)
-{
-	int i;
-
-	/* Disable UART */
-	for (i = 0; i < UART_DEVICES; i++)
-		uart_stop_hw(i);
-
-	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
-		/* Enable HSU global interrupts (DMA/U0/U1) and set PMEN bit
-	 	 * to allow PMU to clock gate ISH
-	 	 */
-		HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN
-				| GIEN_UART1_EN | GIEN_PWR_MGMT);
-
-	task_enable_irq(ISH_DEBUG_UART_IRQ);
-}
-
-void uart_init(void)
-{
-	uart_drv_init();
-	uart_client_init(ISH_DEBUG_UART, B115200, 0);
-	init_done = 1;
-}
diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h
deleted file mode 100644
index b573ef7710..0000000000
--- a/chip/ish/uart_defs.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for ISH */
-
-#ifndef __CROS_EC_UART_DEFS_H_
-#define __CROS_EC_UART_DEFS_H_
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define UART_ERROR		-1
-#define UART_BUSY		-2
-#ifdef CHIP_VARIANT_ISH5P4
-#define UART0_OFFS		(0x00)
-#define UART1_OFFS		(0x2000)
-#define UART2_OFFS		(0x4000)
-#else
-#define UART0_OFFS		(0x80)
-#define UART1_OFFS		(0x100)
-#define UART2_OFFS		(0x180)
-#endif
-
-#define HSU_BASE		ISH_UART_BASE
-#define UART0_BASE		(ISH_UART_BASE + UART0_OFFS)
-#define UART1_BASE		(ISH_UART_BASE + UART1_OFFS)
-#define UART2_BASE		(ISH_UART_BASE + UART2_OFFS)
-
-#define UART_REG(size, name, n)					\
-	REG##size(uart_ctx[n].base +					\
-		  UART_OFFSET_##name * uart_ctx[n].addr_interval)
-
-/* Register accesses */
-#define LSR(n)			UART_REG(8, LSR, n)
-#define THR(n)			UART_REG(8, THR, n)
-#define RBR(n)			UART_REG(8, RBR, n)
-#define DLL(n)			UART_REG(8, DLL, n)
-#define DLH(n)			UART_REG(8, DLH, n)
-#define IER(n)			UART_REG(8, IER, n)
-#define IIR(n)			UART_REG(8, IIR, n)
-#define FCR(n)			UART_REG(8, FCR, n)
-#define LCR(n)			UART_REG(8, LCR, n)
-#define MCR(n)			UART_REG(8, MCR, n)
-#define MSR(n)			UART_REG(8, MSR, n)
-#define DLF(n)			UART_REG(8, DLF, n)
-#define FOR(n)			UART_REG(32, FOR, n)
-#define ABR(n)			UART_REG(32, ABR, n)
-#define PS(n)			UART_REG(32, PS, n)
-#define MUL(n)			UART_REG(32, MUL, n)
-#define DIV(n)			UART_REG(32, DIV, n)
-
-#ifdef CONFIG_ISH_DW_UART
-/*
- * RBR: Receive Buffer register     (BLAB bit = 0)
- */
-#define UART_OFFSET_RBR		(0x00)
-
-/*
- * THR: Transmit Holding register   (BLAB bit = 0)
- */
-#define UART_OFFSET_THR		(0x00)
-
-/*
- * DLL: Divisor Latch Reg. low byte  (BLAB bit = 1)
- * baud rate = (serial clock freq) / (16 * divisor)
- */
-#define UART_OFFSET_DLL		(0x00)
-
-/*
- * DLH: Divisor Latch Reg. high byte (BLAB bit = 1)
- */
-#define UART_OFFSET_DLH		(0x04)
-
-/*
- * IER: Interrupt Enable register   (BLAB bit = 0)
- */
-#define UART_OFFSET_IER		(0x04)
-
-#define IER_RECV		(0x01)  /* Receive Data Available */
-#define IER_TDRQ		(0x02)  /* Transmit Holding Register Empty */
-#define IER_LINE_STAT		(0x04)  /* Receiver Line Status */
-#define IER_MODEM		(0x08)  /* Modem Status */
-#define IER_PTIME		(0x80)  /* Programmable THRE Interrupt Mode Enable */
-
-/*
- * IIR: Interrupt ID register
- */
-#define UART_OFFSET_IIR		(0x08)
-
-#define IIR_MODEM		(0x00)  /* Prio: 4 */
-#define IIR_NO_INTR		(0x01)
-#define IIR_THRE		(0x02)  /* Prio: 3 */
-#define IIR_RECV_DATA		(0x04)  /* Prio: 2 */
-#define IIR_LINE_STAT		(0x06)  /* Prio: 1 */
-#define IIR_BUSY		(0x07)  /* Prio: 5 */
-#define IIR_TIME_OUT		(0x0C)  /* Prio: 2 */
-#define IIR_SOURCE		(0x0F)
-
-
-/*
- * FCR: FIFO Control register (FIFO_MODE != NONE)
- */
-#define UART_OFFSET_FCR		(0x08)
-
-#define FIFO_SIZE		64
-#define FCR_FIFO_ENABLE		(0x01)
-#define FCR_RESET_RX		(0x02)
-#define FCR_RESET_TX		(0x04)
-#define FCR_DMA_MODE		(0x08)
-
-/*
- * LCR: Line Control register
- */
-#define UART_OFFSET_LCR		(0x0c)
-
-#define LCR_5BIT_CHR		(0x00)
-#define LCR_6BIT_CHR		(0x01)
-#define LCR_7BIT_CHR		(0x02)
-#define LCR_8BIT_CHR		(0x03)
-#define LCR_BIT_CHR_MASK	(0x03)
-
-#define LCR_STOP		BIT(2)  /* 0: 1 stop bit, 1: 1.5/2 */
-#define LCR_PEN			BIT(3)  /* Parity Enable */
-#define LCR_EPS			BIT(4)  /* Even Parity Select */
-#define LCR_SP			BIT(5)  /* Stick Parity */
-#define LCR_BC			BIT(6)  /* Break Control */
-#define LCR_DLAB		BIT(7)  /* Divisor Latch Access */
-
-/*
- * MCR: Modem Control register
- */
-#define UART_OFFSET_MCR		(0x10)
-#define MCR_DTR			(0x1)     /* Data terminal ready */
-#define MCR_RTS			(0x2)     /* Request to send */
-#define MCR_LOOP		(0x10)    /* LoopBack bit*/
-
-#define MCR_INTR_ENABLE		(0x08)    /* User-designated OUT2 */
-#define MCR_AUTO_FLOW_EN	(0x20)
-
-/*
- * LSR: Line Status register
- */
-#define UART_OFFSET_LSR		(0x14)
-
-#define LSR_DR			(0x01)         /* Data Ready */
-#define LSR_OE			(0x02)         /* Overrun error */
-#define LSR_PE			(0x04)         /* Parity error */
-#define LSR_FE			(0x08)         /* Framing error */
-#define LSR_BI			(0x10)         /* Breaking interrupt */
-#define LSR_TDRQ		(0x20)       /* Transmit Holding Register Empty */
-#define LSR_TEMT		(0x40)       /* Transmitter empty */
-
-/*
- * MSR: Modem Status register
- */
-#define UART_OFFSET_MSR		(0x18)
-
-#define MSR_CTS			BIT(4) /* Clear To Send signal */
-
-/*
- * TFL: Transmit FIFO Level
- */
-#define UART_OFFSET_TFL		(0x80)
-
-/*
- * RFL: Receive FIFO Level
- */
-#define UART_OFFSET_RFL		(0x84)
-#else
-/* RBR: Receive Buffer register     (BLAB bit = 0)  */
-#define UART_OFFSET_RBR	(0)
-/* THR: Transmit Holding register   (BLAB bit = 0)  */
-#define UART_OFFSET_THR	(0)
-/* IER: Interrupt Enable register   (BLAB bit = 0)  */
-#define UART_OFFSET_IER	(1)
-
-/* FCR: FIFO Control register */
-#define UART_OFFSET_FCR	(2)
-#define FCR_FIFO_ENABLE	BIT(0)
-#define FCR_RESET_RX		BIT(1)
-#define FCR_RESET_TX		BIT(2)
-
-/* LCR: Line Control register */
-#define UART_OFFSET_LCR	(3)
-#define LCR_DLAB		(0x80)
-#define LCR_5BIT_CHR		(0x00)
-#define LCR_6BIT_CHR		(0x01)
-#define LCR_7BIT_CHR		(0x02)
-#define LCR_8BIT_CHR		(0x03)
-#define LCR_BIT_CHR_MASK	(0x03)
-#define LCR_SB			(0x40)	/* Set Break */
-
-/* MCR: Modem Control register */
-#define UART_OFFSET_MCR	(4)
-#define MCR_DTR		BIT(0)
-#define MCR_RTS		BIT(1)
-#define MCR_LOO		BIT(4)
-#define MCR_INTR_ENABLE	BIT(3)
-#define MCR_AUTO_FLOW_EN	BIT(5)
-
-/* LSR: Line Status register */
-#define UART_OFFSET_LSR	(5)
-#define LSR_DR			BIT(0)	/* Data Ready */
-#define LSR_OE			BIT(1)	/* Overrun error */
-#define LSR_PE			BIT(2)	/* Parity error */
-#define LSR_FE			BIT(3)	/* Framing error */
-#define LSR_BI			BIT(4)	/* Breaking interrupt */
-#define LSR_THR_EMPTY		BIT(5)	/* Non FIFO mode: Transmit holding
-					 * register empty
-					 */
-#define LSR_TDRQ		BIT(5)	/* FIFO mode: Transmit Data request */
-#define LSR_TEMT		BIT(6)	/* Transmitter empty */
-
-#define FCR_ITL_FIFO_64_BYTES_56 (BIT(6) | BIT(7))
-
-#define IER_RECV		BIT(0)
-#define IER_TDRQ		BIT(1)
-#define IER_LINE_STAT		BIT(2)
-
-#define UART_OFFSET_IIR	(2)
-/* MSR: Modem Status register */
-#define UART_OFFSET_MSR	(6)
-
-/* DLL: Divisor Latch Reg. low byte  (BLAB bit = 1) */
-#define UART_OFFSET_DLL	(0)
-
-/* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */
-#define UART_OFFSET_DLH	(1)
-#endif
-
-/*
- * DLF: Divisor Latch Fraction Register
- */
-#define UART_OFFSET_DLF		(0xC0)
-
-/* FOR: Fifo O Register (ISH only) */
-#define UART_OFFSET_FOR	(0x20)
-#define FOR_OCCUPANCY_OFFS	0
-#define FOR_OCCUPANCY_MASK	0x7F
-
-/* ABR: Auto-Baud Control Register (ISH only) */
-#define UART_OFFSET_ABR	(0x24)
-#define ABR_UUE		BIT(4)
-
-/* Pre-Scalar Register (ISH only) */
-#define UART_OFFSET_PS		(0x30)
-
-/* DDS registers (ISH only) */
-#define UART_OFFSET_MUL	(0x34)
-#define UART_OFFSET_DIV	(0x38)
-
-#define FCR_FIFO_SIZE_16	(0x00)
-#define FCR_FIFO_SIZE_64	(0x20)
-#define FCR_ITL_FIFO_64_BYTES_1	(0x00)
-
-/* tx empty trigger(TET) */
-#define FCR_TET_EMPTY		(0x00)
-#define FCR_TET_2CHAR		(0x10)
-#define FCR_TET_QTR_FULL	(0x20)
-#define FCR_TET_HALF_FULL	(0x30)
-
-/* receive trigger(RT) */
-#define FCR_RT_1CHAR		(0x00)
-#define FCR_RT_QTR_FULL		(0x40)
-#define FCR_RT_HALF_FULL	(0x80)
-#define FCR_RT_2LESS_FULL	(0xc0)
-
-/* G_IEN: Global Interrupt Enable  (ISH only) */
-#define HSU_REG_GIEN		REG32(HSU_BASE + 0x0)
-#define HSU_REG_GIST		REG32(HSU_BASE + 0x4)
-
-#define GIEN_PWR_MGMT		BIT(24)
-#define GIEN_DMA_EN		BIT(5)
-#define GIEN_UART2_EN		BIT(2)
-#define GIEN_UART1_EN		BIT(1)
-#define GIEN_UART0_EN		BIT(0)
-#define GIST_DMA_EN		BIT(5)
-#define GIST_UART2_EN		BIT(2)
-#define GIST_UART1_EN		BIT(1)
-#define GIST_UART0_EN		BIT(0)
-#define GIST_UARTx_EN		(GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN)
-
-/* UART config flag, send to sc_io_control if the current UART line has HW
- * flow control lines connected.
- */
-#define UART_CONFIG_HW_FLOW_CONTROL		BIT(0)
-
-/* UART config flag for sc_io_control.  If defined a sc_io_event_rx_msg is
- * raised only when the rx buffer is completely full. Otherwise, the event
- * is raised after a timeout is received on the UART line,
- * and all data received until now is provided.
- */
-#define UART_CONFIG_DELIVER_FULL_RX_BUF	BIT(1)
-
-/* UART config flag for sc_io_control.  If defined a sc_io_event_rx_buf_depleted
- * is raised when all rx buffers that were added are full. Otherwise, no
- * event is raised.
- */
-#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF	BIT(2)
-
-#define UART_INT_DEVICES		3
-#define UART_EXT_DEVICES		8
-#define UART_DEVICES			UART_INT_DEVICES
-#define UART_ISH_ADDR_INTERVAL		1
-
-#define B9600				0x0000d
-#define B57600				0x00000018
-#define B115200			0x00000011
-#define B921600			0x00000012
-#define B2000000			0x00000013
-#define B3000000			0x00000014
-#define B3250000			0x00000015
-#define B3500000			0x00000016
-#define B4000000			0x00000017
-#define B19200				0x0000e
-#define B38400				0x0000f
-
-/* KHZ, MHZ */
-#define KHZ(x)				((x) * 1000)
-#define MHZ(x)				(KHZ(x) * 1000)
-#if defined(CHIP_VARIANT_ISH5P4)
-/* Change to 100MHZ in real silicon platform */
-#define UART_ISH_INPUT_FREQ		MHZ(100)
-#elif defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
-#define UART_ISH_INPUT_FREQ		MHZ(120)
-#elif defined(CHIP_FAMILY_ISH4)
-#define UART_ISH_INPUT_FREQ		MHZ(100)
-#endif
-#define UART_DEFAULT_BAUD_RATE		115200
-#define UART_STATE_CG			BIT(UART_OP_CG)
-
-enum UART_PORT {
-	UART_PORT_0,
-	UART_PORT_1,
-	UART_PORT_MAX
-};
-
-enum UART_OP {
-	UART_OP_READ,
-	UART_OP_WRITE,
-	UART_OP_CG,
-	UART_OP_MAX
-};
-
-enum {
-	BAUD_IDX,
-	BAUD_SPEED,
-	BAUD_TABLE_MAX
-};
-
-struct uart_ctx {
-	uint32_t id;
-	uint32_t base;
-	uint32_t addr_interval;
-	uint32_t uart_state;
-	uint32_t is_open;
-	uint32_t baud_rate;
-	uint32_t input_freq;
-	uint32_t client_flags;
-};
-
-#endif /* _CROS_EC_UART_DEFS_H_ */
diff --git a/chip/ish/util/pack_ec.py b/chip/ish/util/pack_ec.py
deleted file mode 100755
index 71a63dd42f..0000000000
--- a/chip/ish/util/pack_ec.py
+++ /dev/null
@@ -1,109 +0,0 @@
-#!/usr/bin/env python2
-# -*- coding: utf-8 -*-"
-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# A script to pack EC binary with manifest header according to
-# Based on 607297_Host_ISH_Firmware_Load_Chrome_OS_SAS_Rev0p5.pdf,
-# https://chrome-internal.googlesource.com/chromeos/intel-ish/+/refs/heads/upstream/master/modules/api/ish_api/include/loader_common.h#211,
-# and b/124788278#comment10
-
-"""Script to pack EC binary with manifest header.
-
-Package ecos main FW binary (kernel) and AON task binary into final EC binary
-image with a manifest header, ISH shim loader will parse this header and load
-each binaries into right memory location.
-"""
-
-from __future__ import print_function
-import argparse
-import struct
-
-MANIFEST_ENTRY_SIZE = 0x80
-HEADER_SIZE = 0x1000
-PAGE_SIZE = 0x1000
-
-def parseargs():
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-k", "--kernel",
-                      help="EC kernel binary to pack, \
-                      usually ec.RW.bin or ec.RW.flat.",
-                      required=True)
-  parser.add_argument("--kernel-size", type=int,
-                      help="Size of EC kernel image",
-                      required=True)
-  parser.add_argument("-a", "--aon",
-                      help="EC aontask binary to pack, \
-                      usually ish_aontask.bin.",
-                      required=False)
-  parser.add_argument("--aon-size", type=int,
-                      help="Size of EC aontask image",
-                      required=False)
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file")
-
-  return parser.parse_args()
-
-def gen_manifest(ext_id, comp_app_name, code_offset, module_size):
-  """Returns a binary blob that represents a manifest entry"""
-  m = bytearray(MANIFEST_ENTRY_SIZE)
-
-  # 4 bytes of ASCII encode ID (little endian)
-  struct.pack_into('<4s', m, 0, ext_id)
-  # 8 bytes of ASCII encode ID (little endian)
-  struct.pack_into('<8s', m, 32, comp_app_name)
-  # 4 bytes of code offset (little endian)
-  struct.pack_into('<I', m, 96, code_offset)
-  # 2 bytes of module in page size increments (little endian)
-  struct.pack_into('<H', m, 100, module_size)
-
-  return m
-
-def roundup_page(size):
-  """Returns roundup-ed page size from size of bytes"""
-  return int(size / PAGE_SIZE) + (size % PAGE_SIZE > 0)
-
-def main():
-  args = parseargs()
-  print("    Packing EC image file for ISH")
-
-  with open(args.output, 'wb') as f:
-    print("      kernel binary size: %i" % args.kernel_size)
-    kern_rdup_pg_size = roundup_page(args.kernel_size)
-    # Add manifest for main ISH binary
-    f.write(gen_manifest('ISHM', 'ISH_KERN', HEADER_SIZE, kern_rdup_pg_size))
-
-    if args.aon is not None:
-      print("      AON binary size:    %i" % args.aon_size)
-      aon_rdup_pg_size = roundup_page(args.aon_size)
-      # Add manifest for aontask binary
-      f.write(gen_manifest('ISHM', 'AON_TASK',
-                           (HEADER_SIZE + kern_rdup_pg_size * PAGE_SIZE -
-                            MANIFEST_ENTRY_SIZE), aon_rdup_pg_size))
-
-    # Add manifest that signals end of manifests
-    f.write(gen_manifest('ISHE', '', 0, 0))
-
-    # Pad the remaining HEADER with 0s
-    if args.aon is not None:
-      f.write('\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3)))
-    else:
-      f.write('\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2)))
-
-    # Append original kernel image
-    with open(args.kernel, 'rb') as in_file:
-      f.write(in_file.read())
-    # Filling padings due to size round up as pages
-    f.write('\x00' * (kern_rdup_pg_size * PAGE_SIZE - args.kernel_size))
-
-    if args.aon is not None:
-      # Append original aon image
-      with open(args.aon, 'rb') as in_file:
-        f.write(in_file.read())
-      # Filling padings due to size round up as pages
-      f.write('\x00' * (aon_rdup_pg_size * PAGE_SIZE - args.aon_size))
-
-if __name__ == '__main__':
-  main()
diff --git a/chip/ish/watchdog.c b/chip/ish/watchdog.c
deleted file mode 100644
index bf78f49312..0000000000
--- a/chip/ish/watchdog.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Watchdog Timer
- *
- * In ISH, there is a watchdog timer available from the hardware. It is
- * controlled by a few registers:
- *
- * - WDT_CONTROL (consists of enable bit, T1, and T2 values): When T1
- *   reaches 0, a warning is fired. After T2 then reaches 0, the system
- *   will reset.
- * - WDT_RELOAD: Pet the watchdog by setting to 1
- * - WDT_VALUES: Gives software access to T1 and T2 if needed
- *
- * For ISH implementation, we wish to reset only the ISH. Waiting until
- * T2 expires will kill the whole system. The functionality of T2 is
- * ignored, and we simply call system_reset when T1 expires. T2 will
- * only be used if the system cannot reset when T1 expires.
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "ish_persistent_data.h"
-#include "task.h"
-#include "registers.h"
-#include "system.h"
-#include "watchdog.h"
-
-/* Units are hundreds of milliseconds */
-#define WDT_T1_PERIOD		(100) /* 10 seconds */
-#define WDT_T2_PERIOD		(10)  /* 1 second */
-
-int watchdog_init(void)
-{
-	/*
-	 * Put reset counter back at zero if last reset was not caused
-	 * by watchdog
-	 */
-	if ((system_get_reset_flags() & EC_RESET_FLAG_WATCHDOG) == 0)
-		ish_persistent_data.watchdog_counter = 0;
-
-	/* Initialize WDT clock divider */
-	CCU_WDT_CD = WDT_CLOCK_HZ / 10; /* 10 Hz => 100 ms period */
-
-	/* Enable the watchdog timer and set initial T1/T2 values */
-	WDT_CONTROL = WDT_CONTROL_ENABLE_BIT
-		| (WDT_T2_PERIOD << 8)
-		| WDT_T1_PERIOD;
-
-	task_enable_irq(ISH_WDT_IRQ);
-
-	return EC_SUCCESS;
-}
-
-void watchdog_reload(void)
-{
-	/*
-	 * ISH Supplemental Registers Info, 1.2.6.2:
-	 * "When firmware writes a 1 to this bit, hardware reloads
-	 * the values in WDT_T1 and WDT_T2..."
-	 */
-	WDT_RELOAD = 1;
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);