diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2019-01-15 17:15:03 +0800 |
|---|---|---|
| committer | Justin TerAvest <teravest@chromium.org> | 2019-01-16 03:33:03 +0000 |
| commit | 21a6339d873770eb7dbcbf06c627a3da68b1b123 (patch) | |
| tree | c4e6abca8d40b7bbbb4169d6f2ab2e62860a3dd3 /chip/it83xx/clock.c | |
| parent | ce696d751f069d87f3e03340888e9fb213829918 (diff) | |
| download | chrome-ec-21a6339d873770eb7dbcbf06c627a3da68b1b123.tar.gz | |
it83xx: reset espi module during init on DX version
Symptom:
On Ampton, boot to kernel with coreboot image R73-11543.0.0 (eSPI
is operating at Quad I/O mode).
Reboot EC with console command "reboot", eSPI will get stuck after
power sequence is done.
Because I/O mode field will not go back to default setting
(single I/O mode) after a software reset.
BUG=b:122820812
BRANCH=octopus
TEST=Running "reboot" on the EC console and then boot to kernel.
Change-Id: I65252aa191294458467f3ba55b2071659f3b5ae8
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/1408752
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'chip/it83xx/clock.c')
| -rw-r--r-- | chip/it83xx/clock.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index 613b5db04d..c52edb6f6a 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -262,6 +262,16 @@ void clock_init(void) */ IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40; +#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && defined(CONFIG_HOSTCMD_ESPI) + /* + * Because we don't support eSPI HW reset function (b/111480168) on DX + * version, so we have to reset eSPI configurations during init to + * ensure Host and EC are synchronized (especially for the field of + * I/O mode) + */ + if (!system_jumped_to_this_image()) + espi_fw_reset_module(); +#endif /* Turn off auto clock gating. */ IT83XX_ECPM_AUTOCG = 0x00; |