diff options
| author | tim <tim2.lin@ite.corp-partner.google.com> | 2018-09-25 09:27:46 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-26 10:33:12 -0700 |
| commit | c042e22956acee71393205e38eae8b8f72458925 (patch) | |
| tree | 2bc2876237f8943fe90edfd228a1533c0b62ea7b /chip/it83xx/clock.c | |
| parent | 9e50f35372b8a351e9ca4f0b8159deeedb2bd00a (diff) | |
| download | chrome-ec-c042e22956acee71393205e38eae8b8f72458925.tar.gz | |
it83xx: add config for reading observation register of external timer issue
In IT8320 BX version, there is a chance of failure in reading
external timer observation register. We are using the time delay
of CPU in order to read register twice that can avoid the bug of
reading time failure when CPU and EC are counting at the same time.
There will be once successful read. The bug has been fixed in
the later version of chip.
BUG=none
BRANCH=none
TEST=Ensure the observation register of external timer will
be read successful in IT8320 DX chip.
Change-Id: I0ec2d0bb83afd1549118de9383dc16cf5adb6b5a
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1215523
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/clock.c')
| -rw-r--r-- | chip/it83xx/clock.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index b10a31d19f..6ab644912f 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -339,11 +339,10 @@ static void clock_htimer_enable(void) uint32_t c; /* change event timer clock source to 32.768 KHz */ -#if 0 - c = TIMER_CNT_8M_32P768K(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)); -#else - /* TODO(crosbug.com/p/55044) */ +#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES c = TIMER_CNT_8M_32P768K(ext_observation_reg_read(EVENT_EXT_TIMER)); +#else + c = TIMER_CNT_8M_32P768K(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)); #endif clock_event_timer_clock_change(EXT_PSR_32P768K_HZ, c); } @@ -357,11 +356,10 @@ static int clock_allow_low_power_idle(void) et_ctrl_regs[EVENT_EXT_TIMER].mask) return 0; -#if 0 - if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) < -#else - /* TODO(crosbug.com/p/55044) */ +#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES if (EVENT_TIMER_COUNT_TO_US(ext_observation_reg_read(EVENT_EXT_TIMER)) < +#else + if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) < #endif SLEEP_SET_HTIMER_DELAY_USEC) return 0; |