diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2019-01-10 19:13:47 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-01-11 23:54:30 -0800 |
| commit | 10d387175c90cb97cf5269091abfdb13e1f8f18a (patch) | |
| tree | f4fe6580484d81ba679576edd7e684524a2cb5c8 /chip/it83xx/clock.c | |
| parent | 1c132ac233dbed5b0cc07401eae66ffef7067b38 (diff) | |
| download | chrome-ec-10d387175c90cb97cf5269091abfdb13e1f8f18a.tar.gz | |
it83xx: disable eSPI pad before changing PLL
This change inhibits eSPI CS# pin's function by disabling pad
instead of turning VCC off. Because eSPI module will also reset
if we turn VCC off, but we just want to inhibits CS# function.
(eSPI module will be reset after sysjump if PLL setting of RO/RW
images are different.)
BUG=b:70537592
BRANCH=none
TEST=On Ampton, EC clock frequency is correct after changing PLL
sequence.
Change-Id: I263132aa6e94542b03afc840ede8527ea98e2927
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1404641
Commit-Ready: Justin TerAvest <teravest@chromium.org>
Tested-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/clock.c')
| -rw-r--r-- | chip/it83xx/clock.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index 12ec22f894..613b5db04d 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -200,20 +200,21 @@ static void clock_set_pll(enum pll_freq_idx idx) * change PLL. */ IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | (1 << 7); -#ifdef IT83XX_ESPI_INHIBIT_CS_BY_VCC_OFF +#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED /* - * On DX version, we have to turn off VCC before changing PLL - * sequence or sequence will fail if CS# pin is low. - * - * The VCC power status will be treated as power-on later in - * clock_init(). + * On DX version, we have to disable eSPI pad before changing + * PLL sequence or sequence will fail if CS# pin is low. */ - IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0); + IT83XX_ESPI_ESGCTRL2 |= (1 << 6); #endif #endif /* Update PLL settings. */ clock_pll_changed(); #ifdef CONFIG_HOSTCMD_ESPI +#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED + /* Enable eSPI pad after changing PLL sequence. */ + IT83XX_ESPI_ESGCTRL2 &= ~(1 << 6); +#endif /* (b:70537592) Change back to ESPI CS# function. */ IT83XX_GPIO_GPCRM5 &= ~0xc0; #endif |