it83xx/clock: turn off VCC before changing PLL

Symptom:
On Ampton board, EC's clock frequency is not correct after changing
PLL sequence.

We have added a workaround to fix changing PLL failure issue while
CS# pin's level is low, but it does not fix the issue on the DX version.
We need to turn off VCC power to fix this issue on the DX.

BUG=b:70537592
BRANCH=none
TEST=EC clock frequency is correct on DX version after changing PLL
     sequence.

Change-Id: Id2f507d6b15da40bab178f2754c7b11d64ff5ddf
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1293133
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: James Chao <james_chao@asus.corp-partner.google.com>
Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>

1 files changed, 10 insertions, 0 deletions

diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index 6ab644912f..12ec22f894 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -200,6 +200,16 @@ static void clock_set_pll(enum pll_freq_idx idx)
 		 * change PLL.
 		 */
 		IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | (1 << 7);
+#ifdef IT83XX_ESPI_INHIBIT_CS_BY_VCC_OFF
+		/*
+		 * On DX version, we have to turn off VCC before changing PLL
+		 * sequence or sequence will fail if CS# pin is low.
+		 *
+		 * The VCC power status will be treated as power-on later in
+		 * clock_init().
+		 */
+		IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0);
+#endif
 #endif
 		/* Update PLL settings. */
 		clock_pll_changed();