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author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-02-03 17:39:01 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-02-05 09:50:16 +0000 |
commit | f060100507d0d02a487e873a22c8ddfa8728d916 (patch) | |
tree | 34480d8ded9a2433726b4fa16e0314d22528c706 /chip/it83xx/clock.c | |
parent | 1e544609affc989a0b4bb75d69659d6a86291ec3 (diff) | |
download | chrome-ec-f060100507d0d02a487e873a22c8ddfa8728d916.tar.gz |
TCPMv1: Don't turn off pd module clock if rx enabled
Plug in type-c adapter in G3 power state. Because the
SLEEP_MASK_USB_PD won't be set before we receive the SRC_Cap
from SRC in SNK_Discovery state, but at waiting SRC_Cap this
period time we will enter deep sleep mode and turns pd module
clock off. This will cause TCPC miss the SRC_Cap message from
SRC, then our PD_T_SINK_WAIT_CAP timer timeout and tx hard reset.
So I add a configuration: SLEEP_MASK_USB_PD is set only by
it83xx driver, so that SLEEP_MASK_USB_PD value won't be overwritten
by set_state() function in usb_pd_prtocol.c. If one of the port TCPC
Rx is enabled, chip will not go to deep sleep, but chip can go to doze
mode that pd module clock won't be turned off only mcu core clock off.
if all ports are nothing plug-in, the chip can go to deep sleep.
BUG=none
BRANCH=none
TEST=TCPC doesn't miss any message from partner:
-in SNK_DISCOVERY and power G3 state on board ampton.
-in SRC_DISCOVERY and power S0 state on board it8xxx2_evb.
Change-Id: I9639523e2ca180809f0f74f24321d06e7b3a04c2
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1990935
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Diffstat (limited to 'chip/it83xx/clock.c')
-rw-r--r-- | chip/it83xx/clock.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index 28827d11eb..00acf8864e 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -407,13 +407,22 @@ static void clock_htimer_enable(void) static int clock_allow_low_power_idle(void) { + /* + * Avoiding using low frequency clock run the same count as awaken in + * sleep mode, so don't go to sleep mode before timer reload count. + */ if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0))) return 0; + /* If timer interrupt status is set, don't go to sleep mode. */ if (*et_ctrl_regs[EVENT_EXT_TIMER].isr & et_ctrl_regs[EVENT_EXT_TIMER].mask) return 0; + /* + * If timer is less than 250us to expire, then we don't go to sleep + * mode. + */ #ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES if (EVENT_TIMER_COUNT_TO_US(ext_observation_reg_read(EVENT_EXT_TIMER)) < #else @@ -422,11 +431,17 @@ static int clock_allow_low_power_idle(void) SLEEP_SET_HTIMER_DELAY_USEC) return 0; + /* + * We calculate 32bit free clock overflow counts for 64bit value, + * if clock almost reach overflow, we don't go to sleep mode for + * avoiding miss overflow count. + */ sleep_mode_t0 = get_time(); if ((sleep_mode_t0.le.lo > (0xffffffff - SLEEP_FTIMER_SKIP_USEC)) || (sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC)) return 0; + /* If we are waked up by console, then keep awake at least 5s. */ if (sleep_mode_t0.val < console_expire_time.val) return 0; |