diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2018-07-10 13:54:20 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-11 08:40:13 -0700 |
| commit | 87671e2e70503e0fccf668c733fefe35aaa999b4 (patch) | |
| tree | f5c415331d3e3e3f3c029d4e224467adcf859fe0 /chip/it83xx/config_chip.h | |
| parent | 56f742bed06c2247803b198875247875d02632a4 (diff) | |
| download | chrome-ec-87671e2e70503e0fccf668c733fefe35aaa999b4.tar.gz | |
it83xx: IT8320 DX version compatibility
[espi]:
The supported maximum frequency of slave is adjustable and we
set it at 66MHz at initialization (the same as Bx version).
[gpio]:
All GPIOs support interrupt on rising, falling, and either edge.
More GPIOs support 1.8v input.
[irq]:
Enable newly added interrupts.
[registers]:
Remove unused declaration.
[system]:
Watchdog reset supports resetting the full EC domain function
(include write protect setting).
BUG=none
BRANCH=none
TEST=[espi]:
Ensure the eSPI frequency is able to work at 50 MHz on small
core CPU.
[gpio]:
The settings of input voltage 1.8v selection and both edge interrupt
registers are matched to the declarations of GPIO signal in gpio.inc.
[system]:
The console command "reboot hard" is able to unprotected the flash.
(testing failed)
Change-Id: I053d8a59a9e90d28e2f2c9b79675ea84425f4959
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1113166
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/config_chip.h')
| -rw-r--r-- | chip/it83xx/config_chip.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h index 5e7a501a8f..334fbbdedd 100644 --- a/chip/it83xx/config_chip.h +++ b/chip/it83xx/config_chip.h @@ -64,11 +64,31 @@ */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_ERASE_SIZE +#if defined(CHIP_VARIANT_IT8320BX) /* This is the physical size of the flash on the chip. We'll reserve one bank * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware * doesn't support a write-protect pin, and if we make the write-protection * permanent, it can't be undone easily enough to support RMA. */ #define CONFIG_FLASH_SIZE 0x00040000 +#elif defined(CHIP_VARIANT_IT8320DX) +#define CONFIG_FLASH_SIZE 0x00080000 +/* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */ +#define IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE +/* Watchdog reset supports hardware reset. */ +/* TODO(b/111264984): watchdog hardware reset function failed. */ +#undef IT83XX_ETWD_HW_RESET_SUPPORT +/* + * More GPIOs can be set as 1.8v input. + * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs. + */ +#define IT83XX_GPIO_1P8V_PIN_EXTENDED +/* All GPIOs support interrupt on rising, falling, and either edge. */ +#define IT83XX_GPIO_INT_FLEXIBLE +/* Enable interrupts of group 21 and 22. */ +#define IT83XX_INTC_GROUP_21_22_SUPPORT +#else +#error "Unsupported chip variant!" +#endif /****************************************************************************/ /* Define our flash layout. */ |