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| author | Caveh Jalali <caveh@chromium.org> | 2021-07-29 16:58:56 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-02 18:23:51 +0000 |
| commit | 32d6417df9b3c8c8dab1cc64a6989c0e444d67db (patch) | |
| tree | c162ddc33862cb3706f1011fd4b073979d22bd05 /chip/it83xx/config_chip_it8320.h | |
| parent | 640ed887a0eff557ca2bafed115f2813042cf90e (diff) | |
| download | chrome-ec-32d6417df9b3c8c8dab1cc64a6989c0e444d67db.tar.gz | |
COIL: chip/it83xx: Rename SPI MAX_FREQ config
This renames the ITE chip specific SPI speed configuration from
IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE to
IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE.
BRANCH=none
BUG=b:181607131
TEST=compare_build.sh matches
Change-Id: If2fcb086a8c35cf43ce15dc0963f3febbaa25f45
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061912
Commit-Queue: Harry Cutts <hcutts@chromium.org>
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Diffstat (limited to 'chip/it83xx/config_chip_it8320.h')
| -rw-r--r-- | chip/it83xx/config_chip_it8320.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h index 2918698e64..53f4a1cbd3 100644 --- a/chip/it83xx/config_chip_it8320.h +++ b/chip/it83xx/config_chip_it8320.h @@ -60,8 +60,11 @@ * (include EC clock frequency) is succeed even CS# is low. */ #define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED -/* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */ -#define IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE +/* + * The peripheral frequency is adjustable + * (bit[2-0] at register IT83XX_ESPI_GCAC1) + */ +#define IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE /* * TODO(b/111480168): eSPI HW reset can't be used because the DMA address * gets set incorrectly resulting in a memory access exception. |