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authorRuibin Chang <ruibin.chang@ite.com.tw>2020-01-20 17:59:40 +0800
committerCommit Bot <commit-bot@chromium.org>2020-01-22 07:34:51 +0000
commitadf6054e8eef567a6beb1d6894133446966c9e0a (patch)
treef56dcd3ef08dc2250f3d54c21b43370f6ddcb779 /chip/it83xx/config_chip_it8320.h
parent29e08659341945d5bda1ea323f64fab89d59197a (diff)
downloadchrome-ec-adf6054e8eef567a6beb1d6894133446966c9e0a.tar.gz
Cleanup: Add chip support pd physical port count configuration
Add chip support pd physical port count configuration. BUG=none BRANCH=none TEST=build all -j Change-Id: Ic473e53af44b5360aad6d2db74cf09ce5a3fa3e8 Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009537 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Diffstat (limited to 'chip/it83xx/config_chip_it8320.h')
-rw-r--r--chip/it83xx/config_chip_it8320.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h
index 3bbb2060ea..9fedd8258a 100644
--- a/chip/it83xx/config_chip_it8320.h
+++ b/chip/it83xx/config_chip_it8320.h
@@ -40,6 +40,8 @@
* of the control register (bit1 and bit5 at register IT83XX_USBPD_CCCSR).
*/
#define IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
+/* Chip IT8320BX actually has TCPC physical port count */
+#define IT83XX_USBPD_PHY_PORT_COUNT 2
/* For IT8320BX, we have to write 0xff to clear pending bit.*/
#define IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR
/* For IT8320BX, we have to read observation register of external timer two
@@ -83,6 +85,8 @@
#define IT83XX_INTC_PLUG_IN_SUPPORT
/* Chip Dx transmit status bit of PD register is different from Bx. */
#define IT83XX_PD_TX_ERROR_STATUS_BIT5
+/* Chip IT8320DX actually has TCPC physical port count */
+#define IT83XX_USBPD_PHY_PORT_COUNT 2
#else
#error "Unsupported chip variant!"
#endif