diff options
| author | tim <tim2.lin@ite.corp-partner.google.com> | 2020-04-28 10:45:35 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-29 11:06:51 +0000 |
| commit | 7f310174323b5e67292b90375447f3ec06998ff3 (patch) | |
| tree | 85f4b524c2d5394236718a448b90c15c1d698b54 /chip/it83xx/config_chip_it8xxx2.h | |
| parent | dc5f575bdd51a022eb8e6daac74ab348620c73ba (diff) | |
| download | chrome-ec-7f310174323b5e67292b90375447f3ec06998ff3.tar.gz | |
it83xx/adc: enabled GPIO alternate mode by default for pin into gpio.inc marked as MODULE_ADC
In the ADC initialization function, we should use the function
of gpio_config_module to set alternate function and declare
corresponding alternate function pins in gpio.inc. So we are
able to enable extra flag if needed.
BUG=none
BRANCH=none
TEST=testing the alternate function pins are normal
on the board of it83xx_evb, it8xxx2_evb, it8xxx2_pdevb
and reef_it8320.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I734b6ecc8f9343be65d9f29837e793b9574f8bdc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2160241
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/config_chip_it8xxx2.h')
| -rw-r--r-- | chip/it83xx/config_chip_it8xxx2.h | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index a14a87ae03..19437e5154 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -33,14 +33,7 @@ #define CONFIG_FLASH_SIZE 0x00080000 #define CONFIG_RAM_BASE 0x80080000 #define CONFIG_RAM_SIZE 0x00010000 -/* - * ADC control pin order change: - * ADC13 control pin GPL0 GPL1 - * ADC14 control pin GPL1 change to GPL2 - * ADC15 control pin GPL2 ---------> GPL3 - * ADC16 control pin GPL3 GPL0 - */ -#define IT83XX_CHIP_ADC_PIN_ORDER_CHANGE + /* Embedded flash is KGD */ #define IT83XX_CHIP_FLASH_IS_KGD /* Don't let internal flash go into deep power down mode. */ |