core:RISC-V / chip:IT83202

The IT83202 is an embedded controller with RISC-V core.
It supports maximum ram size to 256KB and internal flash to 1MB.

BUG=none
BRANCH=none
TEST=EC boots and test console commands (eg: taskinfo, version, sysjump...)
     on it83202 EVB.

Change-Id: I424c0d2878beb941c816363b5c7a3f57fda9fd13
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1588300
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>

1 files changed, 23 insertions, 8 deletions

diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c
index dd50dc3803..658819a193 100644
--- a/chip/it83xx/flash.c
+++ b/chip/it83xx/flash.c
@@ -8,6 +8,7 @@
 #include "flash.h"
 #include "flash_chip.h"
 #include "host_command.h"
+#include "intc.h"
 #include "system.h"
 #include "util.h"
 #include "watchdog.h"
@@ -95,9 +96,10 @@ void FLASH_DMA_CODE dma_reset_immu(int fill_immu)
 	/* Immu tag sram reset */
 	IT83XX_GCTRL_MCCR |= 0x10;
 	/* Make sure the immu(dynamic cache) is reset */
-	asm volatile ("dsb");
+	data_serialization_barrier();
+
 	IT83XX_GCTRL_MCCR &= ~0x10;
-	asm volatile ("dsb");
+	data_serialization_barrier();
 
 #ifdef IMMU_CACHE_TAG_INVALID
 	/*
@@ -122,18 +124,25 @@ void FLASH_DMA_CODE dma_reset_immu(int fill_immu)
 
 void FLASH_DMA_CODE dma_flash_follow_mode(void)
 {
-	/* Enter follow mode and FSCE# high level */
-	IT83XX_SMFI_ECINDAR3 = 0x4F;
+	/*
+	 * ECINDAR3-0 are EC-indirect memory address registers.
+	 *
+	 * Enter follow mode by writing 0xf to low nibble of ECINDAR3 register,
+	 * and set high nibble as 0x4 to select internal flash.
+	 */
+	IT83XX_SMFI_ECINDAR3 = (EC_INDIRECT_READ_INTERNAL_FLASH | 0xf);
+	/* Set FSCE# as high level by writing 0 to address xfff_fe00h */
 	IT83XX_SMFI_ECINDAR2 = 0xFF;
 	IT83XX_SMFI_ECINDAR1 = 0xFE;
 	IT83XX_SMFI_ECINDAR0 = 0x00;
+	/* EC-indirect memory data register */
 	IT83XX_SMFI_ECINDDR = 0x00;
 }
 
 void FLASH_DMA_CODE dma_flash_follow_mode_exit(void)
 {
-	/* Exit follow mode */
-	IT83XX_SMFI_ECINDAR3 = 0x00;
+	/* Exit follow mode, and keep the setting of selecting internal flash */
+	IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
 	IT83XX_SMFI_ECINDAR2 = 0x00;
 }
 
@@ -266,7 +275,7 @@ void FLASH_DMA_CODE dma_flash_cmd_aai_write(int addr, int wlen, uint8_t *wbuf)
 
 uint8_t FLASH_DMA_CODE dma_flash_indirect_fast_read(int addr)
 {
-	IT83XX_SMFI_ECINDAR3 = 0x40;
+	IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
 	IT83XX_SMFI_ECINDAR2 = (addr >> 16) & 0xFF;
 	IT83XX_SMFI_ECINDAR1 = (addr >> 8) & 0xFF;
 	IT83XX_SMFI_ECINDAR0 = (addr & 0xFF);
@@ -559,12 +568,16 @@ static void flash_code_static_dma(void)
 	interrupt_disable();
 
 	/* invalid static DMA first */
+	if (IS_ENABLED(CHIP_ILM_DLM_ORDER))
+		IT83XX_GCTRL_MCCR3 &= ~ILMCR_ILM2_ENABLE;
 	IT83XX_SMFI_SCAR2H = 0x08;
 
 	/* Copy to DLM */
 	IT83XX_GCTRL_MCCR2 |= 0x20;
-	memcpy((void *)SCAR2_ILM2_DLM14, (const void *)FLASH_DMA_START,
+	memcpy((void *)CHIP_RAMCODE_BASE, (const void *)FLASH_DMA_START,
 		IT83XX_ILM_BLOCK_SIZE);
+	if (IS_ENABLED(CHIP_ILM_DLM_ORDER))
+		IT83XX_GCTRL_MCCR3 |= ILMCR_ILM2_ENABLE;
 	IT83XX_GCTRL_MCCR2 &= ~0x20;
 
 	/*
@@ -595,6 +608,8 @@ int flash_pre_init(void)
 {
 	int32_t reset_flags, prot_flags, unwanted_prot_flags;
 
+	/* By default, select internal flash for indirect fast read. */
+	IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
 	flash_code_static_dma();
 
 	reset_flags = system_get_reset_flags();