driver/tcpm/it8xxx2: PD driver for chip it8xxx1/8xxx2

  Add PD driver for chip it8xxx1/8xxx2 series.

BRANCH=none
BUG=none
TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1
     (set cc toggle by console cmd):
     1.pin configuration
     console cmd "gpioget" check gpio settings.
     memory dump check cc pin alternate settings.
     2.Tx data error handle
     Message discard, No GoodCRC, Tx not enable, Timeout
     errors happen, corresponding INT will be triggered
     then do properly handle.
     3.basic pd connection
     SNK:connect with adaptor, request max power (15V,3A),
         state SNK_READY.
     SRC:enable DRP role,
         connect with dongle, provide power (5V,1.5A),
         source Vconn 5v, get ack of cable discover id,
         state SRC_READY.
     4.pd module disable
     SNK:connect with adapter.
         console cmd "hibernate sec", driver disable pd module,
         check still connection with adapter via dead battery rd.
         And when resume from hibernate, pd init can re-enable
         pd module, re-connect with adapter.
     SRC:connect with dongle.
         console cmd "hibernate sec", driver disable pd module,
         check cc pin (not Vconn source pin) volt power down
         to ~0v. And when resume from hibernate, pd init can
         re-enable pd module, re-connect with dongle.
     5.Tx hard reset
       console cmd "pd port hard", check hard reset message by
       lecroy analyzer.
     6.Tx cable reset
       check cable reset message by lecroy analyzer.
     7.SOP' enable
       SRC:connects to SNK via E-mark cable.
           Source Vconn successfully, and receives cable's ack
           of discover id request.
           Not source Vconn to cable, and receives nothing
           of discover id request (this isn't effect on
           request SNK flow).
     8.power role swap
       console cmd "pd port swap power", check pd protocol
       by lecroy.

Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538
Reviewed-by: Jett Rink <jettrink@chromium.org>

1 files changed, 36 insertions, 13 deletions

diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
index c753e095e0..cdef32384a 100644
--- a/chip/it83xx/gpio.c
+++ b/chip/it83xx/gpio.c
@@ -10,6 +10,7 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "intc.h"
+#include "it83xx_pd.h"
 #include "kmsc_chip.h"
 #include "registers.h"
 #include "switch.h"
@@ -633,6 +634,29 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal)
 	return EC_SUCCESS;
 }
 
+/* To prevent cc pins leakage, disables integrated cc module. */
+void it83xx_disable_cc_module(int port)
+{
+	/* Power down all CC, and disable CC voltage detector */
+	IT83XX_USBPD_CCGCR(port) |= USBPD_REG_MASK_DISABLE_CC;
+#if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
+	IT83XX_USBPD_CCCSR(port) |= USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR;
+#elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
+	IT83XX_USBPD_CCGCR(port) |= USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR;
+#endif
+	/*
+	 * Disconnect CC analog module (ex.UP/RD/DET/TX/RX), and
+	 * disconnect CC 5.1K to GND
+	 */
+	IT83XX_USBPD_CCCSR(port) |= (USBPD_REG_MASK_CC2_DISCONNECT |
+				     USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND |
+				     USBPD_REG_MASK_CC1_DISCONNECT |
+				     USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND);
+	/* Disconnect CC 5V tolerant */
+	IT83XX_USBPD_CCPSR(port) |= (USBPD_REG_MASK_DISCONNECT_POWER_CC2 |
+				     USBPD_REG_MASK_DISCONNECT_POWER_CC1);
+}
+
 void gpio_pre_init(void)
 {
 	const struct gpio_info *g = gpio_list;
@@ -642,20 +666,19 @@ void gpio_pre_init(void)
 
 	IT83XX_GPIO_GCR = 0x06;
 
-#ifndef CONFIG_USB_PD_TCPM_ITE83XX
-	/* To prevent cc pins leakage if we don't use pd module */
-	for (i = 0; i < IT83XX_USBPD_PHY_PORT_COUNT; i++) {
-		IT83XX_USBPD_CCGCR(i) = 0x1f;
-		/*
-		 * bit7 and bit3: Dis-connect CC with UP/RD/DET/TX/RX.
-		 * bit6 and bit2: Dis-connect CC with 5.1K resister to GND.
-		 * bit5 and bit1: Disable CC voltage detector.
-		 * bit4 and bit0: Disable CC.
-		 */
-		IT83XX_USBPD_CCCSR(i) = 0xff;
-		IT83XX_USBPD_CCPSR(i) = 0x66;
+	/*
+	 * To prevent cc pins leakage ...
+	 * If we don't use ITE TCPC: disable all ITE port cc modules.
+	 */
+	if (!IS_ENABLED(CONFIG_USB_PD_TCPM_ITE_ON_CHIP)) {
+		for (i = 0; i < IT83XX_USBPD_PHY_PORT_COUNT; i++) {
+			it83xx_disable_cc_module(i);
+			/* Dis-connect 5.1K dead battery resistor to CC */
+			IT83XX_USBPD_CCPSR(i) |=
+				(USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB |
+				 USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB);
+		}
 	}
-#endif
 
 #ifndef CONFIG_USB
 	/*