diff options
| author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-09-14 14:28:25 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-21 06:24:42 +0000 |
| commit | 0b0cc756fd05736a8904a1d297d66b74e4227452 (patch) | |
| tree | 468e8e7a2532700bd4450540ed774bc0590c9a45 /chip/it83xx/gpio.c | |
| parent | f0c3332979bfa2585a02a125da967e731870bee3 (diff) | |
| download | chrome-ec-0b0cc756fd05736a8904a1d297d66b74e4227452.tar.gz | |
chip/it83xx/gpio: correct bit setting
The cc2 bit field of CCCSR was repeated setting twice, so
I correct one of setting to cc1.
BUG=none
BRANCH=none
TEST=on board it8xxx2_evb,
check CCCSR register value by console
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I51b914a2dacefb2c5ed3b6c2be221d95f5724ce3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2417778
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Diffstat (limited to 'chip/it83xx/gpio.c')
| -rw-r--r-- | chip/it83xx/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c index f6951fd3e0..49c3dea103 100644 --- a/chip/it83xx/gpio.c +++ b/chip/it83xx/gpio.c @@ -653,7 +653,7 @@ void it83xx_disable_cc_module(int port) IT83XX_USBPD_CCCSR(port) |= (USBPD_REG_MASK_CC2_DISCONNECT | USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND | USBPD_REG_MASK_CC1_DISCONNECT | - USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND); + USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND); /* Disconnect CC 5V tolerant */ IT83XX_USBPD_CCPSR(port) |= (USBPD_REG_MASK_DISCONNECT_POWER_CC2 | USBPD_REG_MASK_DISCONNECT_POWER_CC1); |