diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2020-11-24 14:21:56 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-11-25 02:53:32 +0000 |
| commit | 7b6455ac961aea76cd70a5de4d1a958f5fb20749 (patch) | |
| tree | c8b5b9ba04181d2ef9dd31011dcd5c8b4d1e2c19 /chip/it83xx/i2c.c | |
| parent | a2a960834bcb7a86d3c30b052bec7f3f4297837b (diff) | |
| download | chrome-ec-7b6455ac961aea76cd70a5de4d1a958f5fb20749.tar.gz | |
it83xx/i2c: adjust Tlow and Thigh of 400kHz clock
This CL increased clock's Tlow to 1.51 us (1.3 us minimum) and
reduced Thigh to 1.087 us (0.6 us minimum).
BUG=b:163384683
BRANCH=none
TEST=i2c clock meet timing at 400kHz.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Id62b2370018ba2d41e0dbc715a4c40629260d66b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2557281
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Mike Goodey <mgoodey@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'chip/it83xx/i2c.c')
| -rw-r--r-- | chip/it83xx/i2c.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c index 905310ea12..2f1ef9e605 100644 --- a/chip/it83xx/i2c.c +++ b/chip/it83xx/i2c.c @@ -782,8 +782,8 @@ static void i2c_standard_port_timing_regs_400khz(int port) /* Port clock frequency depends on setting of timing registers. */ IT83XX_SMB_SCLKTS(port) = 0; /* Suggested setting of timing registers of 400kHz. */ - IT83XX_SMB_4P7USL = 0x5; - IT83XX_SMB_4P0USL = 0x1; + IT83XX_SMB_4P7USL = 0x6; + IT83XX_SMB_4P0USL = 0; IT83XX_SMB_300NS = 0x1; IT83XX_SMB_250NS = 0x2; IT83XX_SMB_45P3USL = 0x6a; |