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| author | Dino Li <dino.li@ite.com.tw> | 2016-01-27 13:44:58 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-01-28 00:02:03 -0800 |
| commit | a313fc9b1aff224f1229f22dafa7564516eb330c (patch) | |
| tree | f3acaed6efa6d3de6c694ae9e1f69f453f5f6c31 /chip/it83xx/intc.h | |
| parent | 347f516d8444a95e0506640f116e102828b89527 (diff) | |
| download | chrome-ec-a313fc9b1aff224f1229f22dafa7564516eb330c.tar.gz | |
chip: it83xx: fix EC interrupt vector registers issue
We have a limitation for EC interrupt vector registers.
System may read incorrect interrupt number in ISR so we need to add
a workaround to prevent it.
The following is a example that got incorrect interrupt number:
1. REG IVCTx = 0x10. (no interrupt pending)
2. EC INT6 interrupt occurs (IVCTx = 0x16) and jump to ISR.
3. Read interrupt vector register to determine interrupt number.
4. Higher priority interrupt of same interrupt group occurs
(for example: INT134, IVCTx = 0x96) while the system is reading the
interrupt vector register for EC INT6, we may end up with an incorrect
interrupt number between 0x16 and 0x96.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. EC interrupts work normally: WUI (GPIO interrupt), timer, uart,
LPC, I2C, and PECI.
2. Console command 'taskinfo'.
Change-Id: I54e61f417ad506eb3b4cd5d0652f64eed9a28a17
Reviewed-on: https://chromium-review.googlesource.com/322097
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/it83xx/intc.h')
| -rw-r--r-- | chip/it83xx/intc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h index 39d8653819..73c69b3c96 100644 --- a/chip/it83xx/intc.h +++ b/chip/it83xx/intc.h @@ -8,6 +8,7 @@ #ifndef __CROS_EC_INTC_H #define __CROS_EC_INTC_H +int intc_get_ec_int(void); void lpc_kbc_ibf_interrupt(void); void lpc_kbc_obe_interrupt(void); void pm1_ibf_interrupt(void); |