diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2018-07-13 14:53:57 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-16 10:22:00 -0700 |
| commit | 1247315ffe057bc546339c53171a23021ee4204f (patch) | |
| tree | 7d1222e917c571bee346ad0fcfd5b68ff7b116d7 /chip/it83xx/registers.h | |
| parent | 47de1e86750736f6e410e359b8f5980811be3556 (diff) | |
| download | chrome-ec-1247315ffe057bc546339c53171a23021ee4204f.tar.gz | |
tcpm: it83xx: IT8320 family compatibility
The bit7 and bit3 at UFPVDR register are reserved on BX version.
But in DX version, these two bits are used to get the result of
fast swap voltage comparing in UFP mode. So we change to mask
three bits only.
Add the support of two TX SOP type on the DX version.
(Debug SOP' and Debug SOP'')
On BX version, cc1/cc2 voltage detector function is enabled by bit1
or bit5 at register CCCSR.
But on DX version, the bit1 will control both cc1 and cc2.
So we create an option for this change.
BUG=none
BRANCH=none
TEST=Plug USB-C power adapter and USB-C to hdmi adapter, both work.
Change-Id: If881ef54145f211f7d48a971f56a6118487d9eed
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1119729
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index a62753c9b1..b91c18817e 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1174,6 +1174,20 @@ enum i2c_channels { #define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p)+0x04) #define USBPD_REG_MASK_DISABLE_CC (1 << 4) #define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x05) +#ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT +#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT ((1 << 3) | (1 << 1)) +#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT ((1 << 7) | (1 << 5)) +#else +#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT (1 << 3) +#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT (1 << 7) +#endif +#define USBPD_CC1_DISCONNECTED(p) \ + ((IT83XX_USBPD_CCCSR(p) | IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) & \ + ~IT83XX_USBPD_REG_MASK_CC2_DISCONNECT) +#define USBPD_CC2_DISCONNECTED(p) \ + ((IT83XX_USBPD_CCCSR(p) | IT83XX_USBPD_REG_MASK_CC2_DISCONNECT) & \ + ~IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) + #define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p)+0x06) #define USBPD_REG_MASK_DISCONNECT_POWER_CC2 (1 << 5) #define USBPD_REG_MASK_DISCONNECT_POWER_CC1 (1 << 1) |