diff options
| author | tim <tim2.lin@ite.corp-partner.google.com> | 2020-09-25 09:09:18 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-30 05:11:38 +0000 |
| commit | 5e4dbc7023d1fbf2e6ce56ace6ad16c2dd4e50fc (patch) | |
| tree | 9065078bf51171e78abd683699df7ef5a5fda4d9 /chip/it83xx/registers.h | |
| parent | 16787760844b62aa1e1d40cc8e9b7d72ce046dc1 (diff) | |
| download | chrome-ec-5e4dbc7023d1fbf2e6ce56ace6ad16c2dd4e50fc.tar.gz | |
it83xx/flash: the configuration only used by N8 core
We need to set the 56k~60k region to DLM on N8 core only.
After copying data into it, we will disable the region
and be the ram code section.
BUG=none
BRANCH=none
TEST=use console commands of #flasherase and #flashwrite to
erase and write are normal on the board of reef_it8320(N8)
it8xxx2_evb(risc-v).
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I9e42329d2e9d614640b668a0b75606f45268b83e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428348
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 3c7202a698..7f70724864 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -981,6 +981,7 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_EPLR REG8(IT83XX_GCTRL_BASE+0x37) #define IT83XX_GCTRL_IVTBAR REG8(IT83XX_GCTRL_BASE+0x41) #define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44) +#define IT83XX_DLM14_ENABLE BIT(5) #define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) #define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) #define IT83XX_GCTRL_WMCR REG8(IT83XX_GCTRL_BASE+0x4C) |