diff options
| author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-06-03 14:08:42 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-10-14 06:10:48 +0000 |
| commit | a57076ce03b3aa43d5cf62371649a7e9a28667e2 (patch) | |
| tree | 3de7bcd25f17068b0b58fa0667f188a5a806542f /chip/it83xx/registers.h | |
| parent | 11053f40043229b98ab7cb6be0325ab483a5d9e5 (diff) | |
| download | chrome-ec-a57076ce03b3aa43d5cf62371649a7e9a28667e2.tar.gz | |
it83xx/KB/GPIO: support keyboard GPIO output mode
These pins could be used as GPIO input, and they can
be configured as GPIO output as well. So we made this
patch to support it.
BRANCH=none
BUG=b:170699805
TEST=On board it8xxx2_evb
1.GPIO only: set/get level properly at GPIO mode.
2.GPIO and alternate mix: KSI input low and KSO GPIO level
not change
On board reef_it8320
1.keyboard scan function still work fine.
Change-Id: I2098812649f2e3ee9a8718d0d75e541ce3f14338
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2182128
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index f8e73f8887..ea344b35ec 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -805,7 +805,16 @@ enum { #endif GPIO_PORT_COUNT, - /* NOTE: Support GPIO input only if KSO/KSI pins are used as GPIO. */ + /* + * NOTE: support flags when KSI/KSO are configured as GPIO + * 1) it8320bx: + * output: GPIO_OUTPUT, GPIO_OPEN_DRAIN, GPIO_HIGH, GPIO_LOW + * input: GPIO_INPUT + * 2) it8320dx, it8xxx1, and it8xxx2: + * output: GPIO_OUTPUT, GPIO_OPEN_DRAIN(always internal pullup), + * GPIO_HIGH, GPIO_LOW + * input: GPIO_INPUT, GPIO_PULL_UP + */ /* KSI[7-0] GPIO data mirror register. */ GPIO_KSI, /* KSO[15-8] GPIO data mirror register. */ @@ -817,11 +826,11 @@ enum { }; struct gpio_reg_t { - /* GPIO port data register (bit mapping to pin) */ + /* GPIO and KSI/KSO port data register (bit mapping to pin) */ uint32_t reg_gpdr; - /* GPIO port data mirror register (bit mapping to pin) */ + /* GPIO and KSI/KSO port data mirror register (bit mapping to pin) */ uint32_t reg_gpdmr; - /* GPIO port output type register (bit mapping to pin) */ + /* GPIO and KSI/KSO port output type register (bit mapping to pin) */ uint32_t reg_gpotr; /* GPIO port control register (byte mapping to pin) */ uint32_t reg_gpcr; @@ -849,9 +858,9 @@ static const struct gpio_reg_t gpio_group_to_reg[] = { [GPIO_Q] = { 0x00F03E03, 0x00F03E63, 0x00F03E73, 0x00F03E20 }, [GPIO_R] = { 0x00F03E04, 0x00F03E64, 0x00F03E74, 0x00F03E28 }, #endif - [GPIO_KSI] = { 0x00F01D09, 0x00F01D09, -1, -1 }, - [GPIO_KSO_H] = { 0x00F01D0C, 0x00F01D0C, -1, -1 }, - [GPIO_KSO_L] = { 0x00F01D0F, 0x00F01D0F, -1, -1 }, + [GPIO_KSI] = { 0x00F01D08, 0x00F01D09, 0x00F01D26, -1 }, + [GPIO_KSO_H] = { 0x00F01D01, 0x00F01D0C, 0x00F01D27, -1 }, + [GPIO_KSO_L] = { 0x00F01D00, 0x00F01D0F, 0x00F01D28, -1 }, }; BUILD_ASSERT(ARRAY_SIZE(gpio_group_to_reg) == (COUNT)); @@ -1248,6 +1257,9 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) #define IT83XX_KBS_SDC2R REG8(IT83XX_KBS_BASE+0x23) #define IT83XX_KBS_SDC3R REG8(IT83XX_KBS_BASE+0x24) #define IT83XX_KBS_SDSR REG8(IT83XX_KBS_BASE+0x25) +#define IT83XX_KBS_KSIGPODR REG8(IT83XX_KBS_BASE+0x26) +#define IT83XX_KBS_KSOHGPODR REG8(IT83XX_KBS_BASE+0x27) +#define IT83XX_KBS_KSOLGPODR REG8(IT83XX_KBS_BASE+0x28) /* Shared Memory Flash Interface Bridge (SMFI) */ #define IT83XX_SMFI_BASE 0x00F01000 |