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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2017-02-15 17:06:37 -0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2017-02-27 19:19:49 +0000 |
| commit | 88e8ffeddba51d17001ca81c05df2179305d1d82 (patch) | |
| tree | 5537defb69fd99182f24c47365e6c426432a4e59 /chip/it83xx/registers.h | |
| parent | 841076f725473e3b650985b0443558173108807f (diff) | |
| download | chrome-ec-88e8ffeddba51d17001ca81c05df2179305d1d82.tar.gz | |
pd: Store PD active state in battery-backed memory
Our previous idea to cut Rd for many reset cases cannot work if cr50
consistently resets the EC by asserting the reset pin shortly after
power-on. Therefore, make a decision based upon whether battery-backed
memory indicates we previously negotiated a PD power contract as a sink.
If we previously did not negotiate a contract, or if power was removed
from the device (causing battery-backed memory to wipe) then we can
assume that we don't have an active power contract.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, run "cutoff" on the console, reattach AC, and verify
device successfully wakes. Also verify Rp is dropped on console 'reboot'
and F3 + power from RW.
Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443356
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446873
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index a90b5b72f2..e47c40e97c 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1075,7 +1075,11 @@ enum bram_indices { BRAM_IDX_RESET_FLAGS2 = 2, BRAM_IDX_RESET_FLAGS3 = 3, - /* index 4 ~ 7 are reserved */ + /* PD state data for CONFIG_USB_PD_DUAL_ROLE uses 2 bytes */ + BRAM_IDX_PD0 = 4, + BRAM_IDX_PD1 = 5, + + /* index 6 ~ 7 are reserved */ BRAM_IDX_SCRATCHPAD = 8, BRAM_IDX_SCRATCHPAD1 = 9, |