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authorDino Li <Dino.Li@ite.com.tw>2020-03-18 11:07:22 +0800
committerCommit Bot <commit-bot@chromium.org>2020-03-21 04:49:34 +0000
commit45e52682c29e0e08f25b0572ed16ad49cf559ee4 (patch)
treee4d6b9a95aa2f89cac51eef92399d672e885bc24 /chip/it83xx/registers.h
parent777f57c6f406292435dd7f836914e3f7ad435ed5 (diff)
downloadchrome-ec-45e52682c29e0e08f25b0572ed16ad49cf559ee4.tar.gz
chip/it8xxx2: add support IT81302 and IT81202
IT81302 (144-pins package) and IT81202 (128-pins package) chips belong to it8xxx2 family. So we apply the same chip options of it83202bx (except ADC pin order config option) and setup the correct flash size, ram size, and ram base. With this change, we are able to build FW image with IT81202 or IT81302 chip variant. BUG=none BRANCH=none TEST=EC boots and test console commands (version, sysinfo, sysjump, flasherase, flashwrite, and flashread) on IT81202 EVB. Hibernate EC and then press servo board's COLD_RST_L to reset EC. EC reboots. Change-Id: If351d561c61f635ebdb1e4e444e73e061a494c9a Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2072562 Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/registers.h')
-rw-r--r--chip/it83xx/registers.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index ff2467c606..2df14c9441 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -1297,7 +1297,11 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4))
#define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3))
#define IT83XX_SPI_RXF2FS BIT(2)
#define IT83XX_SPI_RXF1FS BIT(1)
+#ifdef CHIP_VARIANT_IT83202BX
#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE+0x08)
+#else
+#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE+0x0b)
+#endif
#define IT83XX_SPI_CPUWTFDB0 REG32(IT83XX_SPI_BASE+0x08)
#define IT83XX_SPI_FCR REG8(IT83XX_SPI_BASE+0x09)
#define IT83XX_SPI_SPISRTXF BIT(2)