driver/tcpm/it8xxx2: PD driver for chip it8xxx1/8xxx2

  Add PD driver for chip it8xxx1/8xxx2 series.

BRANCH=none
BUG=none
TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1
     (set cc toggle by console cmd):
     1.pin configuration
     console cmd "gpioget" check gpio settings.
     memory dump check cc pin alternate settings.
     2.Tx data error handle
     Message discard, No GoodCRC, Tx not enable, Timeout
     errors happen, corresponding INT will be triggered
     then do properly handle.
     3.basic pd connection
     SNK:connect with adaptor, request max power (15V,3A),
         state SNK_READY.
     SRC:enable DRP role,
         connect with dongle, provide power (5V,1.5A),
         source Vconn 5v, get ack of cable discover id,
         state SRC_READY.
     4.pd module disable
     SNK:connect with adapter.
         console cmd "hibernate sec", driver disable pd module,
         check still connection with adapter via dead battery rd.
         And when resume from hibernate, pd init can re-enable
         pd module, re-connect with adapter.
     SRC:connect with dongle.
         console cmd "hibernate sec", driver disable pd module,
         check cc pin (not Vconn source pin) volt power down
         to ~0v. And when resume from hibernate, pd init can
         re-enable pd module, re-connect with dongle.
     5.Tx hard reset
       console cmd "pd port hard", check hard reset message by
       lecroy analyzer.
     6.Tx cable reset
       check cable reset message by lecroy analyzer.
     7.SOP' enable
       SRC:connects to SNK via E-mark cable.
           Source Vconn successfully, and receives cable's ack
           of discover id request.
           Not source Vconn to cable, and receives nothing
           of discover id request (this isn't effect on
           request SNK flow).
     8.power role swap
       console cmd "pd port swap power", check pd protocol
       by lecroy.

Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538
Reviewed-by: Jett Rink <jettrink@chromium.org>

1 files changed, 2 insertions, 93 deletions

diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index af76705274..dfa8c2ad11 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -750,6 +750,8 @@
 #define IT83XX_GPIO_GPCRL1      REG8(IT83XX_GPIO_BASE+0x99)
 #define IT83XX_GPIO_GPCRL2      REG8(IT83XX_GPIO_BASE+0x9A)
 #define IT83XX_GPIO_GPCRL3      REG8(IT83XX_GPIO_BASE+0x9B)
+#define IT83XX_GPIO_GPCRP0      REG8(IT83XX_GPIO2_BASE+0x18)
+#define IT83XX_GPIO_GPCRP1      REG8(IT83XX_GPIO2_BASE+0x19)
 
 #define IT83XX_GPIO_GRC1        REG8(IT83XX_GPIO_BASE+0xF0)
 #define IT83XX_GPIO_GRC2        REG8(IT83XX_GPIO_BASE+0xF1)
@@ -1456,99 +1458,6 @@ enum i2c_channels {
 	IT83XX_I2C_PORT_COUNT,
 };
 
-/* USBPD Controller */
-#define IT83XX_USBPD_BASE(port)   (0x00F03700 + (0x100 * (port)))
-
-#define IT83XX_USBPD_GCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x0)
-#define USBPD_REG_MASK_SW_RESET_BIT           BIT(7)
-#define USBPD_REG_MASK_TYPE_C_DETECT_RESET    BIT(6)
-#define USBPD_REG_MASK_BMC_PHY                BIT(4)
-#define USBPD_REG_MASK_AUTO_SEND_SW_RESET     BIT(3)
-#define USBPD_REG_MASK_AUTO_SEND_HW_RESET     BIT(2)
-#define USBPD_REG_MASK_SNIFFER_MODE           BIT(1)
-#define USBPD_REG_MASK_GLOBAL_ENABLE          BIT(0)
-#define IT83XX_USBPD_PDMSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x01)
-#define USBPD_REG_MASK_SOPPP_ENABLE           BIT(7)
-#define USBPD_REG_MASK_SOPP_ENABLE            BIT(6)
-#define USBPD_REG_MASK_SOP_ENABLE             BIT(5)
-#define IT83XX_USBPD_CCGCR(p)     REG8(IT83XX_USBPD_BASE(p)+0x04)
-#define USBPD_REG_MASK_DISABLE_CC             BIT(4)
-#define IT83XX_USBPD_CCCSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x05)
-#ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
-#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT  (BIT(3) | BIT(1))
-#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT  (BIT(7) | BIT(5))
-#else
-#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT  BIT(3)
-#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT  BIT(7)
-#endif
-#define USBPD_CC1_DISCONNECTED(p) \
-	((IT83XX_USBPD_CCCSR(p) | IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) & \
-	~IT83XX_USBPD_REG_MASK_CC2_DISCONNECT)
-#define USBPD_CC2_DISCONNECTED(p) \
-	((IT83XX_USBPD_CCCSR(p) | IT83XX_USBPD_REG_MASK_CC2_DISCONNECT) & \
-	~IT83XX_USBPD_REG_MASK_CC1_DISCONNECT)
-
-#define IT83XX_USBPD_CCPSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x06)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC2   BIT(5)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC1   BIT(1)
-#define IT83XX_USBPD_DFPVDR(p)    REG8(IT83XX_USBPD_BASE(p)+0x08)
-#define IT83XX_USBPD_UFPVDR(p)    REG8(IT83XX_USBPD_BASE(p)+0x09)
-#define IT83XX_USBPD_CCADCR(p)    REG8(IT83XX_USBPD_BASE(p)+0x0C)
-#define IT83XX_USBPD_ISR(p)       REG8(IT83XX_USBPD_BASE(p)+0x14)
-#define USBPD_REG_MASK_TYPE_C_DETECT           BIT(7)
-#define USBPD_REG_MASK_CABLE_RESET_DETECT      BIT(6)
-#define USBPD_REG_MASK_HARD_RESET_DETECT       BIT(5)
-#define USBPD_REG_MASK_MSG_RX_DONE             BIT(4)
-#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3)
-#define USBPD_REG_MASK_HARD_RESET_TX_DONE      BIT(2)
-#define USBPD_REG_MASK_MSG_TX_DONE             BIT(1)
-#define USBPD_REG_MASK_TIMER_TIMEOUT           BIT(0)
-#define IT83XX_USBPD_IMR(p)       REG8(IT83XX_USBPD_BASE(p)+0x15)
-#define IT83XX_USBPD_MTCR(p)      REG8(IT83XX_USBPD_BASE(p)+0x18)
-#define USBPD_REG_MASK_SW_RESET_TX_STAT        BIT(3)
-#define USBPD_REG_MASK_TX_BUSY_STAT            BIT(2)
-#define USBPD_REG_MASK_TX_DISCARD_STAT         BIT(2)
-#ifdef IT83XX_PD_TX_ERROR_STATUS_BIT5
-#define USBPD_REG_MASK_TX_ERR_STAT             BIT(5)
-#else
-#define USBPD_REG_MASK_TX_ERR_STAT             BIT(1)
-#endif
-#define USBPD_REG_MASK_TX_START                BIT(0)
-#define IT83XX_USBPD_MTSR0(p)     REG8(IT83XX_USBPD_BASE(p)+0x19)
-#define USBPD_REG_MASK_CABLE_ENABLE            BIT(7)
-#define USBPD_REG_MASK_SEND_HW_RESET           BIT(6)
-#define USBPD_REG_MASK_SEND_BIST_MODE_2        BIT(5)
-#define IT83XX_USBPD_MTSR1(p)     REG8(IT83XX_USBPD_BASE(p)+0x1A)
-#define IT83XX_USBPD_VDMMCSR(p)   REG8(IT83XX_USBPD_BASE(p)+0x1B)
-#define IT83XX_USBPD_MRSR(p)      REG8(IT83XX_USBPD_BASE(p)+0x1C)
-#define USBPD_REG_MASK_RX_MSG_VALID            BIT(0)
-#define IT83XX_USBPD_PEFSMR(p)    REG8(IT83XX_USBPD_BASE(p)+0x1D)
-#define IT83XX_USBPD_PES0R(p)     REG8(IT83XX_USBPD_BASE(p)+0x1E)
-#define IT83XX_USBPD_PES1R(p)     REG8(IT83XX_USBPD_BASE(p)+0x1F)
-#define IT83XX_USBPD_TDO(p)       REG32(IT83XX_USBPD_BASE(p)+0x20)
-#define IT83XX_USBPD_AGTMHLR(p)   REG8(IT83XX_USBPD_BASE(p)+0x3C)
-#define IT83XX_USBPD_AGTMHHR(p)   REG8(IT83XX_USBPD_BASE(p)+0x3D)
-#define IT83XX_USBPD_TMHLR(p)     REG8(IT83XX_USBPD_BASE(p)+0x3E)
-#define IT83XX_USBPD_TMHHR(p)     REG8(IT83XX_USBPD_BASE(p)+0x3F)
-#define IT83XX_USBPD_RDO0(p)      REG32(IT83XX_USBPD_BASE(p)+0x40)
-#define IT83XX_USBPD_RMH(p)       REG16(IT83XX_USBPD_BASE(p)+0x5E)
-#define IT83XX_USBPD_CCPSR0(p)    REG8(IT83XX_USBPD_BASE(p)+0x60)
-#define IT83XX_USBPD_BMCSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x64)
-#define IT83XX_USBPD_PDMHSR(p)    REG8(IT83XX_USBPD_BASE(p)+0x65)
-#ifdef IT83XX_INTC_PLUG_IN_SUPPORT
-#define IT83XX_USBPD_TCDCR(p)     REG8(IT83XX_USBPD_BASE(p)+0x67)
-#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT  BIT(7)
-#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR   BIT(4)
-#define USBPD_REG_PLUG_IN_OUT_SELECT           BIT(3)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE   BIT(1)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT      BIT(0)
-#endif //IT83XX_INTC_PLUG_IN_SUPPORT
-
-enum usbpd_port {
-	USBPD_PORT_A,
-	USBPD_PORT_B,
-};
-
 #define USB_VID_ITE 0x048d
 
 #define IT83XX_ESPI_BASE  0x00F03100