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| author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-04-10 17:53:06 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-16 10:21:56 +0000 |
| commit | da8728f5d2eb767f7419a5e913ba3009732ad185 (patch) | |
| tree | 9ca074524d750a8f50295279402e18f24727af6e /chip/it83xx/registers.h | |
| parent | 4cf22dc7c90da6431b8727699eb801dc492604f8 (diff) | |
| download | chrome-ec-da8728f5d2eb767f7419a5e913ba3009732ad185.tar.gz | |
it83xx/pwm: clear cycle timer1 high byte for using as 8-bit
The cycle timer1 of chip 8320 later series was enhanced from
8bits to 10bits resolution, and others are still 8bit resolution.
Because the cycle timer1 high byte default value is not zero,
we clear cycle timer1 high byte at init and use it as 8-bit
resolution like others.
BUG=none
BRANCH=none
TEST=on board it8xxx2_evb
1) console check: the register CTR1M value
2) oscilloscope check: the pwm output frequency same as
our setting on board level via prescaler c4.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I5b2f249bbf56d3fbded88401779715973434e5d9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2142850
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index febf5093c9..b5bcd59ca0 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1001,6 +1001,7 @@ enum clock_gate_offsets { #define IT83XX_PWM_PCSSGH REG8(IT83XX_PWM_BASE+0x0D) #define IT83XX_PWM_CR256PCSSG REG8(IT83XX_PWM_BASE+0x0E) #define IT83XX_PWM_PCSGR REG8(IT83XX_PWM_BASE+0x0F) +#define IT83XX_PWM_CTR1M REG8(IT83XX_PWM_BASE+0x10) #define IT83XX_PWM_F1TLRR REG8(IT83XX_PWM_BASE+0x1E) #define IT83XX_PWM_F1TMRR REG8(IT83XX_PWM_BASE+0x1F) #define IT83XX_PWM_F2TLRR REG8(IT83XX_PWM_BASE+0x20) |