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| author | tim <tim2.lin@ite.corp-partner.google.com> | 2020-07-07 18:30:15 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-07-10 05:41:02 +0000 |
| commit | 4223c72d3ba9ef5ca28feb4701f575444b702a53 (patch) | |
| tree | 9169c87993947574071ba236b18bbf46ea22f94a /chip/it83xx/registers.h | |
| parent | 776faf4e76a7dbc3b609eed86de2837af220d408 (diff) | |
| download | chrome-ec-4223c72d3ba9ef5ca28feb4701f575444b702a53.tar.gz | |
it83xx/spi: enable Rx byte reach(256 bytes) interrupt
When Rx received data reaches FIFO target count, the status of Rx byte
reach interrupt bit is set then start to parse transaction.
BUG=b:160662061
BRANCH=none
TEST=EC can receive more than 128 bytes(up to 256 bytes) from host.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I3e922265e35f5bc46e794e92adb1bede20f73498
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2284513
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 28e635a0a2..3f134e8bd5 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1299,10 +1299,9 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) #define IT83XX_SPI_RXF1OC BIT(3) #define IT83XX_SPI_RXFAR BIT(0) #define IT83XX_SPI_IMR REG8(IT83XX_SPI_BASE+0x04) -#define IT83XX_SPI_RFFIM BIT(7) +#define IT83XX_SPI_RX_REACH BIT(5) #define IT83XX_SPI_EDIM BIT(2) #define IT83XX_SPI_ISR REG8(IT83XX_SPI_BASE+0x05) -#define IT83XX_SPI_RXFIFOFULL BIT(7) #define IT83XX_SPI_ENDDETECTINT BIT(2) #define IT83XX_SPI_RXFSR REG8(IT83XX_SPI_BASE+0x07) #define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3)) |