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| author | Dino Li <Dino.Li@ite.com.tw> | 2020-04-07 15:51:36 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-28 06:17:28 +0000 |
| commit | 6430b8b4536758473cfe4c71ef6afaeaeecc9c63 (patch) | |
| tree | 02c4331bd387d5e7c972bba378d3e4535f3bda83 /chip/it83xx/registers.h | |
| parent | 156d34f4a27750a512f78894068cdd82a950192b (diff) | |
| download | chrome-ec-6430b8b4536758473cfe4c71ef6afaeaeecc9c63.tar.gz | |
it8xxx2: lpc/espi: mapping host I/O cycle to h2ram section
On it8xxx2 series, host I/O cycles are mapped to the first block
(0x80080000~0x80080fff) at default, and it is adjustable.
We should set the correct offset depends on the base address of
H2RAM section, so EC will be able to receive/handle commands from
host.
BUG=b:133460224
BRANCH=none
TEST=not yet. just check the register setting is correct (I/O cycles
are mapped to 0x80081000~0x80081fff) after EC initialization.
Change-Id: Ib9085181917712bf735b83487720f12c8cd7ca31
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2038223
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index b5bcd59ca0..d30d8c754e 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -974,6 +974,7 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) #define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) #define IT83XX_GCTRL_WMCR REG8(IT83XX_GCTRL_BASE+0x4C) +#define IT83XX_GCTRL_H2ROFSR REG8(IT83XX_GCTRL_BASE+0x53) /* bit[0] = 0 or 1 : disable or enable ETWD hardware reset */ #define ETWD_HW_RST_EN BIT(0) #define IT83XX_GCTRL_RVILMCR0 REG8(IT83XX_GCTRL_BASE+0x5D) |