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| author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-03-06 15:55:07 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-03-11 04:22:51 +0000 |
| commit | 18500f672d0dcc76c79c8975a014293d7c7e94db (patch) | |
| tree | 6a455552a6052c016102a872f7a1168bac623659 /chip/it83xx/registers.h | |
| parent | 788b6f46ddb78c139bc960e936050882530d591d (diff) | |
| download | chrome-ec-18500f672d0dcc76c79c8975a014293d7c7e94db.tar.gz | |
it83xx/adc: add voltage comparator feature
Add voltage comparator feature.
BUG=b:149094481
BRANCH=none
TEST=on board it83xx_evb,
1.set VCMP1 threshold 2.8v: external input 3v,
the INT would be triggered and ADC5 read the correctly voltage.
2.set VCMP0 threshold 0.2v: external input 0v,
the INT would be triggered and ADC5 read the correctly voltage.
Change-Id: I59510b1c6bd38004ff06e0fcbd2a671e895d59e3
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2062110
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 3eceda91de..ff2467c606 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1065,6 +1065,11 @@ enum clock_gate_offsets { #define IT83XX_ADC_ADCDVSTS REG8(IT83XX_ADC_BASE+0x44) #define IT83XX_ADC_VCMPSTS REG8(IT83XX_ADC_BASE+0x45) #define IT83XX_ADC_VCMP0CTL REG8(IT83XX_ADC_BASE+0x46) +#define ADC_VCMP_CMPEN BIT(7) +#define ADC_VCMP_CMPINTEN BIT(6) +#define ADC_VCMP_GREATER_THRESHOLD BIT(5) +#define ADC_VCMP_EDGE_TRIGGER BIT(4) +#define ADC_VCMP_GPIO_ACTIVE_LOW BIT(3) #define IT83XX_ADC_CMP0THRDATM REG8(IT83XX_ADC_BASE+0x47) #define IT83XX_ADC_CMP0THRDATL REG8(IT83XX_ADC_BASE+0x48) #define IT83XX_ADC_VCMP1CTL REG8(IT83XX_ADC_BASE+0x49) @@ -1086,6 +1091,23 @@ enum clock_gate_offsets { #define IT83XX_ADC_VCH16DATM REG8(IT83XX_ADC_BASE+0x6A) #define IT83XX_ADC_VCH16DATL REG8(IT83XX_ADC_BASE+0x6B) #define IT83XX_ADC_ADCDVSTS2 REG8(IT83XX_ADC_BASE+0x6C) +#define IT83XX_ADC_VCMPSTS2 REG8(IT83XX_ADC_BASE+0x6D) +#define IT83XX_ADC_VCMP3CTL REG8(IT83XX_ADC_BASE+0x6E) +#define IT83XX_ADC_CMP3THRDATM REG8(IT83XX_ADC_BASE+0x6F) +#define IT83XX_ADC_CMP3THRDATL REG8(IT83XX_ADC_BASE+0x70) +#define IT83XX_ADC_VCMP4CTL REG8(IT83XX_ADC_BASE+0x71) +#define IT83XX_ADC_CMP4THRDATM REG8(IT83XX_ADC_BASE+0x72) +#define IT83XX_ADC_CMP4THRDATL REG8(IT83XX_ADC_BASE+0x73) +#define IT83XX_ADC_VCMP5CTL REG8(IT83XX_ADC_BASE+0x74) +#define IT83XX_ADC_CMP5THRDATM REG8(IT83XX_ADC_BASE+0x75) +#define IT83XX_ADC_CMP5THRDATL REG8(IT83XX_ADC_BASE+0x76) +#define IT83XX_ADC_VCMP0CSELM REG8(IT83XX_ADC_BASE+0x77) +#define ADC_VCMP_VCMPCSELM BIT(0) +#define IT83XX_ADC_VCMP1CSELM REG8(IT83XX_ADC_BASE+0x78) +#define IT83XX_ADC_VCMP2CSELM REG8(IT83XX_ADC_BASE+0x79) +#define IT83XX_ADC_VCMP3CSELM REG8(IT83XX_ADC_BASE+0x7A) +#define IT83XX_ADC_VCMP4CSELM REG8(IT83XX_ADC_BASE+0x7B) +#define IT83XX_ADC_VCMP5CSELM REG8(IT83XX_ADC_BASE+0x7C) /* Digital to Analog Converter (DAC) */ #define IT83XX_DAC_BASE 0x00F01A00 |