diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2020-08-25 10:56:43 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-08-27 18:55:21 +0000 |
| commit | 7e894e7e180d62d26fb81804709aa7ff8f958e17 (patch) | |
| tree | c28c7b9c516da8bf918a0c5a2264f955f660fc15 /chip/it83xx/registers.h | |
| parent | b7707a936c79d86d6e57534ca6125acb7021e2f5 (diff) | |
| download | chrome-ec-7e894e7e180d62d26fb81804709aa7ff8f958e17.tar.gz | |
it83xx/system: Don't disable DBGR in system reset
Our current implementation will disable DBGR (debug mode) in system
reset, but this will break flashing sequence. So we make a change to
ensure flashing won't be broken under the above situation.
Note: DBGR is only applied to flashing sequence, a HW reset after
flashing will disable DBGR and allow normal system reset.
We also enable wait flashing sequence in this CL, so EC can check if
there’s a DBGR flag during initialization and proceed afterwards.
BUG=b:118584434, b:165515400
BRANCH=none
TEST=- The soft reset still works after flashing.
- EC can be flashed even if it is in continuous reboot loop.
Change-Id: I9cea2c4fef74de7afcffb203e02f79cb18a4c5bf
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1243878
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 56a4500bf6..3c7202a698 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -963,6 +963,8 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE+0x01) #endif #define IT83XX_GCTRL_CHIPVER REG8(IT83XX_GCTRL_BASE+0x02) +#define IT83XX_GCTRL_DBGROS REG8(IT83XX_GCTRL_BASE+0x03) +#define IT83XX_SMB_DBGR BIT(0) #define IT83XX_GCTRL_WNCKR REG8(IT83XX_GCTRL_BASE+0x0B) #define IT83XX_GCTRL_RSTS REG8(IT83XX_GCTRL_BASE+0x06) #define IT83XX_GCTRL_BADRSEL REG8(IT83XX_GCTRL_BASE+0x0A) |