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| author | tim <tim2.lin@ite.corp-partner.google.com> | 2020-03-31 14:42:58 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-02 09:25:58 +0000 |
| commit | 7dfdde8b60d02a350111552842db758fa1391307 (patch) | |
| tree | 67b91d0632db631e833a8b701732028f80743c24 /chip/it83xx/registers.h | |
| parent | 34dfe4c7df343eb656955c8f0ab230c1b450d7e7 (diff) | |
| download | chrome-ec-7dfdde8b60d02a350111552842db758fa1391307.tar.gz | |
it83xx/spi: enable auto reset rx fifo function
In this change, we enable IT83XX_SPI_AUTO_RESET_RX_FIFO. When CS#
deasserted, the rx fifo and fifo count can auto reset in time by the
hardware way to avoid the time delay caused.
And we removed the spi_chipset_startup and shutdown. we don't need to
disable the interrupt of GPIO_SPI0_CS via hook during chipset suspend
and enable it during chipset resume. Instead, when the interrupt of
GPIO_SPI0_CS occurs, we judge whether the chipset state is enabled and
then to disable deep sleep.
BUG=none
BRANCH=none
TEST=boot to kernel with it81202 on elm board.
Press the button to shutdown and resume testing
10 times are normal.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I263d63fa5c22ef430d8f807c694317b7496f238f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2100372
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Dino Li <Dino.Li@ite.com.tw>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 8eb7d20cb8..febf5093c9 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1288,6 +1288,10 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) #define IT83XX_SPI_TXFCMR BIT(2) #define IT83XX_SPI_TXFR BIT(1) #define IT83XX_SPI_TXFS BIT(0) +#define IT83XX_SPI_GCR2 REG8(IT83XX_SPI_BASE+0x03) +#define IT83XX_SPI_RXF2OC BIT(4) +#define IT83XX_SPI_RXF1OC BIT(3) +#define IT83XX_SPI_RXFAR BIT(0) #define IT83XX_SPI_IMR REG8(IT83XX_SPI_BASE+0x04) #define IT83XX_SPI_RFFIM BIT(7) #define IT83XX_SPI_EDIM BIT(2) |