diff options
| author | tim <tim2.lin@ite.corp-partner.google.com> | 2020-07-07 18:30:15 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-07-10 05:41:02 +0000 |
| commit | 4223c72d3ba9ef5ca28feb4701f575444b702a53 (patch) | |
| tree | 9169c87993947574071ba236b18bbf46ea22f94a /chip/it83xx/spi.c | |
| parent | 776faf4e76a7dbc3b609eed86de2837af220d408 (diff) | |
| download | chrome-ec-4223c72d3ba9ef5ca28feb4701f575444b702a53.tar.gz | |
it83xx/spi: enable Rx byte reach(256 bytes) interrupt
When Rx received data reaches FIFO target count, the status of Rx byte
reach interrupt bit is set then start to parse transaction.
BUG=b:160662061
BRANCH=none
TEST=EC can receive more than 128 bytes(up to 256 bytes) from host.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I3e922265e35f5bc46e794e92adb1bede20f73498
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2284513
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'chip/it83xx/spi.c')
| -rw-r--r-- | chip/it83xx/spi.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c index 0b4e7ce2c2..2989c12bef 100644 --- a/chip/it83xx/spi.c +++ b/chip/it83xx/spi.c @@ -22,7 +22,7 @@ #define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) #define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) -#define SPI_RX_MAX_FIFO_SIZE 128 +#define SPI_RX_MAX_FIFO_SIZE 256 #define SPI_TX_MAX_FIFO_SIZE 256 #define EC_SPI_PREAMBLE_LENGTH 4 @@ -244,8 +244,8 @@ void spi_slv_int_handler(void) /* Reset fifo and prepare to receive next transaction */ reset_rx_fifo(); #endif - /* Enable Rx FIFO full interrupt */ - IT83XX_SPI_IMR &= ~IT83XX_SPI_RFFIM; + /* Enable Rx byte reach interrupt */ + IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH; /* Ready to receive */ spi_set_state(SPI_STATE_READY_TO_RECV); /* @@ -258,20 +258,20 @@ void spi_slv_int_handler(void) } /* - * The status of Rx FIFO full interrupt bit is set, + * The status of Rx byte reach interrupt bit is set, * start to parse transaction. * There is a limitation that Rx FIFO starts dropping * data when the CPU access the the FIFO. So we will - * wait the data until Rx FIFO full then to parse. - * The Rx FIFO to full is dummy data generated by + * wait the data until Rx byte reach then to parse. + * The Rx FIFO to reach is dummy data generated by * generate clock that is not the bytes sent from * the host. */ - if (IT83XX_SPI_ISR & IT83XX_SPI_RXFIFOFULL) { - /* Disable Rx FIFO full interrupt */ - IT83XX_SPI_IMR |= IT83XX_SPI_RFFIM; + if (IT83XX_SPI_ISR & IT83XX_SPI_RX_REACH) { + /* Disable Rx byte reach interrupt */ + IT83XX_SPI_IMR |= IT83XX_SPI_RX_REACH; /* write clear slave status */ - IT83XX_SPI_ISR = IT83XX_SPI_RXFIFOFULL; + IT83XX_SPI_ISR = IT83XX_SPI_RX_REACH; /* Parse header for version of spi-protocol */ spi_parse_header(); } @@ -292,8 +292,8 @@ static void spi_init(void) /* Set dummy blcoked byte */ IT83XX_SPI_HPR2 = 0x00; /* Set FIFO data target count */ - IT83XX_SPI_FTCB1R = SPI_RX_MAX_FIFO_SIZE >> 8; - IT83XX_SPI_FTCB0R = SPI_RX_MAX_FIFO_SIZE; + IT83XX_SPI_FTCB1R = (SPI_RX_MAX_FIFO_SIZE >> 8) & 0xff; + IT83XX_SPI_FTCB0R = SPI_RX_MAX_FIFO_SIZE & 0xff; /* SPI slave controller enable */ IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN; #ifdef IT83XX_SPI_AUTO_RESET_RX_FIFO @@ -308,14 +308,14 @@ static void spi_init(void) #endif /* * Interrupt mask register (0b:Enable, 1b:Mask) - * bit7 : Rx FIFO full interrupt mask + * bit5 : Rx byte reach interrupt mask * bit2 : SPI end detection interrupt mask */ IT83XX_SPI_IMR &= ~IT83XX_SPI_EDIM; /* Reset fifo and prepare to for next transaction */ reset_rx_fifo(); - /* Enable Rx FIFO full interrupt */ - IT83XX_SPI_IMR &= ~IT83XX_SPI_RFFIM; + /* Enable Rx byte reach interrupt */ + IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH; /* Ready to receive */ spi_set_state(SPI_STATE_READY_TO_RECV); /* Interrupt status register(write one to clear) */ |