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authorCaveh Jalali <caveh@chromium.org>2021-07-29 17:12:46 -0700
committerCommit Bot <commit-bot@chromium.org>2021-08-02 18:23:58 +0000
commita7a96fc737e40f110bee0a33299c982cdebc7014 (patch)
tree5848c7931999dec7c8f1905a46358c848fc58a27 /chip/it83xx/spi.c
parent32d6417df9b3c8c8dab1cc64a6989c0e444d67db (diff)
downloadchrome-ec-a7a96fc737e40f110bee0a33299c982cdebc7014.tar.gz
COIL: chip/it83xx: Rename SPI IRQ config
This renames the ITE chip specific SPI IRQ config from IT83XX_IRQ_SPI_SLAVE to IT83XX_IRQ_SPI_PERIPHERAL. BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: Ib7a7674e6cf4f0bf81ee47b5f60225f77236f578 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061913 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
Diffstat (limited to 'chip/it83xx/spi.c')
-rw-r--r--chip/it83xx/spi.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c
index 465d588fc3..63f8e4247c 100644
--- a/chip/it83xx/spi.c
+++ b/chip/it83xx/spi.c
@@ -234,7 +234,7 @@ void spi_event(enum gpio_signal signal)
}
}
-void spi_slv_int_handler(void)
+void spi_peripheral_int_handler(void)
{
if (IS_ENABLED(CONFIG_BOOTBLOCK) &&
(IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL) &&
@@ -283,7 +283,7 @@ void spi_slv_int_handler(void)
}
/* Clear the interrupt status */
- task_clear_pending_irq(IT83XX_IRQ_SPI_SLAVE);
+ task_clear_pending_irq(IT83XX_IRQ_SPI_PERIPHERAL);
}
static void spi_init(void)
@@ -344,8 +344,8 @@ static void spi_init(void)
/* SPI peripheral enable (after settings are ready) */
IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN;
/* Enable SPI peripheral interrupt */
- task_clear_pending_irq(IT83XX_IRQ_SPI_SLAVE);
- task_enable_irq(IT83XX_IRQ_SPI_SLAVE);
+ task_clear_pending_irq(IT83XX_IRQ_SPI_PERIPHERAL);
+ task_enable_irq(IT83XX_IRQ_SPI_PERIPHERAL);
/* Enable SPI chip select pin interrupt */
gpio_clear_pending_interrupt(GPIO_SPI0_CS);
gpio_enable_interrupt(GPIO_SPI0_CS);