diff options
author | tim <tim2.lin@ite.corp-partner.google.com> | 2020-08-17 10:25:43 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-08-19 07:31:48 +0000 |
commit | bdee9264b270abc532366d2052094e4d1969ddbb (patch) | |
tree | e06920147b0729b5c22d187d25ebc4beca45fabb /chip/it83xx/spi.c | |
parent | 36e23f2576bb4d1bbe8cd3560c655bff26aedb61 (diff) | |
download | chrome-ec-bdee9264b270abc532366d2052094e4d1969ddbb.tar.gz |
it83xx/spi: change configuration to IS_ENABLED() style
BUG=none
BRANCH=none
TEST=No error on the command of get EC protocol info.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I08d87bd20e60520c891f1b99d78ff91c1e89b2cb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2359613
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip/it83xx/spi.c')
-rw-r--r-- | chip/it83xx/spi.c | 136 |
1 files changed, 67 insertions, 69 deletions
diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c index 30690d4140..1fb77f9c3b 100644 --- a/chip/it83xx/spi.c +++ b/chip/it83xx/spi.c @@ -242,14 +242,12 @@ void spi_slv_int_handler(void) * EC responded data, then AP ended the transaction. */ if (IT83XX_SPI_ISR & IT83XX_SPI_ENDDETECTINT) { -#ifndef IT83XX_SPI_AUTO_RESET_RX_FIFO /* Reset fifo and prepare to receive next transaction */ - reset_rx_fifo(); -#endif -#ifndef IT83XX_SPI_RX_VALID_INT + if (!IS_ENABLED(IT83XX_SPI_AUTO_RESET_RX_FIFO)) + reset_rx_fifo(); /* Enable Rx byte reach interrupt */ - IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH; -#endif + if (!IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) + IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH; /* Ready to receive */ spi_set_state(SPI_STATE_READY_TO_RECV); /* @@ -261,38 +259,39 @@ void spi_slv_int_handler(void) IT83XX_SPI_ISR = 0xff; } -#ifndef IT83XX_SPI_RX_VALID_INT - /* - * The status of Rx byte reach interrupt bit is set, - * start to parse transaction. - * There is a limitation that Rx FIFO starts dropping - * data when the CPU access the the FIFO. So we will - * wait the data until Rx byte reach then to parse. - * The Rx FIFO to reach is mock data generated by - * generate clock that is not the bytes sent from - * the host. - */ - if (IT83XX_SPI_ISR & IT83XX_SPI_RX_REACH) { - /* Disable Rx byte reach interrupt */ - IT83XX_SPI_IMR |= IT83XX_SPI_RX_REACH; - /* write clear slave status */ - IT83XX_SPI_ISR = IT83XX_SPI_RX_REACH; - /* Parse header for version of spi-protocol */ - spi_parse_header(); - } -#else - /* - * The status of Rx valid length interrupt bit is set that indicates - * reached target count(IT83XX_SPI_FTCB1R, IT83XX_SPI_FTCB0R) and the - * length of length field of the host requested data. - */ - if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) { - /* write clear slave status */ - IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI; - /* Parse header for version of spi-protocol */ - spi_parse_header(); + if (IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) { + /* + * The status of Rx valid length interrupt bit is set that + * indicates reached target count(IT83XX_SPI_FTCB1R, + * IT83XX_SPI_FTCB0R) and the length field of the host + * requested data. + */ + if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) { + /* write clear slave status */ + IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI; + /* Parse header for version of spi-protocol */ + spi_parse_header(); + } + } else { + /* + * The status of Rx byte reach interrupt bit is set, + * start to parse transaction. + * There is a limitation that Rx FIFO starts dropping + * data when the CPU access the the FIFO. So we will + * wait the data until Rx byte reach then to parse. + * The Rx FIFO to reach is mock data generated by + * generate clock that is not the bytes sent from + * the host. + */ + if (IT83XX_SPI_ISR & IT83XX_SPI_RX_REACH) { + /* Disable Rx byte reach interrupt */ + IT83XX_SPI_IMR |= IT83XX_SPI_RX_REACH; + /* write clear slave status */ + IT83XX_SPI_ISR = IT83XX_SPI_RX_REACH; + /* Parse header for version of spi-protocol */ + spi_parse_header(); + } } -#endif /* Clear the interrupt status */ task_clear_pending_irq(IT83XX_IRQ_SPI_SLAVE); @@ -300,18 +299,6 @@ void spi_slv_int_handler(void) static void spi_init(void) { -#ifdef IT83XX_SPI_RX_VALID_INT - struct ec_host_request cmd_head; - /* - * Target count means the size of host request. - * And plus extra 4 bytes because the CPU accesses FIFO base on word. - * If host requested data length is one byte, we need to align the - * data length to 4 bytes. - */ - int target_count = sizeof(cmd_head) + 4; - /* Offset of data_len member of host request. */ - int offset = (char *)&cmd_head.data_len - (char *)&cmd_head; -#endif /* Set SPI pins to alternate function */ gpio_config_module(MODULE_SPI, 1); /* @@ -322,30 +309,42 @@ static void spi_init(void) /* Set unused blocked byte */ IT83XX_SPI_HPR2 = 0x00; /* Set FIFO data target count */ -#ifdef IT83XX_SPI_RX_VALID_INT - IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff; - IT83XX_SPI_FTCB0R = target_count & 0xff; - /* The register setting can capture the length field of host request. */ - IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff; - IT83XX_SPI_TCCB0 = offset & 0xff; -#else - IT83XX_SPI_FTCB1R = (SPI_RX_MAX_FIFO_SIZE >> 8) & 0xff; - IT83XX_SPI_FTCB0R = SPI_RX_MAX_FIFO_SIZE & 0xff; -#endif -#ifdef IT83XX_SPI_RX_VALID_INT + if (IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) { + struct ec_host_request cmd_head; + /* + * Target count means the size of host request. + * And plus extra 4 bytes because the CPU accesses FIFO base on + * word. If host requested data length is one byte, we need to + * align the data length to 4 bytes. + */ + int target_count = sizeof(cmd_head) + 4; + /* Offset of data_len member of host request. */ + int offset = (char *)&cmd_head.data_len - (char *)&cmd_head; + + IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff; + IT83XX_SPI_FTCB0R = target_count & 0xff; + /* + * The register setting can capture the length field of host + * request. + */ + IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff; + IT83XX_SPI_TCCB0 = offset & 0xff; + } else { + IT83XX_SPI_FTCB1R = (SPI_RX_MAX_FIFO_SIZE >> 8) & 0xff; + IT83XX_SPI_FTCB0R = SPI_RX_MAX_FIFO_SIZE & 0xff; + } /* Rx valid length interrupt enabled */ - IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM; -#endif -#ifdef IT83XX_SPI_AUTO_RESET_RX_FIFO + if (IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) + IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM; /* * General control register2 * bit4 : Rx FIFO2 will not be overwrited once it's full. * bit3 : Rx FIFO1 will not be overwrited once it's full. * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high. */ - IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC - | IT83XX_SPI_RXFAR; -#endif + if (IS_ENABLED(IT83XX_SPI_AUTO_RESET_RX_FIFO)) + IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC + | IT83XX_SPI_RXFAR; /* * Interrupt mask register (0b:Enable, 1b:Mask) * bit5 : Rx byte reach interrupt mask @@ -354,10 +353,9 @@ static void spi_init(void) IT83XX_SPI_IMR &= ~IT83XX_SPI_EDIM; /* Reset fifo and prepare to for next transaction */ reset_rx_fifo(); -#ifndef IT83XX_SPI_RX_VALID_INT /* Enable Rx byte reach interrupt */ - IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH; -#endif + if (!IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) + IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH; /* Ready to receive */ spi_set_state(SPI_STATE_READY_TO_RECV); /* Interrupt status register(write one to clear) */ |