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| author | Dino Li <Dino.Li@ite.com.tw> | 2017-09-07 10:39:58 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-09-07 21:21:36 -0700 |
| commit | 7b96b2784d21dc47897ec1e6e22aa74afdaa4fa6 (patch) | |
| tree | f7aee6ffa931a143be33add64d1af3ff2944bf56 /chip/it83xx | |
| parent | 0898c7a63a4ccb0f11c1c61bb085d8d062f664ab (diff) | |
| download | chrome-ec-7b96b2784d21dc47897ec1e6e22aa74afdaa4fa6.tar.gz | |
it83xx: clock: support e-flash clock up to 48MHz
Default setting of embedded flash's clock is 24 or 32 MHz
and PLL is 48 or 96 MHz correspondingly.
And it8320 supports e-flash clock up to 48 MHz,so we add
a new config option to support it.
BRANCH=none
BUG=none
TEST=Run FAFT with e-flash 48MHz and test results are passed.
Change-Id: I096ae3abc8fec9bd7e0556c57605e87a31ac3b07
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/645466
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/it83xx')
| -rw-r--r-- | chip/it83xx/clock.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index b3fad35c9a..8b2c8882c9 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -118,10 +118,17 @@ const struct clock_pll_t clock_pll_ctrl[] = { */ /* PLL:24MHz, MCU:24MHz, Fnd(e-flash):24MHz */ [PLL_24_MHZ] = {24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2}, +#ifdef CONFIG_IT83XX_FLASH_CLOCK_48MHZ + /* PLL:48MHz, MCU:48MHz, Fnd:48MHz */ + [PLL_48_MHZ] = {48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5}, + /* PLL:96MHz, MCU:96MHz, Fnd:48MHz */ + [PLL_96_MHZ] = {96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb}, +#else /* PLL:48MHz, MCU:48MHz, Fnd:24MHz */ [PLL_48_MHZ] = {48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5}, /* PLL:96MHz, MCU:96MHz, Fnd:32MHz */ [PLL_96_MHZ] = {96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb}, +#endif }; static uint8_t pll_div_fnd; |