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authorTim Wawrzynczak <twawrzynczak@chromium.org>2022-04-27 11:22:01 -0600
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>2022-05-11 17:30:06 +0000
commit200542008dca0aba2490e9993333be430b5fda6f (patch)
tree0ae271ba489504f1e55582fcb36c92c8b226c286 /chip/it83xx
parent6f8dab1033786ac7071e48bc68add2b5ac271c82 (diff)
downloadchrome-ec-200542008dca0aba2490e9993333be430b5fda6f.tar.gz
treewide: Convert ESPI_DEFAULT_SCI_WIDTH_US to default VWIRE pulse width
In the corresponding bug, Intel has clarified that this SCI# pulse length requirement is actually for all virtual wires, therefore this patch renames CONFIG_ESPI_DEFAULT_SCI_WIDTH_US to CONFIG_ESPI_DEFAULT_VW_WIDTH_US to reflect its broader purpose. All pulses of virtual wire signals were converted to use this new pulse width config option, and all GPIO pulses were converted back to their original value (65 us). BUG=b:227367177 BRANCH=brya TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1225b3e436cd1dca71c93500538a201d008781b3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3610694 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'chip/it83xx')
-rw-r--r--chip/it83xx/lpc.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
index 1f38491084..29f92e9b94 100644
--- a/chip/it83xx/lpc.c
+++ b/chip/it83xx/lpc.c
@@ -138,7 +138,7 @@ static void lpc_generate_smi(void)
{
#ifdef CONFIG_HOST_INTERFACE_ESPI
espi_vw_set_wire(VW_SMI_L, 0);
- udelay(65);
+ udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
espi_vw_set_wire(VW_SMI_L, 1);
#else
gpio_set_level(GPIO_PCH_SMI_L, 0);
@@ -151,11 +151,11 @@ static void lpc_generate_sci(void)
{
#ifdef CONFIG_HOST_INTERFACE_ESPI
espi_vw_set_wire(VW_SCI_L, 0);
- udelay(CONFIG_ESPI_DEFAULT_SCI_WIDTH_US);
+ udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
espi_vw_set_wire(VW_SCI_L, 1);
#else
gpio_set_level(GPIO_PCH_SCI_L, 0);
- udelay(CONFIG_ESPI_DEFAULT_SCI_WIDTH_US);
+ udelay(65);
gpio_set_level(GPIO_PCH_SCI_L, 1);
#endif
}