cleanup: it83xx: pull pnpcfg_settings[] to the chip-level

With this change, we don't need to declare pnpcfg_settings[]
for each it83xx based board.

BUG=b:76022972
BRANCH=none
TEST=make buildall -j, boot to kernel on reef_it8320.

Change-Id: I39eb465ba7d6191dce4ab1a39787a2c925ec3b91
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1009544
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>

2 files changed, 90 insertions, 2 deletions

diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
index cb8f5d3365..31ed7b4595 100644
--- a/chip/it83xx/ec2i.c
+++ b/chip/it83xx/ec2i.c
@@ -11,6 +11,96 @@
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
+#include "util.h"
+
+/* PNPCFG settings */
+static const struct ec2i_t pnpcfg_settings[] = {
+	/* Select logical device 06h(keyboard) */
+	{HOST_INDEX_LDN, LDN_KBC_KEYBOARD},
+	/* Set IRQ=01h for logical device */
+	{HOST_INDEX_IRQNUMX, 0x01},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+
+	/* Select logical device 05h(mouse) */
+	{HOST_INDEX_LDN, LDN_KBC_MOUSE},
+	/* Set IRQ=0Ch for logical device */
+	{HOST_INDEX_IRQNUMX, 0x0C},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+
+	/* Select logical device 11h(PM1 ACPI) */
+	{HOST_INDEX_LDN, LDN_PMC1},
+	/* Set IRQ=00h for logical device */
+	{HOST_INDEX_IRQNUMX, 0x00},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+
+	/* Select logical device 12h(PM2) */
+	{HOST_INDEX_LDN, LDN_PMC2},
+	/* I/O Port Base Address 200h/204h */
+	{HOST_INDEX_IOBAD0_MSB, 0x02},
+	{HOST_INDEX_IOBAD0_LSB, 0x00},
+	{HOST_INDEX_IOBAD1_MSB, 0x02},
+	{HOST_INDEX_IOBAD1_LSB, 0x04},
+	/* Set IRQ=00h for logical device */
+	{HOST_INDEX_IRQNUMX, 0x00},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+
+	/* Select logical device 0Fh(SMFI) */
+	{HOST_INDEX_LDN, LDN_SMFI},
+	/* H2RAM LPC I/O cycle Dxxx */
+	{HOST_INDEX_DSLDC6, 0x00},
+	/* Enable H2RAM LPC I/O cycle */
+	{HOST_INDEX_DSLDC7, 0x01},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+
+	/* Select logical device 17h(PM3) */
+	{HOST_INDEX_LDN, LDN_PMC3},
+	/* I/O Port Base Address 80h */
+	{HOST_INDEX_IOBAD0_MSB, 0x00},
+	{HOST_INDEX_IOBAD0_LSB, 0x80},
+	{HOST_INDEX_IOBAD1_MSB, 0x00},
+	{HOST_INDEX_IOBAD1_LSB, 0x00},
+	/* Set IRQ=00h for logical device */
+	{HOST_INDEX_IRQNUMX, 0x00},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+	/* Select logical device 10h(RTCT) */
+	{HOST_INDEX_LDN, LDN_RTCT},
+	/* P80L Begin Index */
+	{HOST_INDEX_DSLDC4, P80L_P80LB},
+	/* P80L End Index */
+	{HOST_INDEX_DSLDC5, P80L_P80LE},
+	/* P80L Current Index */
+	{HOST_INDEX_DSLDC6, P80L_P80LC},
+#ifdef CONFIG_UART_HOST
+	/* Select logical device 2h(UART2) */
+	{HOST_INDEX_LDN, LDN_UART2},
+	/*
+	 * I/O port base address is 2F8h.
+	 * Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2.
+	 * See specification 7.24.4 for more detial.
+	 */
+	{HOST_INDEX_IOBAD0_MSB, 0x02},
+	{HOST_INDEX_IOBAD0_LSB, 0xF8},
+	/* IRQ number is 3 */
+	{HOST_INDEX_IRQNUMX, 0x03},
+	/*
+	 * Interrupt Request Type Select
+	 * bit1, 0: IRQ request is buffered and applied to SERIRQ.
+	 *       1: IRQ request is inverted before being applied to SERIRQ.
+	 * bit0, 0: Edge triggered mode.
+	 *       1: Level triggered mode.
+	 */
+	{HOST_INDEX_IRQTP, 0x02},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(pnpcfg_settings) == EC2I_SETTING_COUNT);
 
 /* EC2I access index/data port */
 enum ec2i_access {
diff --git a/chip/it83xx/ec2i_chip.h b/chip/it83xx/ec2i_chip.h
index 13102f6577..8802e3d0b8 100644
--- a/chip/it83xx/ec2i_chip.h
+++ b/chip/it83xx/ec2i_chip.h
@@ -164,8 +164,6 @@ struct ec2i_t {
 	uint8_t data_port;
 };
 
-extern const struct ec2i_t pnpcfg_settings[];
-
 /* EC2I write */
 enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data);